JPS61158191A - Hybrid integrated circuit board - Google Patents

Hybrid integrated circuit board

Info

Publication number
JPS61158191A
JPS61158191A JP59280074A JP28007484A JPS61158191A JP S61158191 A JPS61158191 A JP S61158191A JP 59280074 A JP59280074 A JP 59280074A JP 28007484 A JP28007484 A JP 28007484A JP S61158191 A JPS61158191 A JP S61158191A
Authority
JP
Japan
Prior art keywords
board
conductive
hybrid
integrated circuit
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59280074A
Other languages
Japanese (ja)
Inventor
保 中野
市川 岩夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59280074A priority Critical patent/JPS61158191A/en
Publication of JPS61158191A publication Critical patent/JPS61158191A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えば同一の混成集積回路が複数形成される
混成集積回路基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit board on which, for example, a plurality of identical hybrid integrated circuits are formed.

〔従来の技術〕[Conventional technology]

第3図は、混成集積回路(以下、ハイブリッドICとい
う)の生産工程の一例を示している。基板メーカーにお
いては、まず基板を用意し、フォトエツチング等の処理
で回路パターンを形成する。
FIG. 3 shows an example of a production process for a hybrid integrated circuit (hereinafter referred to as a hybrid IC). A board manufacturer first prepares a board and forms a circuit pattern through photoetching or other processing.

次に、抵抗ペーストの印刷、焼成をした後、レーデ−ト
リミングにより抵抗値を調整して印刷抵抗を形成する。
Next, after printing and firing the resistor paste, the resistance value is adjusted by radar trimming to form a printed resistor.

次に、′回路パターンの導通、抵抗の抵抗値等を検査し
て終る。また、この基板を使用するハイブリッドICの
生産メーカーでは、基板に半田り70−により部品を実
装し、その後検査して完成する。
Next, the conduction of the circuit pattern, the resistance value of the resistor, etc. are inspected. Further, manufacturers of hybrid ICs using this board mount components on the board by soldering 70-, and then inspect and complete the board.

この場合、実際には、基板は複数のハイブリッドICが
形成される複数の基板部、例えば第4図に示すようにA
1〜A6を有して形成され、生産メーカーで検査が終了
するまでハイブリッドICは集合状態で生産される。
In this case, the substrate actually includes a plurality of substrate parts on which a plurality of hybrid ICs are formed, for example, A as shown in FIG.
1 to A6, and the hybrid ICs are produced in an assembled state until inspection is completed by the manufacturer.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このように集合状態で生産が行なわれるとき。 When production is carried out in a collective state like this.

生産過程において、その集合の中の一部に不良が発生し
たとき、その取扱いが問題となる。即ち、集合全体を不
良とすると、生産の歩留りが著しく低下し、コストアッ
プにつながる。一方、その一部の不良を無視してそのま
ま生産を続けると、不良部に対して無駄な工数、費用を
かけることになり、コストアップにつながる。
During the production process, when a defect occurs in a part of the set, how to handle it becomes a problem. That is, if the entire set is defective, the production yield will drop significantly, leading to an increase in costs. On the other hand, if you ignore some of the defects and continue production as is, you will waste man-hours and money on the defective parts, leading to an increase in costs.

本発明はかかる点に鑑み、歩留りを低下させることなく
、しかも、不良部に対して無駄な工数、費用をかけるこ
とのないようにするために工夫されたハイブリッドIC
基板を提案せんとするものである。
In view of these points, the present invention provides a hybrid IC that is devised to avoid reducing the yield and also to avoid wasting man-hours and costs for defective parts.
This paper aims to propose a substrate.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は上述問題点を解決するため、複数の基板部A1
〜A6と余白部(3)とよりなると共に、余白部(31
K ?!数の基板部Al−A6に対応する数の良否判別
用の導電)4ターンa1〜a6が形成されるものである
In order to solve the above-mentioned problems, the present invention provides a plurality of substrate parts A1
~ Consists of A6 and margin section (3), and margin section (31
K? ! Four conductive turns a1 to a6 for quality determination are formed corresponding to the number of substrate parts Al-A6.

〔作用〕[Effect]

以上の構成において、例えば基板メーカーで不良部に対
応する導電ノ4ターン金切断しておく。生産メーカーで
は、その導通チェックをすることにより不良部を判別す
ることができ、不良部を除いて部品の実装が可能となる
In the above configuration, for example, a four-turn conductive metal cut corresponding to the defective part is cut at the board manufacturer. The manufacturer can identify the defective part by checking the continuity, and can then remove the defective part and mount the component.

〔実施例〕〔Example〕

以下、第1図を参照しながら本発明の一実施例について
説明しよう。
Hereinafter, one embodiment of the present invention will be described with reference to FIG.

同図において、A1〜A6は同一のハイブリッドICが
形成される基板部であり、(1)は回路/母ターンであ
り、(2)は印刷抵抗である。
In the figure, A1 to A6 are substrate parts on which the same hybrid IC is formed, (1) is a circuit/mother turn, and (2) is a printed resistor.

また、(3)は余白部であり、この余白部(3)には、
基板部人1〜八6に対応する数の導電・々ターンal〜
a6が形成される。尚、(4)はこれら導電パターンa
1〜a6の一方の端子であり、(51)〜(56)はこ
れら導電/#ターンa1〜a6の他方の端子である。
Also, (3) is a margin, and in this margin (3),
The number of conductive turns corresponding to the board members 1 to 86 is
a6 is formed. In addition, (4) refers to these conductive patterns a
1 to a6, and (51) to (56) are the other terminals of these conductive/# turns a1 to a6.

この場合、端子(41,(5rl〜(56)は回路パタ
ーン(1)が形成されると同時に同様に形成され、一方
、導電パターンa1〜a6は印刷抵抗(2)が形成され
ると同時に同じ材料を用いて同様に形成される。
In this case, the terminals (41, (5rl-(56)) are formed in the same way at the same time as the circuit pattern (1) is formed, while the conductive patterns a1-a6 are formed in the same way at the same time as the printed resistor (2). Similarly formed using materials.

本例は以上のように構成され、例えば基板メーカーでは
、検査時に回路ノ4ターン(1)の導通、抵抗(2)の
値をチェックし、不良の生じている基板部に対応する導
電パターンをレーデ−加工あるいは放電加工により切断
し、その状態で生産メーカーに納入する。
This example is configured as described above. For example, a board manufacturer checks the continuity of the circuit's 4 turns (1) and the value of the resistance (2) during inspection, and creates a conductive pattern corresponding to the defective part of the board. It is cut by radar machining or electric discharge machining and delivered to the manufacturer in that state.

生産メーカーでは、例えば第2図に示すように接触子(
6)を用いて、導電パターン町〜a6の導通チェックを
行ない、非導通の導電・臂ターンに対応する基板部は不
良部であると判別し、この情報を実装システム忙与え、
その不良部を除いて部品の実装を行なう。
For example, as shown in Figure 2, manufacturing manufacturers use contactors (
6) is used to check the continuity of the conductive pattern Machi~a6, determine that the board part corresponding to the non-conductive conductive/arm turn is a defective part, and send this information to the mounting system.
The parts are mounted after removing the defective parts.

このように、本例のように導電ノ々ターンa1〜a6が
形成されるものによれば、例えば基板メーカーにおいて
、基板部A1〜A6の一部に不良が生じている場合に、
集合全体を不良としなくて済み、歩留りの著しい低下を
回避できると共に、生産メーカーにおいては、不良部に
部品の実装をするという無駄な工程、費用を不要とでき
、生産されるハイブリッドICの生産コストの低減化を
図ることができる。
As described above, according to the structure in which the conductive turns a1 to a6 are formed as in this example, if a defect occurs in a part of the board parts A1 to A6 at a board manufacturer, for example,
It is not necessary to mark the entire assembly as defective, which avoids a significant drop in yield, and also eliminates the wasteful process and expense of mounting parts on defective parts for manufacturers, reducing the production cost of the hybrid IC produced. can be reduced.

また、本例によれば、導電・9ターンa1〜a6を回路
パターン(1)、抵抗(2)の形成と同時に形成でき、
また、導電パターンa1〜a6の切断は、例えばレーザ
ー加工で行なうことができ、何等特別な設備を必要とす
るものでなく、既存の設備を利用できる利益がある。ま
た、判別も接触子(6)による電気的導通チェックで容
易にできる利益がある。
Further, according to this example, the conductive 9 turns a1 to a6 can be formed simultaneously with the formation of the circuit pattern (1) and the resistor (2),
Further, the conductive patterns a1 to a6 can be cut by, for example, laser processing, and there is an advantage that existing equipment can be used without requiring any special equipment. Further, there is the advantage that discrimination can be easily performed by checking electrical continuity using the contactor (6).

尚、上述実施例によれば、導電、・臂ターンa1〜a6
は抵抗(2)と同材料のもので形成されたものであるが
、回路・ぐターン(1)と同時に同じ材料で形成しても
よい。ただし、切断が多少困難となる。
Incidentally, according to the above-mentioned embodiment, conductive, arm turns a1 to a6
is made of the same material as the resistor (2), but may be made of the same material at the same time as the circuit/gut (1). However, cutting is somewhat difficult.

また、上述実施例によれば、導電・々ターンal〜a6
は、基板メーカーの検査時における良否を示すも□ので
あるが、その他の工程における良否を示すものであって
もよく、また、各主意工程毎に各基板部A1〜A6の良
否を示す導電パターンを形成してもよい。例えば両面基
板である場合には、上述例の他に生産メーカーで片面の
部品実装後の検査による良否を示す導電・々ターンを形
成することが考えられる。
Further, according to the above-mentioned embodiment, the conductive/interturn al~a6
□ indicates the quality at the time of inspection by the board manufacturer, but it may also indicate the quality at other processes, and the conductive pattern indicates the quality of each board part A1 to A6 for each main process. may be formed. For example, in the case of a double-sided board, in addition to the above-mentioned example, it is conceivable that the manufacturer forms conductive turns that indicate the quality of the board by inspection after mounting components on one side.

また、導電パターン31〜a6の形状、材質は上述実施
例に限られないことは勿論である。
Moreover, it goes without saying that the shapes and materials of the conductive patterns 31 to a6 are not limited to those in the above-mentioned embodiments.

〔発明の効果〕〔Effect of the invention〕

以上述べた本発明によれば、余白部に、複数の基板部の
良否を表示する導電パターンが形成されるものであり、
例えば基板メーカーにおいて、基板部の一部に不良が生
じていても全体を不良としなくて済み、歩留りの著しい
低下を回避できると共に、生産メーカーにおいては不良
部に部品の実装をすることを回避でき、ハイブリッドI
Cの生産コストの低減化を図ることができる。
According to the present invention described above, a conductive pattern indicating the quality of a plurality of substrate parts is formed in the margin part,
For example, a board manufacturer can avoid a significant drop in yield by not having to judge the entire board as defective even if a part of the board is defective, and a production manufacturer can avoid mounting parts on the defective part. , Hybrid I
It is possible to reduce the production cost of C.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す構成図、第2図はその
説明のための図、第3図はハイブリッドICの生産工程
を示す図、第4図はノ・イブリッドIC基板の説明のた
めの図である。 (11は回路Aターン、(2)は印刷抵抗、(3)は余
白部、A1〜A6は基板部、a1〜a6は導電パターン
であ第2図
Fig. 1 is a configuration diagram showing an embodiment of the present invention, Fig. 2 is a diagram for explaining the same, Fig. 3 is a diagram showing the production process of a hybrid IC, and Fig. 4 is an explanation of a hybrid IC board. This is a diagram for (11 is the circuit A turn, (2) is the printed resistor, (3) is the margin area, A1 to A6 are the board parts, and a1 to a6 are the conductive patterns.

Claims (1)

【特許請求の範囲】[Claims] 複数の基板部と余白部とよりなると共に、上記余白部に
上記複数の基板部に対応する数の良否判別用の導電パタ
ーンが形成されてなる混成集積回回基板。
What is claimed is: 1. A hybrid integrated circuit board comprising a plurality of substrate parts and a blank area, and a number of conductive patterns for quality determination corresponding to the plurality of substrate parts are formed in the blank area.
JP59280074A 1984-12-28 1984-12-28 Hybrid integrated circuit board Pending JPS61158191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59280074A JPS61158191A (en) 1984-12-28 1984-12-28 Hybrid integrated circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59280074A JPS61158191A (en) 1984-12-28 1984-12-28 Hybrid integrated circuit board

Publications (1)

Publication Number Publication Date
JPS61158191A true JPS61158191A (en) 1986-07-17

Family

ID=17619937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59280074A Pending JPS61158191A (en) 1984-12-28 1984-12-28 Hybrid integrated circuit board

Country Status (1)

Country Link
JP (1) JPS61158191A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007287799A (en) * 2006-04-13 2007-11-01 Nitto Denko Corp Wiring circuit board aggregate sheet

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007287799A (en) * 2006-04-13 2007-11-01 Nitto Denko Corp Wiring circuit board aggregate sheet
US8017871B2 (en) 2006-04-13 2011-09-13 Nitto Denko Corporation Wired circuit board assembly sheet
US8362360B2 (en) 2006-04-13 2013-01-29 Nitto Denko Corporation Wired circuit board assembly sheet
US8487189B2 (en) 2006-04-13 2013-07-16 Nitto Denko Corporation Wired circuit board assembly sheet

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