JPS61145589A - Memory buildup system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention makes it possible to increase the capacity of each plane by the same capacity and increase the number of planes when in multiple plane mode. - This relates to a memory expansion method that allows all planes to be specified with consecutive addresses when set to mode.

[Prior art and problems]

Traditionally, video RAM (hereinafter referred to as VRAM) has been expanded by expanding the address area of a single plane to increase the number of monochrome screens, or by adding a color display plane using the color option, and then increasing the number of monochrome screens. A method has been realized in which the number of screens is increased when displaying in monochrome. However, a VR that has multiple planes of VRAM that can display color, and can increase the capacity of each plane by the same amount by adding more VRAMs, and at the same time can increase the number of planes.
No effective method for adding AM is known.

[Purpose of the invention]

The present invention is based on the above consideration, and is based on the above consideration.
The purpose of the present invention is to provide a memory expansion method that not only allows expansion of the memory, but also allows all planes, including the added plane, to be treated as a single plane that allows continuous address specification when displaying in monochrome. It is said that

[For this reason, the memory expansion method of the present invention includes a first address decoder having first to m-th output terminals, and first to m-th output terminals and 1' to m'-th output terminals. a second address decoder with a signal line L
1 to L6, the signal line / or the signal line, /, the logic circuit L1 to Lm-1, and the logic circuit DI ' to D
a-1', and the first address decoder is the first address decoder.
The second address decoder becomes active when the second control signal is a predetermined value, and the kth (k is 1 to m) of the first address decoder becomes active when the second control signal is a predetermined value. and the output terminal of the second address decoder are connected to the signal [, *, the output terminal of the second address decoder is connected to the signal line Lk', and the output terminal of the (x is engineering or m-1) logic circuit,
outputs the signal Hr= when the third control signal is a predetermined value, and outputs the signal line Lx when the third control signal is another predetermined value.

1 signal, and when the third control signal is a predetermined value, the Xth logic circuit D□' outputs the signal line I
, and when the third control signal is at another predetermined value, a signal on the signal line Lx+1' is output.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a diagram showing an overview of the present invention. In FIG. 1, Pl to P7+ represent memory planes, and ΔP represents incremental memory for each plane, respectively.

Figure 1(a) shows the case where multiple plane mode is specified, and the VRA when color display is performed on the display device.
Corresponds to M. The n planes from Pl to pH have the same capacity and can be accessed simultaneously by specifying the same address from a to al. Here■
As shown in , by adding VRAMs each having a capacity of ΔP by the same capacity, it is possible to expand the address to AIDS. Furthermore, as shown by ■, planes with the same capacity as each plane are p, 1. , to P7°, it is possible to add m planes. In addition, the capacity of each plane can be increased arbitrarily by ΔZ(a
It is also possible to perform up to io, ).

Figure 1 (bl indicates the case where single plane mode is specified, and is used for monochrome display on a display device or for VR
This corresponds to the case where the processor accesses the contents of AM. If I and H are added in FIG. 1(a) and set to single plane mode, P5. ΔP, P! , ΔP
,...,P7. ΔP, P□1゜ΔP,... , P,
, ΔP, the planes are arranged in the order of a, to a (**
*) Continuous addresses up to (!.S) can be specified.

FIG. 2 is a block diagram of one embodiment of the present invention.

In FIG. 2, 1 is a multiplexer, 2 and 3 are address decoders, 4 to 6 are control signal lines, 7 is an address bus from a processor (not shown), and 8 is from a display controller (not shown). 9 is the output bus from the multiplexer, 10 is the in-plane address bus, D8 (x stands for factory or m-1) is the logic circuit, D
x' is also a logic circuit, Q (k is 1 to m) is the output terminal of the decoder, Qk' is also the output terminal of the decoder, Lk and L
Each symbol indicates a signal line. In addition, P indicated with ■
, , or PII planes and the ΔpXm memories indicated by ■ correspond to the additional memory in FIG.

Multiplexer 1 selects an address on address bus 7 or 8 and sends the selected address to decoders 2 and 3. The output terminal Qk of the decoder 2 is a logic rO when the input address is in the range of a(k-1)i to aki.
Output J. The output terminal Q5 of the decoder 3 outputs the input address from a (k-1) (its)+1 to a
(k-1) (its) When in the range of +i, outputs "0". Also, the output terminal Qk of the decoder 3
', the input address is a (k-11(its)
. Outputs logic "0" when i++ or ak(is.).

When the signal (signal 4) on the control signal line 4 is logic "1", the decoder 2 is enabled to operate, and when the signal 5 is logic "1", the decoder 3 is enabled.

Output terminal Qj of decoder 2 (j=2.3...1m
) and the output terminal Q of the decoder 3 are connected to the signal line Lj. The output terminal Qj' of the decoder 3 is the signal line Lj
/It is connected to the. Logic circuit Dx (x=1.2.
..., m-1) has a signal at the first input terminal, but the second
The input terminal receives the signal 6, and the third input terminal receives the signal L
41 is input. A first input terminal of the logic circuit Dx' receives a signal l, a second input terminal receives a signal 6, and a third input terminal receives a signal l. , ′ are input. When the signal LI is logic "0", the plane P is ready for operation,
When the output of the logic circuit Dx is logic rOJ, the plane P
□ is ready for operation. Also, the signal / is logical
0'', the first incremental memory ΔP becomes operational and 1, and when the output of the logic circuit Dx' is logical 0, the X+1st incremental memory ΔP becomes operational.

FIG. 3 is a block diagram of one embodiment of the logic circuit.

In FIG. 3, 11 indicates a NAND circuit, and 12 indicates a NOR circuit. When the signal 6 is logic "1", the output of the NAND circuit 11 becomes logic "1", and the NOR
The logic value of the output of circuit 12 is equal to the logic value of signal L2. When the signal 6 is logic "0", the logic value of the output of the NAND circuit 11 becomes equal to the signal RI, and therefore the logic value of the output of the NOR circuit 12 also becomes equal to the logic value of the signal RI. In multiple plane mode, signal 6 is a logic "0" and in single mode, signal 6 is a logic "1". Other logic circuits also have the same configuration as logic circuit D+.

For multi-plane mode without incremental memory ΔP (corresponding to the case of color display), signal 4 is set to logic “1”.
”, signal 5 is logic “0′”, and signal 6 is logic “0”. Plane P+ or P, and expansion plane P *+
1 to Pyo can be accessed simultaneously by specifying the same address from al to a (.In the case of multiple plane mode using incremental memory ΔP, set signal 4 to logic "0" and set signal 5 to logic “1” and signal 6 to logic “0.” This selects decoder 3.
A signal 1' corresponding to an address from a i 4 + to a, - specifies ΔPXm memories. As a result, the capacity of each of the planes Pl to P6 is increased by ΔP, and address expansion from a to a i is realized.

In single plane mode without using incremental memory ΔP (corresponding to monochrome display or processor access),
The signal 4 is set to logic "1", the signal 5 is set to logic "O", and the signal 6 is set to logic "1". In this case, the output terminal Q of the decoder 2,
Output signals from planes P to Q serve as selection signals for selecting one of planes P to P. For single plane mode also using incremental memory ΔP, signal 4
is logic “0”, signal 5 is logic “1”, signal 6 is logic “1”
”. In this case, the output signal from the output terminal Q or QII of the decoder 3 becomes a selection signal for selecting one of the planes P1 to P, and the output terminal Q1
The output signal from ' to Q, ' is the incremental memory set ΔPX
This is a selection signal for selecting one of m. Signal L
I+L1', +L,,L,' are respectively a, or ai, ai+蒐 or ai, s, +'', a (
ass-11(its)+1 to a(□a-H(it
s) or it a (,1l-0o1,6 or a
0. , ) (!.,) address area, and all planes can be specified with consecutive addresses. Note that the present invention is also applicable to adding memory to devices other than display devices.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, additional memory can be used efficiently in multiple plane mode and single plane mode.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an overview of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is a block diagram of one embodiment of a logic circuit. P, to P 1141%...memory plane, Δ
P...incremental memory for each plane, one-way multiplexer, 2 and 3...address decoder, 4 to 6...control signal lines, 7...address bus from processor, 8 display control Address from device
Bus, 9... Output bus from multiplexer, 10.
...Intra-brane address bus, Dx (x is 1 to m
-1)...Logic circuit, Dx'...Logic circuit, Qk
(k is 1 to m)...Decoder output terminal, Qk
'...Decoder output terminal, Lk terminal, /...signal line, 11...NAND circuit, 12...NOR circuit.

Claims (1)

[Claims] a first address decoder having first to mth output terminals; a second address decoder having first to mth output terminals and first' to m'th output terminals; and a signal line L_1. to L_m and signal lines L_1' to L_
m', logic circuits D_1 to D_m_-_1, and logic circuits D_1' to D_m_-_1';
The address decoder becomes active when the first control signal is a predetermined value, the second address decoder becomes active when the second control signal is a predetermined value, and the k-th address decoder of the first address decoder becomes active when the second control signal is a predetermined value. (k is 1 to m) and the k-th output terminal of the second address decoder are signal lines L_
k, the k'th output terminal of the second address decoder is connected to the signal line L_k', and the xth (x is 1
to m-1) logic circuit D_x outputs the signal on the signal line L_1 when the third control signal is a predetermined value, and outputs the signal on the signal line L_x_+_1 when the third control signal is another predetermined value. The xth logic circuit D_x is configured to output
' is configured to output a signal on the signal line L_1' when the third control signal is a predetermined value, and output a signal on the signal line L_x_+_1' when the third control signal is another predetermined value. A memory expansion method that is characterized by: