JPS61129786A - Tape travelling quantity detecting device - Google Patents

Abstract

PURPOSE:To detect a tape travelling quantity with a high accuracy and to confirm always tape travelling direction information by detecting a phase to the second pulse to the second pulse of the counting of the counter, controlling an input to the counter of the first pulse and obtaining a tape travelling quantity detecting signal based upon the output of the counter. CONSTITUTION:A roller 30 is installed which rotatably contacts to a magnetic tape TP and rotates by travelling of the tape, a rotating detecting device 31 is installed to this, the first and second rotating pulses with a phase difference of 90 deg. obtained by this to a rotating detecting circuit 35, from the rotating detecting circuit 35 the first pulse and a tape travelling direction detecting signal corresponding to the front and rear edges of the rotating pulse is obtained. By reproducing a position signal 38 recorded in the length-wise direction to a side end of the tape TP with the second pulse generating means 41, the second pulse is obtained. A control circuit 8 controls the input to a counter 4 of the first pulse in accordance with the fact whether the phase to the second pulse of the counting of the counter 4 is a condensive phase or a lagging phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tape running amount detection device suitable for application to VTRs, audio tape recorders, and the like.

[Conventional technology]

Conventional tape running amount detection devices include the following. ■A roller is provided that contacts the magnetic tape and rotates as the tape runs, a rotation detector is attached to the roller, and the tape travel i detection pulse from this rotation detector drives a count display to determine the amount of tape travel. Display. ■Position signals (CT
L signal) is recorded, the tape is run, this position signal is reproduced by a magnetic head, and a tape running amount detection pulse from the magnetic head drives a counter display to display the tape running amount.

The device described in (2) has the advantage of continuously obtaining highly reliable tape running amount detection pulses, but if there is slippage between the tape and the roller or there is expansion or contraction of the tape, the tape running amount cannot be detected. This has the disadvantage that the pulse detection accuracy is reduced.

Although the device (2) improves the drawback of the device (2), “if there is a dropout in the reproduction of the position signal, the detection accuracy of the tape running amount detection pulse will still decrease.

Therefore, a tape running amount detection device has been proposed in which the accuracy of the tape running amount detection pulse is improved by combining the devices (1) and (2) (see Japanese Patent Publication No. 5B-9504).

The conventional tape running amount detecting device will be described below with reference to FIG. In the embodiment of the above-mentioned publication, a quinary counter is used, but in order to simplify the explanation, an octal counter will be used in this example. (4) is an octal up/down counter, and the clock input terminal is connected to the first counter by mechanical detection of tape running from the input terminal (1).
The pulse of is applied to the up/down switching signal input terminal,
A tape running direction detection signal based on mechanical detection of the tape running amount is supplied from the input terminal (2).

The signals supplied to the input terminals (1) and (2) are obtained as follows. That is, a rotation detector is attached to a roller that is in rolling contact with the magnetic tape and rotates as the tape runs, and a rotation pulse having a phase difference of 90 degrees is supplied to a rotation detection circuit. I'm trying to get a signal.

(5) is a logic circuit which receives the 22° and 21.2° digit output Q2 Qt Qo from the counter (4) and generates a pulse of 1 +W every cycle of the counter (4) to display the count display. (6), and also supplies a gate signal for noise removal to the reset/preset pulse generation circuit (7). Incidentally, the display device (6) also receives a tape running direction detection signal from the input terminal (2). This indicator (
6), the tape running distance is 9 minutes 1 second, frame (1/
30 seconds) format.

The reset/preset pulse generation circuit (7) receives the tape running direction detection signal from the input terminal (2) and the tape running direction detection signal from the input terminal (2).
3) receives the second pulse (gated by the above-mentioned gate signal) from the tape running, and supplies a reset and preset pulse to the counter (4) based on this.

The second pulse supplied to the input terminal (3) is a position signal CC recorded on the side edge of the tape at equal intervals in its longitudinal direction.
This is the reproduction signal of the TL signal) by the magnetic head.

In this case, the second pulse is a 30 Hz pulse when the tape runs at a constant speed. Therefore, the frequency of the first pulse is 240Hz when the tape is running at a constant speed.
(=30Hz x 8).

Next, the operation of the tape running amount detecting device shown in FIG. 8 will be explained with reference to FIG. 9 as well.

First, consider ignoring the second PAX to be supplied to the input terminal (3). In this way, when the tape runs in the positive direction and the counter (4) counts in the positive direction by the first pulse, the content of the count is expressed by converting the binary number into a decimal number as shown in FIG. 9A. As shown in , ・ ・ , 0.
1,2.3,4.5,6,7゜0, 1. 2. 3.
It changes like... Also, when the tape runs in the opposite direction and the counter (4) counts in the opposite direction by the first pulse, the counted contents are shown in Figure 9F when the binary number is converted into a decimal number. As shown...7,6.
5.4,3,2゜1.0.7,6. It changes like...

A pulse is supplied from the logic circuit (5) to the display (6) when the count content of the counter (4) changes from the maximum to the minimum or from the minimum to the maximum, that is, the most significant digit output Q2 of the counter (4). The value of is "1" - "0" or "0" - "1"
” occurs when the change occurs.

The gate signal (which gates the second pulse) supplied from the logic circuit (5) to the reset/preset pulse generation circuit (7) is applied to the counter (
It is a signal that becomes high level when the count content of 4) is 6-2 or 2-6, and becomes low level otherwise.

Next, consider also the second pulse supplied to the input terminal (3). When the tape is running in the forward direction and the counter (4) is counting in the forward direction as shown in Figure 9 by the first pulse, when the count is 7, as shown in Figure 9C. When the second pulse is generated as shown in Fig. 9, a reset pulse is supplied from the circuit (7) to the counter (4), and the count content is changed to O as shown in Fig. 9. From then on, the count content is 1.2. ,3. ..., and when the count reaches 0, a second pulse is generated as shown in FIG. 9C, but the count remains unchanged. And the ninth
As shown in Figure E, when the count content of the counter (4) changes from 7 to 0, a pulse is obtained from the logic circuit (5) and supplied to the count display (6), which displays each l increased.

Further, when the tape runs in the opposite direction and the counter (4) is counted in the opposite direction by the first pulse as shown in FIG. 9G, when the count is 1, the 9th When the second pulse is generated as shown in Figure C, a preset pulse is supplied from the circuit (7) to the counter (4), and the count is changed to 7 as shown in Figure 9G. The contents are 6. 5. 4 degrees, and when the count reaches 7, a second pulse is generated as shown in FIG. 9C, but the count remains unchanged. As shown in FIG. 9H, when the count content of the counter (4) changes from 1 to 7 and from 0 to 7, the logic circuit (5)
pulses are obtained from and supplied to the counting display (6);
The display is each decremented by one.

[Problem that the invention seeks to solve]

By the way, in the tape running amount detecting device shown in FIG. 8, the count content of the counter (4) that counts the first pulse is
Since it is changed by the pulse of , the tape running amount can be detected with high accuracy. On the other hand, however, such conventional devices have the disadvantage that, because the continuity of the number of stitches in the counter is lost, it may become impossible to obtain tape running direction information based on data transitions with minute resolution.

In view of these points, the present invention seeks to propose a tape running amount detection device that can detect the tape running amount with high precision and can also obtain tape running direction information based on data transitions with minute resolution. be.

[Means for solving problems]

The tape running amount detecting device according to the present invention includes a first pulse generating means (40) that mechanically detects the running of the tape and generates a first pulse, and a first pulse generating means (40) that reproduces a position signal recorded on the tape and generates a first pulse. a second pulse generating means for generating two pulses (
41), a counter (4) that counts the first pulse,
This counter (41 counts) detects the phase of the second pulse and controls the human power applied to the first pulse counter (4) depending on whether the phase is leading or lagging. The tape running amount detection signal is obtained based on the output of the counter (4).

[Effect]

According to the present invention, the counting phase of the counter (4) that counts the first pulse is corrected by the second pulse. This correction is performed by controlling the input of the first pulse to the counter (4) depending on whether the phase of the count of the counter (4) with respect to the second pulse is leading or lagging.

[Real deer example]

An embodiment of the present invention will be described below with reference to FIG. (4) is, for example, a quaternary up/down counter, and the first pulse from the mechanical detection of tape running from the input terminal (1) is input to its clock input terminal, and the up/down switching signal input terminal is input to its clock input terminal. A tape running direction detection signal based on mechanical detection of tape running is supplied from the terminal (2).

The signals supplied to the input terminals 1), +21 are obtained from the first pulse generating means (40) shown in FIG.

First, a roller (30) is provided which is in rolling contact with the magnetic tape TP and rotates as the tape runs, and a rotation detector (a rotating magnet (32) attached to the roller (30) via a shaft) is provided.
and magnetic heads (33) and (34)")
(31), and the first and second rotational pulses with a phase difference of 90° obtained from this (Fig. 4 A, B)
is supplied to the rotation detection circuit (35), and the rotation detection circuit (
35), the first pulse (120Hz) (FIG. 4C) and tape running direction detection signal (FIG. 4D) corresponding to the front and rear edges of the rotation pulses in FIGS. 4A and B are obtained. .

(3) is the input terminal for the second pulse. As shown in FIG. 3, the position signal (CTL signal) (corresponding to the start position of the odd field of the inclined track) (38) recorded on the side edge of the tape TP in its longitudinal direction is applied to the second pulse. This second pulse <30)1z) is obtained each time it is reproduced by the generating means (fixed magnetic throat) (41).

(8) is a control circuit that detects the phase of the count of the counter (4) with respect to the second pulse, and depending on whether the phase is leading or lagging, the counter (4) of the first pulse ). Below, this control circuit (8) will be explained. +11 is a prohibition circuit (prohibition gate) that prohibits input of the first pulse from the input terminal (1) to the counter (4). (11) is an addition circuit (OR gate) that adds another pulse to the first pulse input from the input terminal [11 to the counter (4). The input terminal (1) is connected to the clock input terminal of the counter (4) through the inhibit circuit OI and the adder circuit (11) in sequence.

(12) is a phase advance detection circuit, and the 21 from counter (4)
．． 2° output QL QO received the tape running direction detection signal from the input terminal (2) and the second pulse from the input terminal (3), and was latched by the second pulse of the output QIQo of the counter (4). It is determined whether the phase of the latch contents with respect to the second pulse is advanced or not, and when it is determined that the phase is advanced, the inhibition circuit (11 is controlled) so as to inhibit one first pulse. .

(I3) is a slow phase detection circuit which receives the output QrQo from the counter (4), the tape running direction detection signal from the input terminal (2), and the second pulse from the input terminal (3), and outputs the signal from the counter (4). It is determined whether the phase of the latched contents latched with respect to the second pulse of the output QIQo is delayed, and when it is determined that the phase is delayed, the first
The adder circuit (11) is controlled to add another pulse to the pulse.

(5) is a logic circuit, and the output Q from the counter (4)
The logic circuit receives the tape running direction detection signal from the LQO and input terminal (2), generates one pulse and tape running direction control signal for each cycle of the counter counter ((1), and supplies them to the counter display. A[ receives the tape running direction detection signal and generates a tape running direction control signal by correcting it based on the change in the count of the counter (4), that is, the detection output of whether it is increasing or decreasing. This is useful when the running direction of the tape TP changes midway through.This indicator (6) shows the amount of tape running in hours, minutes, and
Displayed in seconds and frames (1/30 second).

Next, referring also to FIG. 2, the operation of the apparatus shown in FIG. 1 will be explained. In Figure 2, for convenience of explanation, time T1~
Set T13. The second pulse is shown in FIG. 2A and is common to FIGS. T7 and T l
'l' is assumed to occur approximately in the middle.

First, a case where the tape TP is running in the forward direction will be described. In this case, the phase of the count content of the counter (4) with respect to the second pulse is determined by the detection circuit (12),
In (13), when the count content of the counter (4) latched by the second pulse is 1, the phase lead detection circuit (12) determines that the phase is leading, and when it is 2° or 3, it is determined that the phase is lagging. If so, it is determined by the slow phase detection circuit (13). Therefore,
When the count content of the counter (4) latched by the second pulse is 0, it means that the count of the counter (4) is in phase with the second pulse.

The operation when the tape TP runs in the forward direction and the counting phase of the counter (4) with respect to the second pulse is lagging will be described. The count contents of the counter (4) in this case are shown in FIG. 2B. Time T1. T2, T'], the count content of the counter (4) changes to 0, 1.2, and at time T
Since the second pulse is generated at time T3, the count content 2 is determined to be a slow phase by the slow phase detection circuit (13), and from now on, a pulse is generated at time T4, and it is counted together with the first pulse. Since the signal is supplied to the counter (4), the count content of the counter (4) changes from 3 to 0 at time T4.

Then, time T5, TG, T? At this point, the number of stitches in the counter (4) changes to 1.2.3, and the second pulse is generated at time T7, so the count value 3 is changed to 1.2.3 in the slow phase detection circuit (13). It is determined that the phase is slow, a pulse is generated at time Ts, and is supplied to the counter (4) together with the first pulse, so that the count content of the counter (4) at time Ti is 0. Changes to 1.

Then, at time Ts + Tto + Tx't,
The count content of counter (4) is 2. 3. O, and a second pulse occurs at time T1'1,
Since the count content O at this time is in phase with the second pulse, it is neither inhibited nor added to the first pulse supplied to the counter (4).

In the logic circuit (5), as shown in FIG. 2C, the count content of the counter (4) changes from 3 to O at time T1. A tape running amount detection signal is generated at T4, Ts, and Tls, and this is supplied to the counting display (5) together with a positive tape running direction detection signal.

The operation when the tape TP runs in the forward direction and the phase of the number of stitches of the counter (4) with respect to the second pulse is advanced will be described. The number of stitches in the counter (4) in this case is shown in the second diagram. At times TI, T2, and T3, the count content of the counter (4) changes to 3.0.1, and at time T3, the second pulse is generated, so the count content 1 changes to 3.0.1. 12), it is determined that the phase is advanced, and the first pulse is prohibited at time T4, so the time T
4, the count content of the counter (4) remains 1 and does not change.

Thereafter, at times Ts, Ts, and TT, the count content of the counter (4) changes to 2.3.0, and a second pulse is generated at time T7, but the count content at this time is 0.
is in phase with the second pulse, so it is neither inhibited nor added to the first pulse supplied to the counter (4).

As shown in FIG. 2, the logic circuit (5) outputs the tape running amount detection signal at times Tz, TT, and T1'1 when the count of the counter (4) changes to 3-0. This is supplied to the stitch number indicator (5) together with a positive tape running direction detection signal.

Next, a case where the tape TP is running in the opposite direction will be explained. In this case, the phase of the stitch count content of the counter (4) with respect to the second pulse is determined by the detection circuit (12),
In (13), when the count content of the counter (4) latched by the second pulse is 2.3, it is judged by the phase lead detection circuit (12) that the phase is leading, and when it is 1, it is judged that the phase is lagging. If so, it is determined by the slow phase detection circuit (13). Therefore,
When the count content of the counter (4) latched by the second pulse is 0, it means that the count of the counter (4) is in phase with the second pulse.

The operation when the tape TP runs in the opposite direction and the phase of the number of stitches of the counter (4) with respect to the second pulse is advanced will be described. The count contents of the counter (4) in this case are shown in FIG. 2F. Time TL, T2. At time T3, the count content of the counter (4) changes to 0.3.2, and since the second pulse is generated at time T3, the count content 2 is detected by the phase advance detection circuit (12). Since it is determined that the phase is advancing and the first pulse is prohibited at time T4, the count content of the counter (4) remains 2 and does not change at time T4.

Thereafter, at time T5, Tr,, TT, the number of stitches in the counter (4) changes to 1.0.3, and at time T7, a second pulse is generated, so the count 3 advances. Since the phase detection circuit (12) determines that the phase is advanced and the first pulse is prohibited at time T8, the count content of the counter (4) remains at 3 and does not change at time T8.

Then, at time T9. Too, T1>, the count content of the counter (4) is 2.1. 0, and a second pulse is generated at time T11, but since the count content 0 at this time is in phase with the second pulse, there is no prohibition for the first pulse supplied to the counter (4). It is not added either.

Therefore, in the logic circuit (5), as shown in FIG. At l T 12, a tape running amount detection signal is generated, which is supplied to the counter display (5) together with an opposite tape running direction detection signal.

The operation when the tape TP runs in the opposite direction and the counting phase of the counter (4) with respect to the second pulse is delayed will be described. The count contents of the counter (4) in this case are shown in FIG. 2H. Time T1. At T2 and T3, the count content of the counter (4) changes to 3, 2.1, and at time T3
Since the second pulse is generated at T4, the count content 1 is determined to be a slow phase by the slow phase detection circuit (13), and from now on, a pulse is generated at time T4 and is counted by the counter together with the first pulse. (4), the count content of the counter (4) changes to 0.3 at time T4.

Thereafter, at times Ts, Ts, and TT, the count content of the counter (4) changes to 2.1.0, and a second pulse is generated at time T7, but the count content at this time is O
is in phase with the second pulse, so it is neither inhibited nor added to the first pulse supplied to the counter (4).

As shown in FIG. 2I, the logic circuit (5) generates a tape running amount detection signal at times T4, Ts, and 'TL2 when the count content of the counter (4) changes from 0 to 3. , which is supplied to the count display (5) together with the reverse tape running direction detection signal.

Next, another embodiment of the present invention will be described with reference to FIG. 5. In FIG. 5, parts corresponding to those in FIG. do. α is an inhibition circuit consisting of a Nant gate, and (11) is an addition circuit consisting of an OR gate.

The phase advance detection circuit (12) includes a logic circuit (5), and D-type flip-flop circuits (15) and (16) in the front and rear stages.
It consists of cascaded circuits. From the logic circuit (5), if the tape running direction is positive, the count content of the counter (4) is 1.
When the tape running direction is reversed, the counter (4)
When the count content of is 2 or 3, a high level output is obtained respectively, and this is the D of the previous stage flip-flop circuit (15).
Supplied to the input terminal. Also, the second input terminal from the input terminal (3)
The pulse is supplied to the T input terminal of the previous stage flip-flop circuit (15).

The non-inverted output of the flip-flop circuit (15) at the front stage is supplied to the D input terminal of the flip-flop circuit (16) at the rear stage. The first pulse (see Figure 6A) is applied to the inverter (20
) to the T input terminal of the subsequent flip-flop circuit (16). The subsequent flip-flop circuit (1
The inverted output of 6) is the previous stage flip-flop circuit (15)
is supplied to the inverting reset terminal of In this way, a high level inhibition pulse (C in FIG. 6) is output from the Q output terminal of the flip-flop circuit (16) in the subsequent stage, and the NAND circuit αω is output.
As shown in Figure 6E, the first
The supply of the pulses to the counter (4) is blocked by the NAND circuit αω.

The delay detection circuit (12) includes a logic circuit (5), and D-type flip-flop circuits (17) and (18) in the preceding and subsequent stages.
It consists of cascaded circuits. From the logic circuit (5), if the tape running direction is positive, the count content of the counter (4) is 2.
．． 3, if the tape running direction is reversed, the counter (
When the count content of 4) is 1, a high level output is obtained, and this is the D of the previous stage flip-flop circuit (17).
Supplied to the input terminal. Also, the second input terminal from the input terminal (3)
The pulse is supplied to the T input terminal of the flip-flop circuit (17) at the previous stage.

The non-inverted output of the flip-flop circuit (17) at the front stage is supplied to the D input terminal of the flip-flop circuit (18) at the rear stage. The first pulse (see Figure 6A) is applied to the inverter (
20) to the T input terminal of the subsequent flip-flop circuit (18). The inverted output of the flip-flop circuit (18) in the subsequent stage is the inverted output of the flip-flop circuit (18) in the previous stage.
7) is supplied to the inverting reset terminal. Thus, a low level passing pulse (FIG. 6D) is output from the Q output terminal of the flip-flop circuit (18) at the subsequent stage. On the other hand, a Nandt gate (21) is provided, which causes the first pulse to be slightly delayed by the delay circuit (19), and between this delayed first pulse (see FIG. 6B) and the subsequent flip-flop circuit ( Passing pulse from the inverted output terminal of 18) (
(see Fig. 6) is supplied to the NAND circuit (21).

Then, the output of this NAND circuit (21) is the OR circuit (1
1), the delayed first pulse is then supplied to the counter (4) together with the first pulse, as shown in FIG. Note that the other explanations of the operation of the apparatus shown in FIG. 5 are the same as those of the apparatus shown in FIG. 1, and therefore redundant explanations will be omitted.

Next, still another embodiment of the present invention will be described with reference to FIG. 7. In FIG. 7, parts corresponding to those in FIG. . In this embodiment, the adder circuit is omitted and its function is taken over by the logic circuit (5).

An AND circuit (26) is provided, and the second
pulse (positive pulse) and from the logic circuit (5),
A pulse that becomes high level when the count content of the counter (4) is advanced is supplied to the AND circuit (26), and the high level pulse as an output thereof is supplied to the inhibition circuit α as an inhibition signal.

On the other hand, a latch circuit (25) is provided, and a pulse from the logic circuit (5) that becomes high level when the count of the counter (4) is in a slow phase is supplied to the latch circuit (25), and the input terminal (
3), and its latch output is supplied to the logic circuit (5), where it outputs the output C1tQ of the counter (4).

1 is added to . Note that the other explanations of the operations of this device are the same as those of the device shown in FIG. 1, so a redundant explanation will be omitted.

〔Effect of the invention〕

According to the present invention described above, it is possible to obtain a tape running amount detecting device that can detect the tape running amount with high precision and can always obtain tape running direction information based on data transitions with minute resolution.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining the same, FIG. 3 is a layout diagram showing some means of an embodiment of the present invention, and FIG. 4 5 is a block diagram showing another embodiment of the present invention, FIG. 6 is a time chart providing explanation thereof, and FIG. 7 shows still another embodiment of the present invention. Block diagram, Fig. 8 is a block diagram showing a conventional device, Fig. 9
The figure is a time chart for explanation. (4) is a counter, (5) is a logic circuit, (6) is a count display, (8) is a control circuit, (to) is a prohibition circuit, (1
1) is an adder circuit, (12) is a leading phase detection circuit, and (13) is a lagging phase detection circuit. Figure 1 Figure 2 lT11T21T31T41T51T61T71T81
τ91TIOIT111T121T131 Figure 1 Figure 9 Procedural amendment document January 1985, Labor Day 8, 1, Display of case Hini 1989 Patent application J8250244 No. 3, Relationship with the person making the amendment Patent applicant address Tokyo Parts District Kitashinyo 6-7-35 Name (2
18) Sony Corporation Representative Director Norio Ohga 4, Agent 6, Number of inventions increased by amendment (1) Added ``in the positive direction'' after ``value'' on the last line of page 5 in ``Mei My'' do. (2) Same, page 6, line 1, “in the opposite direction” before “O”
join. (3) Same, page 5 line ``6-2 or 2-6'' is replaced with ``6-2 or 2-6''.
6-1 or 1-6”. (4) Between, page 12, line 11 “Logic circuit (10)
Correct "J" to "logic circuit (5)". (5) Same page, line 13, "Is it in the increasing direction or decreasing direction?" is corrected to "Is it in the positive increasing direction or the opposite decreasing direction?" (6) Same, page 19, lines 13 to 15, ``Circuit (5), consisting of the preceding stage and subsequent stage...'' was replaced with ``Circuit (5), consisting of the preceding stage D-type flip-flop circuit (15).'' ” he corrected. (7) Same, page 20, lines 4-5, ``The following...is supplied.'' is corrected as follows. ``The subsequent flip-flop circuit that constitutes a prohibited circuit (
16) and inhibits one first pulse in cooperation with the NOR circuit (10). ” (8) Same page, lines 12 and 14 “Nand circuit (10
) "J" should be corrected as "Noah circuit (10) J." (9) Same page, lines 16 to 18, "Circuit (5), consisting of a preceding stage and..." should be replaced with "Circuit ( 5) and a D-type flip-flop circuit (17) in the previous stage. Corrected to J. (10) Same, page 21, line 7, before "later stage", add "constitutes an adder circuit." (11) Same page, line 8, “supplied” should be corrected as follows. "One extra pulse is supplied to the counter (4) and added in cooperation with the delay circuit (10), NOR circuit (21), and OR circuit (11)." (12) Same page. Lines 15-16 “Nantes Gate (21) J”
Correct it as NOR circuit (21) J. (13) Same, page 21, last line to page 22, line 1, 22nd
Page 1 to 2 lines ``Nand circuit (21) J''
NOR circuit (21) Correct as J. (14) Same, page 22, line 12 “Logic circuit (5)
” is replaced with “Logic circuit (5), latch circuit (25)
and data adder (30) J. (15) Same page, line 15 and last line “Counter (4)
'' is corrected as [data adder (30) J]. (16) Same as above, from the last line of page 22 to the first line of page 23, the phrase ``the pulse that becomes high level'' is corrected to ``the data to which 1 is added by the data adder (30)''. (17) Same, page 23, line 3 “Logic circuit (5)”
(18) In line 4 of the same page, the statement "output Qi, Qo J of the counter (4) is corrected to read "data adder (30) J. Correct the data to be (19) In the drawings, Figures 7 and 9 will be corrected as shown in the attached sheet. Above correction diagram Figure 9■

Claims (1)

[Claims] a first pulse generating means that mechanically detects the running of the tape and generates a first pulse; and a second pulse generating means that reproduces a position signal recorded on the tape and generates a second pulse. and a counter that counts the first pulse,
a control circuit that detects the phase of the count of the counter with respect to the second pulse and controls input of the first pulse to the counter depending on whether the phase is leading or lagging; What is claimed is: 1. A tape running amount detecting device comprising: a tape running amount detecting device, wherein a tape running amount detection signal is obtained based on the output of the counter.