JPH0664863B2 - Time code data output circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time code data output circuit for reading and outputting time code data used, for example, for editing a video tape, and more particularly to a time code data output circuit. Even when a reading error of the recorded time code signal occurs, valid time code data can be output.

[Background technology and its problems]

When editing an image recorded by a video tape recorder, it has been conventionally known that a time code signal serving as an address signal is recorded on a tape in advance and the editing is performed while reading the time code signal. As this time code, a longitudinal time code (so-called) recorded along the tape running direction of the video tape is used.
LTC) and a vertical section time code (so-called VITC) recorded in a vertical synchronization section on a video track, and each includes a kind of address information indicating hours, minutes, seconds and frames.

As a modulation method of the LTC signal, a so-called bi-phase mark method is adopted in which it is always inverted at the boundary of each bit of data and is inverted even at the intermediate position of the bit only when it is "1". The inversion interval is the bit period T
, Then either 0.5T or 1T. Therefore, it can be said that the modulation method generally includes a clock signal component in the signal and is resistant to jitter. However, when editing a video tape, the change range of the tape running speed is extremely wide such as fast-forward, rewind, slow-motion playback, quick-motion playback, etc., and especially when switching the tape speed or when the tape speed is low. The LTC reading may not be performed normally.

By the way, when switching the tape running speed to low speed, it is possible to obtain the time code interpolation data by adding the number of frames calculated according to the control pulse so that it continues to the LTC data immediately before this switching. However, with this method, the LTC
There is a drawback that normal LTC data cannot be obtained when the data is incorrect or an error occurs during high speed driving. The control pulse is a pulse obtained by reproducing the control track recorded and formed along the running direction of the video tape.

As described above, when normal time code data cannot be obtained, automation of videotape editing is hindered, and editing accuracy is reduced and editing errors frequently occur, which is not preferable.

[Object of the Invention]

In view of the above-mentioned point, the present invention can effectively perform data interpolation when a reading error of time code data occurs at any tape running speed, and can obtain time code data without a dropout portion, and edit accuracy. It is an object of the present invention to provide a time code data output circuit that contributes to the improvement of performance and reduction of editing mistakes, and also contributes greatly to the complete automation of editing.

[Summary of the Invention] That is, the feature of the time code data output circuit according to the present invention is that the time to read the time code data from the time code reproduction signal obtained by reproducing the time code signal recorded on the magnetic tape such as a video tape. Code reading means, error detecting means for detecting a reading error of the time code reading means, gate means supplied with output data from the time code reading means and controlled by output from the error detecting means, and gate The storage means for storing the output data from the means and outputting the stored contents as time code data, the pulse generating means for outputting a pulse corresponding to the running amount of the recording medium, and the storage contents of the storing means are It is changed using the pulse from the pulse generating means according to the detection output of the error detecting means. When there is no reading error in the time code reading means, the gate means is put into a signal passing state by the output from the error detecting means, and the output data from the time code reading means is provided. If the reading error occurs in the time code reading means, the contents are supplied to and stored in the storage means, and the stored contents are output. When the reading error occurs in the time code reading means, the gate means is shut off by the output from the error detecting means. In addition to the state, the stored contents of the storage means changed by the time code interpolating means are output as time code data. Therefore, continuous time code data without omission can be obtained even when a reading error occurs, which can greatly contribute to the improvement of the efficiency of editing work.

〔Example〕

Preferred embodiments of the time code data output circuit according to the present invention will be described below with reference to the drawings.

In FIG. 1, an input terminal 1 is supplied with, for example, a time code reproduction signal obtained by reproducing a longitudinal time code signal (so-called LTC signal) recorded along the running direction of a video tape. The time code reproduction signal is sent to the time code reading circuit 2 to read the time code data. Error detection circuit 3
Detects a reading error in the time code reading circuit 2 and controls the gate circuit 4 to be turned on and off according to the error detection signal. The gate circuit 4 is provided between the time code reading circuit 2 and the storage circuit (so-called memory) 5, and in normal times (when there is no reading error described above), the time code reading data from the time code reading circuit 2 is read. Is sent to the storage circuit 5 to be stored therein, and when the reading error occurs, the output data from the time code reading circuit 2 is prevented from being sent to the storage circuit 5. Memory circuit 5
The storage content of is output from the output terminal 6 as time code data.

Next, the time code interpolation circuit 10 outputs the time code data for interpolation according to the stored contents of the storage circuit 5 and other information. In the present embodiment, the video is used as the other information. The running amount of the tape is used. This tape running amount can be obtained by detecting the rotation of the tape running drive capstan, pinch roller, reel drive shaft, or the like, as in the case of a so-called tape counter or tape timer. A rotation detection pulse generator that outputs eight pulses for tape running is used, and the rotation detection pulse from this pulse generator is supplied to an octal counter (or 1/8 frequency divider). The tape counter pulse of the frame cycle is obtained, and this tape counter pulse is passed through the input terminal 11 of the time code interpolation circuit 10 to the counter circuit.
Sending to 12. The counter circuit 12 is capable of up / down counting, and the up / down switching control terminal is supplied with an FWD / REV switching signal from the input terminal 13, that is, depending on whether the tape running direction is forward or backward. A switching signal is supplied. Further, the counter circuit 12 can be preset, and the contents stored in the memory circuit 5 are supplied to the preset terminal via the correction circuit 14. The correction circuit 14 is supplied with the FWD / REV switching signal from the input terminal 13, and at the time of FWD (when traveling in the forward direction), the value obtained by subtracting 1 (frame) from the stored content of the storage circuit 5 is used by the counter circuit. It is sent to the 12 preset input terminals, and the stored content of the storage circuit 5 is sent to the preset input terminal of the counter circuit 12 as it is (without changing) during REV (during backward traveling). The correction circuit 14 is supplied with an error detection signal from the error detection circuit 3, so that the counter circuit 12 is preset only when there is no error, and the preset operation is not performed when an error occurs. The count output from the counter circuit 12 is sent to the memory circuit 5 via the write circuit 15. When the above error occurs, the output from the writing circuit 15 becomes time code interpolation data, which is stored (written) in the storage circuit 5 and is output as time code data via the output terminal 6. When there is no error, the output from the writing circuit 15 may or may not be stored in the storage circuit 5.

In the time code data output circuit having the above configuration, the data interpolation operation when an error occurs when the video tape runs in the forward direction as in the so-called FWD mode will be described with reference to FIG.

First, FIG. 2A shows a substantial frame address corresponding to a video signal recorded on a video tape. The fifth frame is before time t _{2 and} the sixth frame is between time t _{2 and} t _6. , ... FIG. 2B shows frame address data stored in the storage circuit 5 and taken out from the output terminal 6 as time code data. FIG. 2C shows a reading operation of the time code data in the time code reading circuit 2, and shows a state in which the reading operation is being executed during a low level period (for example, between time t _{2 and} t ₅ ) in the drawing, and is high. When the level is reached, the reading is completed and the read data is output. This X in FIG. 2C
The mark indicates that an error occurred during the reading operation, resulting in error data. Next, FIG. 2D shows a data output timing pulse from the reading circuit 2, and the data output at this time is one obtained by adding 1 to the read time code data. FIG. 2E shows data output from the counter circuit 12 of the time code interpolating circuit 10 through the writing circuit 15, and FIG. 2F shows input data.
The tape counter pulse signal to 11 and the control pulse in FIG. 2G are shown.

The control pulse shown in FIG. 2G is obtained by supplying the rotation detection pulse (8 pulses per frame) for detecting the tape running amount to the octal counter and the 1/8 frequency divider. It is used as a reference when obtaining a tape counter pulse as shown in FIG. 2F at a rate of one per frame. That is, the control pulse output timing (for example, time t ₄ ) in FIG. 2G maintains a constant phase (for example, 1/2 field) with respect to the frame switching timing (for example, time t ₂ ). the octal counter or the like is preset to a predetermined value by a pulse, a timing closest (e.g. time immediately after the tape counter pulse frame switching Taimungu in FIG. 2 F, which is the output from the octal counter, etc. (for example, time t ₆₎ It is output at t ₇ ). In this case, the maximum value between times t _{6 and} t ₇ is 1/8 frame.

Before such time t _{1 in} FIG. 2, the time code reading circuit 2 normally reads the time code, and at this time t ₁ , the frame data “5” of the time code data is obtained. Next, at the frame switching timing at time t ₂ , frame data “6” obtained by adding 1 to the data “5” is output from the time code reading circuit 2 and sent to the storage circuit 5 via the gate circuit 4. As a result, the stored contents of the storage circuit 5 and the frame data of the time code data from the output terminal 6 become "6" as shown in FIG. 2B. Further, the frame data "6" of this stored content is subtracted by 1 by the correction circuit 14 to become "5", and this data "5" is sent to the counter circuit 12 and preset. Next, at time t ₃ , the tape counter pulse shown in FIG. 2F is supplied to the counter circuit 12, so that the output of the counter circuit 12 changes from “5” to “6” as shown in FIG. 5E. The output data “6” is incremented and sent to the memory circuit 5 via the write circuit 15. The output data from the writing circuit 15 at this time is
It may or may not be written in the memory circuit 5 (see the dashed arrow at time t ₃ in FIG. 2).

Next, when the reading error at time t ₂ ~t ₅ of Figure 2 occurs, since the error detection signal from the error detection circuit 3 to the gate circuit 4 as a signal blocking condition, the frame switching timing time t the second diagram D of error data of the data output time code even timing pulse is given read circuit 2 of ₆ is sent to the memory circuit 5 without
The stored contents remain "6" as shown in FIG. 2B.
Here, the error detection signal is also sent to the correction circuit 14, and when an error occurs, the preset operation of the counter circuit 12 by the correction circuit 14 is prohibited, or the subtraction of -1 is not performed, The stored contents of the storage circuit 5 are preset as they are in the counter circuit (see time t _{6 in} FIG. 2).
). Next, at time t ₇ , the counter pulse of FIG. 2F is supplied to the counter circuit 12, whereby the count output advances from “6” to “7”, and this data “7” is written in the write circuit 15 By being sent to and stored in the storage circuit 5 via, the stored contents and the time code data output change from "6" to "7" as shown in FIG. 2B.

Here, the time t ₇ is slightly deviated from the frame switching timing (time t ₆ ) of the video signal recorded on the tape, but it is within 1/8 frame, and during actual video editing, One frame section (for example, time t ₆
At the timing near the substantially center because performs uptake such time code data of the ~t between _8), does not affect at all the editing process.

Next, regarding the operation when an error occurs in the so-called REV mode when the tape running direction is the reverse direction,
Description will be given with reference to the drawings.

3A to 3G correspond to FIGS. 2A to 2G described above, respectively, and FIG. 3A shows the frame address corresponding to the video signal recorded on the video tape. B shows the stored contents of the storage circuit 5 and the time code data from the output terminal 6, FIG. 3C shows the reading operation in the time code reading circuit 2, and FIG. 3D shows the data output timing pulse from the time code reading circuit 2. The third
FIG. E shows data output through the counter circuit 12 and the write circuit 15, FIG. 3F shows a tape counter pulse signal to the input terminal 11, and FIG. 3G shows a control pulse.

First, at time t _{1 2} the frame switching timing of the frame address of the video signal shown in Figure 3 A is switched from "10" to "9", the data read in the time code reading circuit 2 as shown in Fig. 3 C operation is completed, if the frame address data "10" is obtained successfully (no error) at time t _{1 3} of the next data output timing, obtained by subtracting the frame address data "10" by one data "9" is sent to the memory circuit 5 via the gate circuit 4 (see arrows in Figure 3 the time t _{1 2),} the memory circuit 5
The stored contents and the time code data from the output terminal 6 change from "10" to "9" as shown in FIG. 3B. Further, the stored content of the storage circuit 5 is sent to the preset input terminal of the counter circuit 12 via the correction circuit 14 of the time code interpolation circuit 10, but when the vehicle is running in the reverse direction (RE
When V), the correction circuit 14 outputs the input data as it is,
In this case, the frame address data “9” is the counter circuit.
It is sent to 12 and preset.

On the other hand, for example, when a data reading error occurs after time t _{13 in} FIG. ₃ , the gate circuit 4 is turned off and the output data from the time code reading circuit 2 is stored in the storage circuit 5. In addition to being prevented from being sent, the output from the counter circuit 12 of the time code interpolation circuit 10 is sent to the storage circuit 5 via the writing circuit 15 and is output from the output terminal 6 as time code data.

Here, the tape counter pulse when the tape running direction is the reverse direction is obtained within ⅛ frame period of the frame switching timing straight line as shown in FIG. 3F. This is because the output timing of the control pulse (FIG. 3G) appears 1/2 field (1/4 frame) before the frame switching timing, symmetrically with the case of FIG. 2 described above. In accordance with the above, the tape counter pulse as shown in FIG. 3F is obtained by presetting the octal counter or the like for dividing the rotation detection pulse described above to a predetermined value.

Now, at time t _{1 3} after the time t _{1 5} tape counter pulse is input to the read error has occurred, as the counter circuit 12 is shown in FIG. 3 E from "9" to "8" so-called counts down (see arrows in Figure 3 the time t _{1 5)} the count output data "8" is sent to the memory circuit 5 via the write circuit 15, from the stored contents and the output terminal 6 of the memory circuit 5 The frame address of the time code data is “9” as shown in FIG. 3B.
Changes from "8". In the read data output timing of time t _{1 7,} there gate circuit 4 is the cut-off state, it is needless to say that the output data from the time code reading circuit 2 is not sent to the memory circuit 5.

It is not necessary to store the output data from the writing circuit 15 of the time code interpolation circuit 10 in the storage circuit 5 at the tape counter pulse input timing (for example, time t _{1 1} ) when there is no error, but FIG. At time t _{1 1}
May send the memory circuit 5 as shown in broken line arrows be stored the data "9" is the next frame address, even though if the data is erroneous, the next read data output timing (time t _{1 3} ) Stores correct data.

As is clear from the above description, when the data reading error occurs in the time code reading circuit 2 regardless of whether the tape running direction is the forward direction or the backward direction, the time code interpolation circuit 10 Is output from the output terminal 6 as time code data.
The interpolation circuit 10 outputs the time code interpolation data based on the correct time code data read immediately before the occurrence of the error and the frame number data (tape count data) according to the tape running amount. Even at times, the continuity of the time code data from the output terminal 6 is maintained.

The present invention is not limited to the above-described embodiment, and for example, as the time code interpolation circuit, other than the one that uses the tape running amount data such as the tape timer or the tape counter that detects the actual running amount of the tape. In addition, for example, one using tape running amount data obtained by counting control pulses may be used. However, since the control pulse is obtained by reproducing the control track by the control head, compensation when the tape speed becomes extremely low is insufficient, whereas the tape running amount as in the above embodiment is insufficient. In the case of directly detecting, the octal count (or frequency division) described above is continuously performed even if the control pulse cannot be obtained, and the tape counter pulse of substantially the frame period is continuously obtained. It is possible to output the time code data with sufficient reliability even in the transition period until the control pulse is obtained again and the reference timing is accurately determined.

In addition, a multiplexer may be used instead of the gate circuit 4, and the read data when no error occurs and the interpolated data when the error occurs may be selectively switched to be sent to the storage circuit. The memory circuit 5 may be configured as a buffer register or a latch circuit for outputting time code data, and the time code reading circuit unit includes the error detection circuit 3, the gate circuit 4, and the memory circuit 5. It is also possible to Further, it goes without saying that the circuit configuration of FIG. 1 may be implemented not only by hardware but also by software using a so-called microprocessor and memory.

〔The invention's effect〕

According to the time code output circuit of the present invention, when a read error occurs in the time code data, the output data from the time code interpolating means is output as the time code data. Since the interpolation data is output based on the time code data taken and the running amount of the recording medium, the continuity of the time code output data before and after the error occurs is kept good, and an error occurs during data reading. Even in such a case, since it is irrelevant to the detection of the running amount of the recording medium, the running amount can be detected with the same accuracy as in the case of no error, and the reliability of the interpolation data is high. Therefore, not only the editing accuracy and the editing mistakes can be reduced in the video editing work, but also the full automation of the editing can be greatly contributed.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a time code data output circuit according to the present invention, and FIGS. 2 and 3 are time charts for explaining the operation of the above embodiment. 2 ... Time code reading circuit 3 ... Error detection circuit 4 ... Gate circuit 5 ... Memory circuit 10 ... Time code interpolation circuit 12 ... Counter circuit

Claims (1)

[Claims] 1. A time code reading means for reading time code data from a time code reproduction signal obtained by reproducing a time code signal recorded on a recording medium, and an error detecting means for detecting a reading error of the time code reading means. And gate means which is supplied with output data from the time code reading means and is controlled by output from the error detecting means, and output data from the gate means is stored and the stored contents are output as time code data. The storage means, the pulse generation means for outputting a pulse corresponding to the running amount of the recording medium, and the storage contents of the storage means are stored in the storage means by using the pulse from the pulse generation means according to the detection output of the error detection means. And a time code interpolating means for changing the time code, If have, as the signal passes through a state of the gate means by the output from said error detecting means, the output data from the time code reading means is stored is supplied to the storage means,
The stored contents are output as time code data, and when a reading error occurs in the time code reading means, the gate means is brought into a signal cutoff state by the output from the error detecting means, and the time code interpolating means is also provided. A time code data output circuit for outputting the stored contents of the storage means changed by the above as time code data.