JPS61123244A - Data communication processor - Google Patents

Abstract

PURPOSE:To attain normally burst transfer independently of the buffer memory capacity by applying stop/continuity/restart of burst transfer in response to the relation of quantity between the data stored in a buffer memory and the capacity of the buffer memory. CONSTITUTION:A reception data D is written in a buffer memory 5 according to the write address. The read from the memory 5 is executed by the read address. A signal A adding a prescribed number (a number decided by the capacity of the memory 5) to the read address and a signal corresponding to the write address are inputted to a comparator 14, and when A<B, a signal C1 is generated, a wait controlsignal Wa is outputted to stop data transfer at the transmission side. When A>=B, a signal C2 is generated, a wait control signal Wb is outputted to continue or restart normal data transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data communication processing device used in a multi-data communication system.

[Conventional technology]

Conventionally, when performing burst transfer between data communication processing devices in this type of multi-data communication system, a data buffer memory is provided in the data communication processing device, data is temporarily stored in this data buffer memory, and then data communication processing is performed. Data store operations were performed between the device and the memory device.

[Problem that the invention seeks to solve]

The conventional data communication processing device described above has a drawback that when data is transferred in excess of the capacity of the data buffer memory, data overflow occurs when the data buffer memory in the receiving data communication processing device becomes full.

An object of the present invention is to provide a data communication processing device that can normally perform burst transfer regardless of the capacity of a data buffer memory.

[Means for solving problems]

The uninvented invention is to temporarily stop or continue burst transfer depending on the size relationship between the amount of data stored in the data buffer memory and the capacity of the data buffer memory in order to achieve the purpose described in L. Each data communication processing device is provided with a function that allows it to restart the communication. Further, as a signal line for controlling burst transfer in this manner, a wait line is provided in parallel with the system bus connecting each data communication processing device.

That is, in the data communication processing device according to the present invention, each data communication processing device has a data buffer memory and performs burst transfer of data to each other via a system bus. When the amount of data stored in the buffer memory reaches the capacity of this data buffer memory, via the above-mentioned wait line,
Outputs a first control signal that controls the data communication processing device that has sent the data to temporarily stop burst transfer; and when the amount of data stored in the data buffer memory is less than its capacity or a wait function control unit that outputs a second control signal to control the data communication processing device that transmitted the data to continue burst transfer or restart burst transfer via the above-mentioned wait line when It is characterized by having the following.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a data communication processing device according to the present invention together with a multi-data communication system. The data communication processing device l has a system bus 2 and a wait line 3.
A row line interface unit 4, a data buffer memory 5 through which data is input/output through the interface unit 4, and a data buffer are connected to each other by a line interface unit 4, which is connected to the system bus 2 and the data line 3, respectively. It includes a wait function control section 6 that controls the memory 5, and an interface section 7ζ that connects the data buffer memory 5 and an external CPOS. This CPUA is further connected to a memory device 9.

FIG. 2 is a concrete block diagram of the data communication processing device. Hereinafter, a case where it is applied for reception will be explained.

The wait function control section 6 is equipped with an address control section 10, and a write address register 11 and a read address register 12 are connected to this address control section 1G. These registers 11 and 12 are controlled by the address 11111 unit 10 to specify which address in the data buffer memory 5 data is to be written, or from which address of the written data data is to be read. It is for the purpose of On the output side of the read address register 12, there is a register 12.
An adder 13 is connected which adds a predetermined number of bits (a number determined according to the capacity of the data buffer memory 5) to the contents of the signal A and sends the result as a signal A to one input terminal of the comparator 14. Furthermore, the signal B from the write address register 11 is directly input to the other input terminal of the comparator 14.

The comparator 14 has two output terminals, one output terminal is connected to the set terminal S of the flip-flop 15, and the other output terminal is connected to the reset gate R of the flip-flop 15. The comparator 14 compares the two input signals A and B, and if A<B, the discrimination signal C! to one output terminal, that is, the set terminal S of the flip-flop 15
If A≧B, another discrimination signal C2 is sent to the other output terminal, that is, the reset terminal R of the flip-flop 15.

The output terminal Q of the flip-flop 15 is connected to the wait line 3 via the interface section 4, and when the discrimination signal C8 is input to the output terminal S, a high-level wait control signal -d is output. , controls the transmitting side data communication processing device to stop data transfer via the wait line 3.

Conversely, when the determination signal C2 is input to the reset terminal H, a low-level wait control signal wb is output, and the transmitting side data communication processing device is controlled to restart data transfer.

Next, the operation of the data communication processing device configured as described above will be explained.

The data communication processing device on the receiving side receives data and control signals through the interface section 4. Received data D
is written to the data buffer memory 5. The write address is specified by the write address register 11 controlled by the address control unit 1O. -'yz, the memory contents specified by the read address register 12 controlled by the address control section 10 are read from the data buffer memory 5. The data read from the data buffer memory 5 is sent to the CPU via the interface section 7.
8.

At this time, the comparator 14 compares the value obtained by adding a predetermined number of bits to the contents of the read address register 12, that is, signal A, and the contents of the write address register 11, that is, signal B. Then, the comparator 14 outputs the discrimination signal C1
When the flip-flop 15 outputs a high-level wait control signal Wa, the data communication processing device on the transmitting side stops data transfer.

At this time, if the comparator 14 outputs the determination signal C2, this indicates that there is room in the data buffer memory 5, so that normal data transfer is continued.

After a while after the data transfer from the transmitting side data communication processing device is interrupted, the magnitude relationship between signals A and B is reversed. At this point, the comparator 14 outputs the discrimination signal C2, and in response thereto, the flip-flop 15 outputs a low-level wait control signal wb.

As a result, the sending data communication processing device resumes data transfer.

〔Effect of the invention〕

As described above, the present invention has the advantage that even if the processing time of the receiving side data communication processing device is temporarily extended, burst transfer can be performed normally without causing data overflow.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a data communication processing device according to the present invention together with a multi-data communication system, and FIG. 2 is a concrete block diagram of the data communication processing device. l...Data communication processing device. 2...System bus. 3... Weight line. 4.7...Interface section. 5...Data buffer memory. 6...Wait function control section. 8...CPIJ. 9...Memory device. lO: Address control unit. ll...Write address register. 12...Read address register. 13... Adder. 14... Comparator. 15...Flip-flop. A... Signal (a predetermined number of beats added to the contents of the register 12). B... (indicates the contents of register 11) @ number. C,...(When A<B) Discrimination signal. C2...Discrimination signal (when A≧B). D... Received data. Wa--Wait control signal (for stopping data transfer). ■...Wait control signal (for continuing or resuming data transfer).

Claims (1)

[Scope of Claims] A data communication processing device each having a data buffer memory and performing burst transfer of data to each other via a system bus, comprising: a wait line arranged in parallel with the system bus; A first control signal that controls the data communication processing device that transmitted the data to temporarily stop burst transfer via the wait line when the amount of stored data reaches the capacity of the data buffer memory. When the amount of data output and stored in the data buffer memory is less than or equal to the capacity, the data communication processing device that sent the data continues burst transfer via the wait line. 1. A data communication processing device, comprising: a wait function control unit that outputs a second control signal for controlling to restart or restart burst transfer.