JPS6049465A - Data transfer method between microcomputers - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity of an interface and at the same time to discriminate the transfer order of data through a simple process by transferring data successively via an input/output register FIFO. CONSTITUTION:An independent access is possible at the input and output sides with a register FIFO4, and the FIFO4 delivers an input ready signal IR showing the presence or absence of an idle area in a memory region as well as an output ready signal OR showing the presence or absence of writing of data to the memory region. When it is needed to read the memory information of the FIFO4 while a microcomputer 6 for reception is using the data given from a microcomputer 1 for transmission, the computer 6 discriminates whether the signal OR is set at 1. Then a reading action is carried out if the signal OR is set at 1. Thus the frequent interruption processing can be omitted by transferring data via the FIFO4. This can reduce the hardware quantity and also discriminate the transfer order of data with a simple process.

Description

[Detailed description of the invention] “Technical field of invention”.

The present invention relates to a data transfer method between microcomputers.

Prior Art and Problems In general, methods for transferring data between microcomputers include (1) DMA method; (2) the transmitting microcomputer puts the receiving microcomputer in a hold state and the data is stored in the memory of the receiving microcomputer; A method of transferring data via a bus is known.

However, both have the disadvantage of requiring a large amount of interface hardware. Furthermore, in order to know the data transfer order, it is necessary to control the data transfer order using a pointer or the like, which poses the problem of complicating the process.

Purpose of the Invention The present invention aims to improve these conventional drawbacks.
It is an object of the present invention to provide a data transfer method between microcomputers that can interface with a small amount of hardware and can determine the data transfer order without requiring complicated processing.

Embodiment of the Invention FIG. 1 is a block diagram of essential parts showing an example of an apparatus for carrying out the invention.

In the figure, reference numeral 1 is a transmitting microcomputer, whose 8-bit bidirectional bus 2 is connected to the data input terminal of a FIFO register 4 via a driver 3, and any 1-bit bus line is connected to the driver 5. The input ready signal IR output terminal of the FIFO register 4 is connected to the input ready signal IR output terminal of the FIFO register 4 via. Further, a write signal WR is connected to a write signal input terminal of the FIFO register 4. 6 is a receiving microcomputer, whose 8-bit bus 7 is connected to the data output terminal of the FIFO register 4 via the driver 8, and any 1-bit bus line is connected to the output terminal of the FIFO register 4 via the driver 9. Connected to the ready signal OR output terminal. In addition, the input ready signal IR of the FIFO register 4 is input to the interrupt input terminal via an edge-trigger type one-shot multi-by-break (hereinafter simply referred to as one-shot multi) 10, and the read signal RD is output to the read signal input terminal of the FIFO register 4. has been done.

The FIFO register 4 can be accessed independently on the input side and the output side, and also has an input ready signal JR indicating whether the storage area is full or not, and an input ready signal JR indicating whether data has been written to the storage area. This is a register that outputs an output ready signal OR, for example, 74LS2.
It can be configured with 24 ICs.

FIG. 2 is a block diagram showing an embodiment of the FIFO register 4. Two commercially available FIFO registers with 4-bit input/output and a capacity of 4 x 16 bits are used to configure the FIFO register 4 with a total of 8 x 16 bits. This is what I did. In the figure, D1 to D are the outputs of the driver 3, 0. ~OIl is the output of the FIFO register 20.degree. 21, and this output is input to the driver 8. Also, the write signal HR of the transmitting microcomputer 1 is the FIFO register 20.2.
The read signal RD of the receiving microcomputer 6 is input to the write signal input terminal of the FIFO register 2.
It is manually input to the read signal input terminal of 0°21. FIFO
Input ready signal 1' output from register 21
l? , , IR2 is set to “1” when there is free space in the storage area.
'', which becomes "0" when the storage area is full, and the AND circuit 22 takes the AND circuit to generate the input ready signal IR. Toready signal OR
,,OR2 is a signal that becomes "1" when at least one data is stored in the storage area, and becomes "θ" when no data is stored. A □ The output ready signal OR is generated.

FIG. 3 is a flowchart showing the flow of data writing processing by the sending microcomputer 1, and FIGS. 4 and 5 are flowcharts showing the flow of data reading processing by the receiving microcomputer 6. Further, FIG. 6 is a timing chart showing the states of each part when the first illustrated device is operated, and (a) is a timing chart showing the state of each part when the first illustrated device is operated.
write processing, (b) is the receiving microcomputer 6
(C') is the state of the input ready signal IR, (d) is the output waveform of the one-shot multi 10, (
e) shows the state of the output ready signal OR, respectively.

As shown in the flowchart of FIG. 3, the transmitting microcomputer 1 determines whether the input ready signal IR is "1" or not, and when it is "1", sends the data to the receiving microcomputer 6 to the bus 2.driver. F through 3
Send and write processing to the IFO register 4. When the input ready signal IR is 0'', FIFO register 4
Since the memory capacity of is full, data will not be written.

The receiving microcomputer 6 normally executes the processing shown in the flowchart of FIG. 4, and when the data from the transmitting microcomputer 1 is needed during processing or for other processing. Output ready signal OR is set to “1” at any time such as during free time.
If it is "1", the information stored in the FIFO register 4 is transferred to the driver 8. Read via bus 7. Also,
The receiving microcomputer 6 is busy with other processing L<FI
Since the reading process of the stored information in the FO register 4 is not performed for a certain period of time, when the stored information in the FIFO register 4 becomes full, the input ready signal IR changes from "1" to 0, and at the falling edge, the one-shot multi-channel signal is activated. 10 is activated and an interrupt is applied to the receiving microcomputer 6.The receiving microcomputer 6 is programmed to execute the process shown in FIG. 5 when the interrupt occurs, and the output ready signal OR is The information stored in the FIFO register 4 is read out up to '', that is, until all of the information stored in the FIFO register 4 is exhausted. Note that instead of reading out all the information, it is also possible to adopt a configuration in which a predetermined amount of data is read out.

The storage capacity of the FIFO register 4 is determined by taking into account variations in the writing speed of the transmitting microcomputer 1 and variations in the reading speed of data in the receiving (M) microcombiator 6, so that there are not too many interrupts to the receiving microcomputer 6. It is preferable not to apply it frequently.

Incidentally, depending on the interrupt acceptance format of the receiving microcomputer 6, the one-shot multiplexer 10 shown in FIG. 1 can be omitted. Furthermore, if another set of configuration similar to that shown in FIG. 1 is provided, data transfer from the receiving microcomputer 6 to the transmitting microcomputer 1 is also possible.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the hardware
It only requires the IFO register 4 and a few circuits, making the interface circuit extremely simple. Also, FIF
Since data is transferred via the O register 4, the data transfer order can be determined without complicated processing. It is also possible to read the information stored in the FIFO register 4 by sending an interrupt to the receiving microcomputer 6 using the output ready signal IR, and to perform the reading within the interrupt processing. In addition, there is a possibility that other processing of the reception microcomputer 6 will be adversely affected due to frequent interruptions. In contrast, in the present invention, the receiving microcomputer 6
Since the next data is read when necessary, such a problem does not occur, and the FIFO register 4 is only read by interrupt processing when the FIFO register 4 is full.
Since the data in the O register 4 is immediately read, it is possible to avoid a situation where the writing process of the transmitting microcomputer I is stopped for a long time.

The method of the present invention is very effective when applied to a multi-microcomputer system or the like where data transfer between an upper microcomputer and a lower microcomputer is concerned with the order of data transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts showing an example of a device implementing the present invention, FIG. 2 is a block diagram showing an embodiment of the FIFO register 4, and FIG. 3 shows the flow of data write processing of the sending microcomputer 1. 4 and 5 are flowcharts showing the flow of the data reading process of the receiving microcomputer 6, and FIG. 6 is a timing chart showing the states of each part when the first illustrated device is operated. l is the sending microcomputer, 2 is its bus, 4 is the FIFO register, 6 is the receiving microcomputer,
10 is a one-shot multi-IR that generates an interrupt signal.
is an input ready signal, and OR is an output ready signal. Patent Applicant Fanuc Co., Ltd. Patent Attorney Patent Attorney Gobe Tamamushi Gobu I Name 1 Figure 2 Figure M 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] In a data transfer method between microcomputers, the input side and the output side can be accessed independently, and an input ready signal indicating whether the storage area is full or not and whether data has been written to the storage area. A FIFO register is provided between the transmitting microcomputer and the receiving microcomputer, and the transmitting microcomputer determines from the input ready signal that there is free space in the storage area and outputs the data. is written to the storage area of the FIFO register, and the receiving microcomputer determines that data has been written to the storage area by the output ready signal at an arbitrary time and stores the data in the storage area. A data transfer method between microcomputers, characterized in that when data is read and the storage area becomes full due to the input ready signal, the data in the storage area is immediately read by interrupt processing.