JPS61109095A - Screen display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a screen display device, and particularly to a CRT such as a TV.
The present invention relates to a dot matrix character and pattern display device on a screen.

[Conventional technology]

A conventional device of this type is shown in FIG. In the figure, 1 is a first memory circuit that stores pattern data of a 5×7 dot matrix, 2 is a second memory circuit that stores pattern data of a 4×6 dot matrix, and 3 is a memory circuit 1゜An address circuit for specifying arbitrary pattern data in 2; 4 a first output circuit for reading and outputting the specified pattern data from the memory circuit 1; 6 reading the specified pattern data from the memory circuit 2; 8 is a synthesis circuit that logically synthesizes the pattern data from the output circuits 4 and 6 and outputs it as a display pattern; 11 is a border that outputs a border pattern for deleting the video signal; The output circuit 10 is a control circuit for controlling the circuits 1 to 4.6.11.

Next, the operation will be explained. The control circuit 10 detects pattern display timing from the vertical synchronization signal V and horizontal synchronization signal H of the CR7 display device, and specifies arbitrary pattern data in the memory circuit 1.2 through the address circuit 3. - As an example, the pattern data specified in the storage circuit 1 is shown in FIG. 3, and the pattern data specified in the storage circuit 2 is shown in FIG. and sequentially read out the dot matrix patterns.

At this time, the control circuit 10 controls the pattern data from the output circuit 4.6 to be synthesized with a shift of half a dot in the vertical and horizontal directions in the display pattern. A logical sum as shown in FIG. 5 is synthesized. Furthermore, when the control circuit 10 operates the border output circuit 11, a border pattern as shown in FIG. 6 is sent to the CR7 display device, and a rectangular border pattern as shown in FIG. 7 is displayed on the CRT screen. A pattern with is displayed.

[Problem that the invention seeks to solve]

In conventional screen display devices, the border pattern for deleting video signals is fixed regardless of the pattern data to be displayed, so when a pattern with borders is viewed on a CRT screen, The black area of the border was very thick (there was a problem that it seriously spoiled the aesthetic appearance).

This invention was made in view of the problems of the conventional ones as described above.The display pattern on the CRT screen is clearly distinguished from the background image by the black border, and it is not only easy to see, but also aesthetically pleasing. To obtain a screen display device capable of creating a border that does not cause damage.

[Means for solving problems]

The screen display device according to the present invention uses pattern data that is equal to the logical sum of four pattern data obtained by shifting the pattern data to be displayed vertically and horizontally, for example, by half a dot, as the border pattern data. It is.

[Effect]

The screen display device according to the present invention uses pattern data created from the data to be displayed as border pattern data, so when the display pattern and the border pattern are combined on the CRT screen, the black border area is the minimum required area.

〔Example〕

Hereinafter, an embodiment of the present invention will be explained with reference to the drawings, taking as an example a case of 5×7 dot matrix display.

FIG. 1 shows a screen display device according to an embodiment of the present invention,
In the figure, 1 is a first memory circuit that stores the pattern data of the 5×7 dot matrix shown in FIG. 3, and 2 is the first memory circuit that stores the pattern data of the 4×6 dot matrix shown in FIG. 3 is the second memory circuit connected to the first memory circuit; A second memory circuit 1.2 is an address circuit for specifying arbitrary pattern data in 2, and 4 is a first memory circuit that reads specified pattern data from the first memory circuit 1 at a first timing and sequentially outputs it. The output circuit 5 is from the first storage circuit 1;
A second output circuit reads and sequentially outputs designated pattern data at a second timing; 6 is a second storage circuit 2;
7 is a third output circuit that reads and sequentially outputs specified pattern data at a third timing, and 7 is a fourth output circuit that reads and sequentially outputs specified pattern data from the second storage circuit 2 at a fourth timing. output circuit, 8 is the first
゜A first synthesis circuit that logically synthesizes pattern data from the third output circuit 4.6 and outputs this as a display pattern; 9 is a second synthesis circuit; A second synthesis circuit 10 which logically synthesizes the pattern data from the fourth output circuit 5.7 and outputs this as a edging pattern for deleting the video signal.
is a control circuit that controls the circuits 1 to 7 described above.

Next, the operation of this device will be explained according to the drawings. Control circuit 1
0 obtains display timing signals T1 to T4 in the vertical direction of the screen from the vertical synchronization signal V and horizontal synchronization signal H of the CRT display device. Similarly, display timing signals T5 to T in the horizontal direction of the screen
8 is obtained from the horizontal synchronization signal H and the output clock of the device.

The first output circuit 4 outputs the pattern data in the first storage circuit 1 specified by the address circuit 3 according to the timing signals Ti, T5, and the timing signals T2. The second output circuit 5 reads and outputs according to T6.

Similarly, the pattern data in the second storage circuit 2 specified by the address circuit 3 is transferred to the timing signal T3. T7, the third output circuit 6 outputs the timing signal T4. T1
3, the fourth output circuit 7 reads and outputs.

FIG. 8 shows part of the timing signal. The figure (a) shows the vertical synchronization signal V, and the figure (-) shows the horizontal synchronization signal H1 (0).
-(f) are examples of the timing signals T1 to T4, respectively, and as is clear from the figure, the timing signals T1.
The relationship between T2 and T3. Due to the relationship of T4, the second. The pattern data outputted from the fourth output circuit 5.7 are respectively outputted from the first . The pattern data output from the third output circuit 4.6 and the display pattern are shifted by half a dot in the vertical direction.

Although not shown, the relationship between the timing signals T5 to T8 is also the same as the second. The pattern data outputted from the fourth output circuits 5.7 and 1. It is set to be shifted by half a dot in the horizontal direction from the pattern data output from the third output circuits 4 and 6.

Therefore, the first and second points designated by the address circuit 3
Assuming that the pattern data in the memory circuits 1 and 2 are as shown in FIGS. 3 and 4, respectively, and that the display pattern synthesized by the first synthesis circuit 8 is as shown in FIG.
Second. The pattern data output from the fourth output circuit 5.7 is as shown in FIGS. 9 and 10, respectively.

When the logical sum is obtained by the second synthesis circuit 9, it becomes as shown in FIG. Due to the relationship, the first
A pattern like the one shown in Figure 2 will be displayed.

In this way, in the device of this embodiment, the pattern data to be displayed is shifted by half a dot in the vertical and horizontal directions.
Since the pattern data that is equal to the logical sum of the two pattern data is used as the border pattern data, the display pattern is not only made clear by the border pattern (but also the border pattern can be created with the minimum necessary area). , it does not spoil the aesthetic appearance on the screen.

Note that although a 5×7 dot matrix is used as an example in the above embodiment, the same applies to other dot matrices, and any display device other than a CR7 display device that is capable of displaying a dot matrix may be used. By applying the present invention, the same effects as in the above embodiments can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, since the apparatus is configured to create a border pattern from the pattern data to be displayed, a border can be created around the display pattern on the CR7 screen with the minimum necessary area. This has the effect of not only making it possible to clearly distinguish the displayed pattern from the background image, but also not detracting from its aesthetic appearance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a screen display device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional screen display device,
FIG. 3 shows the data stored in the first memory circuit of the device.
FIG. 4 is a diagram showing the pattern data "do" in the second storage circuit of the device, and FIG. 5 is a diagram showing the display pattern "do" synthesized by the first synthesis circuit of the device. 6 is a diagram showing the edging pattern output from the edging output circuit, and FIG. 7 is a diagram showing the edging pattern output by the edging output circuit.
7 screen - A diagram showing "Do 1" displayed on the top, FIG. 8 is a timing chart diagram showing part of the operation timing of the device according to an embodiment of the present invention, and FIG. 9 is a diagram according to an embodiment of the present invention. A diagram showing the edging pattern data "DO" output from the second output circuit of the device, and FIG. 10 shows the edging pattern data "DO" output from the fourth output circuit of the device.
FIG. 1F is a diagram showing the edge pattern "do" synthesized by the second synthesis circuit of the device, and FIG. 12 is a diagram showing the "do" displayed on the CRT screen by the device. It is. 1.2... 1st. Second memory circuit, 3... Address circuit, 4.5.6.7... First. Second. Third. 4th output circuit, 8, 9... 1st. second synthesis circuit, 10.
...Control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A dot matrix screen display device that uses a plurality of pixels as one dot, including a first memory circuit that stores pattern data of a K×L dot matrix, and a first memory circuit that stores pattern data of a K×L dot matrix; a first address circuit for specifying arbitrary pattern data, and first and second address circuits that read and output the pattern data specified by the address circuit from the first storage circuit at first and second timings, respectively. a second memory circuit storing pattern data of an M×N dot matrix, and a second address circuit for specifying arbitrary pattern data among the data stored in the memory circuit; a third device that reads and outputs pattern data designated by the address circuit from the second storage circuit at third and fourth timings, respectively;
, a fourth output circuit, a control circuit that controls the first to fourth timings, and a first synthesis circuit that synthesizes pattern data from the first and third output circuits and outputs it as a display pattern. and a second synthesis circuit that synthesizes pattern data from the second and fourth output circuits and outputs the synthesized pattern as a display pattern. (2) The screen display device according to claim 1, wherein a single address circuit serves as the first and second address circuits. (3) The control circuit is arranged such that the pattern data outputted from the first output circuit and the pattern data outputted from the second output circuit are also combined with the pattern data outputted from the first output circuit. The pattern data output from the third output circuit, and the pattern data output from the third output circuit and the pattern data output from the fourth output circuit are vertically aligned in the display pattern. The screen according to claim 1 or 2, wherein the first, second, third, and fourth timings are controlled so as to be shifted by half a dot in both the direction and the lateral direction. Display device.