JPS61101872A - Fast fourier transform arithmetic circuit - Google Patents

Abstract

PURPOSE:To shorten the operation time and increase the rate of in-taking of the input data column by taking-in the input data column in two data memories of real number part and imaginary number part alternately when the input column is of real number data only. CONSTITUTION:The operation of the real number part is performed by a data memory 22, a multiplier circuit 24, and an adder-subtractor 25, and that of the imaginary number part is done by a data memory 23, a multiplier circuit 26, and an adder-subtractor 27. A fast fourier transform arithmetic circuit needs at least four clocks in order to perform the butterfly operation of the input data constituted only by the real number part. Therefore, when the input data column is of real number part only, the data is so controlled as to be taken-in by memories 22 and 23 alternately. In this manner even if the frequency of the internal clock is 1/2 of that of the clock that controls the entire system, all the data columns can be stored in the memories 22 and 23 without lowering transmission time to 1/2. Also, two pieces of data can be transmitted to the arithmetic circuit by one clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fast Fourier transform calculation circuit used in a fast Fourier transform device.

[Conventional technology]

Fast Fourier transform performs Fourier transform on a data string indicated by 2fi by rearranging the data string according to a method called bit reverse ordering and repeating two-point Fourier transform called butterfly operation on the rearranged data string. be. This fast Fourier transform arithmetic circuit is composed of two arithmetic circuits: an arithmetic circuit that operates on real part data and an arithmetic circuit that operates on imaginary part data. The real part data calculation circuit includes a multiplication circuit, an addition/subtraction circuit, and a data memory for performing calculations on the real part data. The calculation circuit for imaginary part data is
It has a multiplication circuit, an addition/subtraction circuit, and a data memory for calculating imaginary part data.

In a conventional arithmetic circuit, a data string whose bits have been rearranged in reverse order is real number data, so it is taken into the data memory of the real number data arithmetic circuit. A two-point Fourier transform calculation is performed in a real number data calculation circuit. Among the data obtained as a result of the calculation, the real part data is stored in the data memory of the real part data calculation circuit, and the imaginary part data is stored in the data memory of the imaginary part data calculation circuit.

In these real part data calculation circuits and imaginary part data calculation circuits, calculations are performed by pipeline processing.

Below, among the data obtained as a result of the calculation, the real part data is stored in the data memory of the real part data calculation circuit, the imaginary part data is stored in the data memory of the imaginary part data calculation circuit, and the butterfly calculation is performed. is repeated.

This fast Fourier transform calculation circuit is operated by a clock that is slower than the clock that controls the entire fast Fourier transform device, for example, a clock whose frequency is 1/2. This is because multiplication is required for the calculation of the fast Fourier transform circuit, and the multiplication circuit cannot operate at high speed.

[Problem that the invention seeks to solve]

The above-described fast Fourier transform arithmetic circuit requires at least four clocks to perform butterfly computation (two-point Fourier transform) on input data consisting only of real part data, even if the arithmetic operation is performed by pipeline processing. That is, two clocks are required to send the two data stored in the data memory to the real part data arithmetic circuit, and two clocks are required to store the two obtained data in the data memory.

In addition, since this fast Fourier transform arithmetic circuit is operated by a clock with a frequency that is, for example, half the frequency of the clock that controls the entire device, the input data string consisting only of real part data is processed by the real part data arithmetic circuit. In order to input data into the data memory, the transfer speed of the input data string must be halved. Therefore, it takes time to import the input data string.

Therefore, it is an object of the present invention to provide a fast Fourier transform arithmetic circuit that can reduce the calculation time and the input data string acquisition speed.

[Means for solving problems]

The present invention includes a real part calculation circuit including a first data memory 22, a first multiplication circuit 24, and a first addition/subtraction circuit 25, a second data memory 23, a second multiplication circuit 26, and a second In a fast Fourier transform calculation circuit equipped with an imaginary part calculation circuit consisting of an addition/subtraction circuit 27, when the input data string is only real number data, this input data string is transferred to the first data memory 22 and the second data memory. This is a fast Fourier transform calculation circuit characterized in that it is provided with means for controlling the data to be taken in alternately into the 23.

[Effect]

The first data memory 22, the first multiplication circuit 24, and the first addition/subtraction circuit 25 perform calculations on the real part. The second data memory 23, the second multiplication circuit 26, and the second addition/subtraction circuit 27 perform calculations on the imaginary part. If the input data string is a data string containing only real parts, the first
Data is taken in alternately into the data memo IJ 22 and the second data memory 23. Among the calculation results, the real part data is stored in the data memory 22, and the imaginary part data is stored in the data memory 23.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

The Fourier transform of N points is W N=e −1+2 ”' M), then the Fourier transform output X (k) is X(k)=
(1/N) Σx (n) WN ik When calculated, approximately N2 multiplications and approximately N2 additions and subtractions are required. Therefore, a fast Fourier transform algorithm is known that reduces the number of calculation circuits and shortens the calculation time by repeating two-point Fourier transform called butterfly calculation. Since the butterfly operation is a two-point Fourier transform, the real part of the Fourier transform output is expressed as X o, X l, and the imaginary part Yo,
Y, if the input data is xOn xl +, then Xo =
(x(1'+xl)/2.Yo =OX+ = (X
o X+ )/2. Y+=0.

An example of a fast Fourier transform circuit using the above algorithm is shown in FIG. 5 and will be described. This Fourier transform circuit generates an input data string x(0) of 8 points.

Fourier transform outputs of x (1), x (2), -...-, x (7) X (0), X (1), X (2
), ..., X (7) is required.

The input data strings x(0) to x(7) are supplied to a rearrangement circuit 1 and rearranged in reverse bit order.

The rearrangement circuit 1 sets the order of the data string to x(0).

x(4), x(2), x(6), x(1), x
(5), x(3), x(7).

Data x(0) and x(4) are converted into two-point Fourier transform circuit 2
is supplied to Data x(2) and x(6) are supplied to a two-point Fourier transform circuit 3. Data X(1) and x(5
) are supplied to the two-point Fourier transform circuit 4. data x
(3) and x(7) are supplied to the two-point Fourier transform circuit 5.

The output of the two-point Fourier transform circuit 2 is supplied to addition/subtraction circuits 6 and 7. The output of the two-point Fourier transform circuit 3 is supplied to multiplication circuits 8 and 9, and multiplied by coefficients W0 and W2.

The outputs of multiplication circuits 8 and 9 are supplied to addition and subtraction circuits 6 and 7. A butterfly operation is performed by these addition/subtraction circuits 6, 7 and multiplication circuits 8, 9.

The output of the two-point Fourier transform circuit 4 is added to the addition/subtraction circuits 10 and 1.
1. The output of the two-point Fourier transform circuit 5 is supplied to multiplication circuits 12 and 13, and multiplied by coefficients WO and W2. The outputs of multiplication circuits 12 and 13 are supplied to addition and subtraction circuits 10 and 11.

A butterfly operation is performed by these addition/subtraction circuits 10.11 and multiplication circuits 12.13.

The outputs of the adder/subtractor circuits 6 and 7 are the adder/subtractor circuit 14°15.1
Delivered on 6.17. The outputs of the addition/subtraction circuits 10 and 11 are supplied to multiplication circuits 18, 19, 20, and 21, and the coefficient w
', Wl, WZ, and vJ3 are multiplied. The outputs of the multiplication circuits I8.19 and 20.21 are added to the addition/subtraction circuit 14.
．． Supplied on 15th, 16th and 17th. These addition/subtraction circuits 1
4, 15.16.17 and multiplication circuits 18, 19, 20.
21 performs a butterfly operation.
11° addition/subtraction circuit 14, 15, 1
From 6.17, the Fourier transform outputs X (0), X (
1) , X (2) , X (3) , X (4
), X (5), X (6), and X (7) are output.

An embodiment of the present invention is used in a fast Fourier transform arithmetic circuit as described above.

In FIG. 1, 22 and 23 are data memories.

The data memories 22 and 23 are loaded with data whose bits have been rearranged in reverse order by the acquisition circuit shown in FIG.
taken in alternately. From the data taken into the data memories 22 and 23, a multiplier 24 and an adder/subtractor 25 perform calculations on the real part, and a multiplier 26 and an adder/subtractor 27 perform calculations on the imaginary part. A plurality of these operations are simultaneously performed in parallel by pipeline control. The obtained real part data is stored in the data memory 22.
The imaginary part data is stored in the data memory 23.

A capture circuit for alternately fetching data rearranged in reverse bit order into the data memories 31 and 32 includes:
It is constructed as shown in FIG.

In FIG. 2, registers 33 and 34 are operated by an external clock supplied from a terminal 35, and register 36 is operated by an external clock supplied from a terminal 35.
and 37 are operated by an internal clock supplied from a terminal 38. The external clock is a clock with twice the frequency of the internal clock. The entire device is controlled in synchronization with an external clock. The arithmetic circuit is controlled in synchronization with the internal clock. Data string X Dr X l+ X ! whose bit paths have been rearranged. +X 3・・・・・・
is supplied to the register 33 from the input terminal 39 in synchronization with an external clock, as shown in FIG. 3A. register 3
The output of 3 is supplied to register 36 and is also delayed through register 34 and supplied to register 37.

Registers 36 and 37 are supplied with a common internal clock. Therefore, the data strings are taken out alternately from the register 36 and the register 37, and from the output terminal 40
+Xl+X3+XS... is taken out and output terminal 41 or X-2+XO+
+X4... is taken out. Output terminal 40
The output from the output terminal 4 is stored in the data memory 22, and
The output from 1 will be stored in data memory 23.

In this way, the input data strings are taken into the data memories 22 and 23 alternately, so even if the internal clock of the arithmetic circuit has half the frequency of the external clock, the transfer time is reduced to 1/2. All data strings can be stored in the data memories 22 and 23 without having to reduce the number of data to 2.

Note that registers 36 and 37 and data memories 22 and 23
By inserting the recombinant circuit shown in FIG. 4 between them, the data strings to be taken into the data memories 22 and 23 can be exchanged, improving versatility.

In FIG. 4, 42, 43, 44, and 45 are buffers. The output from register 36 is supplied to buffers 42 and 43 from input terminal 46.

The output from register 37 is supplied to buffers 43 and 45 from input terminal 47. The outputs of buffers 43 and 45 are supplied to output terminal 50, and the outputs of buffers 42 and 44 are supplied to output terminal 51. A control signal is supplied from terminal 48. This control signal is supplied to buffers 43 and 44, and inverter 49
The signal is supplied to buffers 42 and 45 via the control signal, and recombination is performed by this control signal.

When the control signal is at a low level, data supplied from the input terminal 46 is taken out from the output terminal 50, and data supplied from the input terminal 47 is taken out from the output terminal 51. When the control signal becomes high level, the data supplied from the input terminal 46 is taken out from the output terminal 51, and the data supplied from the input terminal 47 is taken out from the output terminal 50.

A butterfly calculation is performed from the data alternately stored in the data memories 22 and 23 by the following steps synchronized with the clock. As mentioned above, the butterfly operation is: Xo ”= (xo +) (,) /2. Yo = O
Xl=(xoXI)/2. This is to perform the calculation of Y+ =0. Data x0 is stored at address 0 of the data memory 22 in FIG. 1, data x1 is stored at address 0 of the data memory 23, and the real parts X, , 0
The imaginary parts Y o and Y r of the Fourier transform output are stored at addresses 0 and 1 of the data memory 23, respectively.
It is assumed that each address is stored separately.

In step 1, data x0 is read out of the data stored in the data memory 22 and supplied to the register 52. Data x is successively extracted from the data stored in the data memory 23 and supplied to the register 53.

In step 2, data x1 from the register 53 is sent to the multiplier 2.
4 and the multiplier 24 receives the coefficient 1 from the coefficient memory 28.
72 is supplied.

In step 3, the multiplier 24 outputs the data x and the coefficient 1/2.
Multiplication with x1/2 is performed, and the multiplied data x1/2 is latched into a register within the multiplier 24. Data x from register 52
0 is supplied to the multiplier 24, and the coefficient memory 2 is supplied to the multiplier 24.
8 supplies the coefficient 1/2.

In step 4, adder/subtractor 2 is input from the register in multiplier 24.
5 is supplied with x, /2. Multiplier 24 outputs data x
Multiplication of 0 and coefficient 172 is performed, and the multiplication data x0/2
is latched into a register within multiplier 24. register 5
2, the data X0 is supplied to the multiplier 24, and the coefficient 1/2
is supplied to the multiplier 24. At this time, calculation of the next data is started in parallel from step 1.

In step 5, from the register in the multiplier 24, the adder/subtracter 2
5 is supplied with multiplication data x0/2, (xo-xl)/
2 is calculated, and (Xo-xI>/2 is supplied to the register 54. Data of 0 is supplied to the register 55. The multiplier 24 multiplies the data x0 by the coefficient 1/2, and the multiplication Data x0/2 is latched into a register within multiplier 24.

In step 6, the output of register 54 (Xo −XI)/
2 is stored in the data memory 22 as the Fourier transform output XI. Output 0 from register 55 is stored in data memory 23 as Fourier transform output Y1. Multiplier 2
Multiply data x0/2 from the register in 4 to the adder/subtractor 25
is supplied, (xo +x,)/2 is found, and (x0
+X, )/2 is provided to register 54.

In step 7, butterfly computations for other data are performed in parallel, but the state of step 6 is maintained for the butterfly computations for data x0 and X.

In step 8, the output of register 54 (X0+X1)/2
is the Fourier transform output X. The data is stored in the data memory 22. Output 0 from register 55 is stored in data memory 23 as Fourier transform output Y0.

This butterfly calculation step is performed in parallel with butterfly calculations on other data by pipeline control. In this way, by storing data alternately in the data memories 22 and 23 and then performing calculations, a Fourier transform output is required at least once every three clocks. In other words, since the two data to be Fourier transformed are stored in separate data memories, it takes one clock to send these two data to the real part data arithmetic circuit, and the two obtained data are the same data. This is because since it is stored in memory, two clocks are required to store the obtained data.

In addition, in the calculation process of fast Fourier transform, the result of the first butterfly calculation has an imaginary part of 0.

Therefore, if all the obtained data is not stored in the data memory 22, which stores real part data, but is stored alternately in the data memory 22 and the data memory 23, when performing the next butterfly operation, two data are processed at the same clock. One data can be sent to the arithmetic circuit, and the Fourier transform output can be obtained in three clocks for the next butterfly operation.

FIG. 5 shows an embodiment in which four-point Fourier transform is performed on data stored alternately in data memories 22 and 23.

The four-point Fourier transform performs the calculation shown in the following equation.

Xe = (Xo 1X, +x, +x:l)/4. y
o = 05: Xt = (xo Xz)/4+ yl = (-x
+ 1X3) / 4Xz = (X(l Xt +)
c, X:I)/41 YZ =OX3 = (xo
-XZ)/4. Y:l = (x+ -X3)/4 5th
The data memory 22 in the figure stores xo at address 0 and x2 at address 2, and the data memory 23 stores x3 at address 0 and X at address 2, and the four-point Fourier transform output. The real parts Xo, X11X21X3 are stored at addresses 0, 1, 2, and 3 of the data memory 22, respectively, and the imaginary part Y0゜Y r + Y z + Y s
+ indicates addresses 0, 1, 2, and 3 of the data memory 23.
It is assumed that each address is stored separately.

In step 1, xo is read from the data stored in the data memory 22 and supplied to the register 52. From the data stored in the data memory 23,
, are successively output and supplied to the register 57.

In step 2, data x0 from register 52 is sent to multiplier 2.
4, and the coefficient 1/4 is supplied from the coefficient memory 28 to the multiplier 24. Data x1 is supplied from the register 57 to the multiplier 26, and coefficient 1/4 is supplied from the coefficient memory 29 to the multiplier 26.

In step 3, xo/4 is transferred from the multiplier 24 to the adder/subtractor 25.
is supplied. x1/4 from the multiplier 26 to the adder/subtractor 27
is supplied. Data x2 is read from data memory 22 and supplied to register 52. Data x3 is read from data memory 23 and supplied to register 57.

In step 4, data x is sent from the register 57 to the multiplier 26.
3 is supplied. Coefficient 174 is supplied from coefficient memory 29 to multiplier 26 .

In step 5, x3/4 is added to the adder/subtracter 27 from the multiplier 26.
(-xl+)C3)/4 is calculated. Data x2 is supplied from register 52 to multiplier 24, and coefficient 1/4 is supplied from coefficient memory 28 to multiplier 24. Data x3 is supplied from the register 57 to the multiplier 26, and coefficient 1/4 is supplied from the coefficient memory 29 to the multiplier 26.

In step 6, from the adder/subtractor 27, (-x, +x3)/4
is supplied to register 55. x2/4 from multiplier 24
is supplied to the adder/subtractor 25. x, /4 from multiplier 26
is supplied to the adder/subtractor 27. Data x2 is supplied from register 52 to multiplier 24, and coefficient 1/4 is supplied from coefficient memory 28 to multiplier 24. Data X2 is supplied from the register 57 to the multiplier 26, and coefficient 1/4 is supplied from the coefficient memory 29 to the multiplier 26.

In step 7, (Xo-x2)/4 is supplied from the adder/subtractor 25 to the register 54. From the multiplier 24 X z /
4 is supplied to the adder/subtractor 25, and (x.

10Xz)/4 is calculated. From the adder/subtractor 27 (X++
X3)/4 is provided to register 58.

x3/4 is supplied to the adder/subtractor 27. At this time, calculation of the next data is started in parallel from step 1.

In step 8, (Xo-Xz)/4 is sent from the register 54 to the data memory 22 as the real part Fourier transform output xI.
can be stored in From register 55 (-XI +x3)
/4 is stored in the data memory 23 as the Fourier transform output YI of the imaginary part. From the adder/subtractor 27 (xl
)/4 is supplied to register 55.

In step 9, the calculation step of Fourier transform of other data is continued, but the data Xo"
Regarding the calculation of the Fourier transform of 'X3, the state of step 8 is maintained.

In step 10, from register 54 (Xo −X2)/
4 is the real part of the Fourier transform output X3.

The data is stored in the data memory 22. From register 55 (X
I 1X3 )/4 is the Fourier transform output Y3 of the imaginary part
It is stored in the data memory 23 as .

(XI +x3)/4 from the register 58 is added to the adder/subtractor 25
(Xo +X+ +Xz +X3)/4 is determined and supplied to the register 54. Data of O is supplied to the register 55.

In step 11, from the register 54 (x0+x+ +X
2+)C3)/4 is stored in the data memory 22 as the real part Fourier transform output X0. Data 0 from the register 55 is stored in the data memory 23 as the Fourier transform output Yo of the imaginary part.

(x++X3)/4 is supplied from the register 58 to the adder/subtractor 25, and (Xo XI''XZ X3)/4 is determined and supplied to the register 54.

In step 12, from register 54 (xo −X1+X
2X:l)/4 is stored in the data memory 22 as the real part Fourier transform output X2. Data 0 from the register 55 is stored in the data memory 23 as the Fourier transform output Y2 of the imaginary part.

In the embodiments described above, the coefficient memories 28 and 29 are
It may be configured with one coefficient memory.

〔Effect of the invention〕

According to this invention, the input data strings are taken into the data memories 22 and 23 alternately. Therefore, even if the internal clock of the arithmetic circuit has half the frequency of the clock that controls the entire device, the transfer time will be half the frequency.
All data columns can be stored in the data memory 22 without
and 23. Furthermore, according to the present invention, since the input data strings are stored alternately in the data memories 22 and 23, two pieces of data can be sent to the arithmetic circuit with one clock. Therefore, the butterfly calculation, which conventionally required at least 4 clocks, can be performed in 3 clocks, and the 4-point Fourier transform, which conventionally required at least 8 clocks, can be performed in 6 clocks, reducing the processing time of the calculation. Ru.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of this invention, FIG. 2 is a block diagram of a capture circuit in an embodiment of this invention,
FIG. 3 is a waveform diagram used to explain the acquisition circuit, and FIG. 4 is a block diagram of a recombination circuit in an embodiment of the present invention.
FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is a block diagram of an example of a fast Fourier transform circuit to which the present invention is applied. 22.23: Data memory, 24.26: Multiplication circuit, 2
5.27: Addition/subtraction circuit.

Claims (1)

[Claims] A real part arithmetic circuit consisting of a first data memory, a first multiplication circuit, and a first addition/subtraction circuit; a second data memory, a second multiplication circuit, and a second addition/subtraction circuit; In the fast Fourier transform calculation circuit, when the input data string is only real number data, the input data string is alternately stored in the first data memory and the second data memory. A fast Fourier transform calculation circuit, characterized in that it is provided with means for controlling the input.