JPS60164868A - Fast fourier transforming device - Google Patents

Abstract

PURPOSE:To enable a device of improved processing speed by rearranging strings of digital signal data of mX2<n> length, dividing said strings into a data string of m points, Fourier-transforming the m points and repeating butterfly arithmetic of an output. CONSTITUTION:A figure shows one of examples of a data string indicating the length of a data string by 3X2<n> in case of n=4. Twelve data x0-x11 are supplied to a string rearranging circuit 1, and are rearranged in the order of x0, x4, x8, x2, x6, x10 x1, x5, x9, x3, x7, and x11. Data strings x0, x4, and x8 are supplied to a three-point Fourier transforming circuit 2A, and equally each of data strings is supplied to three-point Fourier transforming circuits 2B, 2C, and 2D. A butterly arithmetic circuit 3A butterfly-calculates outputs of the three-point Fourier transforming circuits 2A and 2B, a butterfly arithmetic circuit 3B butterfly-calculates outputs of the three-point Fourier transforming circuits 2C and 2B. The outputs of the circuits 3A and 3B are supplied to a butterfly arithmetic circuit 4 to obtain Fourier transforming outputs y0-y11.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a fast Fourier transform device used to calculate the power spectrum, correlation, convolution, etc. of a digital video signal.

"Background Art and Its Problems" A fast Fourier transform processor is used to calculate the power spectrum, correlation, and convolution of digital video signals. Conventionally, this fast Fourier transform processor has been configured to be applied only to data strings having a length that is a power of 2, for example, 1024.

For example, an NTSC video signal has a frequency of 4 fsc (fs
c: color subcarrier frequency), the effective number of samples in one horizontal section is 768. In addition, when digitizing a component video signal, the number of samples is 5 lines.
In both the case of 25 lines and the case of 625 lines, the sampling frequency is 13.5 MHz and the number of samples in one horizontal section is defined as 720 samples or more.

Therefore, in order to process a digital video signal using a conventional fast Fourier transform processor, a large number of 0 or blank level values are added to the video signal as dummy data, and the number of samples is increased to a power of 2, such as 1024. It was necessary to expand and process it. Therefore, there was a waste of processing time, resulting in a problem of lowering the processing speed.

``Object of the Invention'' The present invention aims to eliminate wasteful processing and speed up processing by realizing a fast Fourier transform device that can directly process data sequences approximately equal in number to input digital signal data sequences. It is an object of the present invention to provide a fast Fourier transform device with improved performance.

"Summary of the Invention" The present invention provides means for rearranging a digital signal data string of length mx2, dividing the rearranged data string into data strings each having m points, and This is a fast Fourier transform device which is equipped with means for performing Fourier transform of points and means for repeating butterfly calculation of the Fourier transform output of each m point, and is adapted to perform Fourier transform on one isotal signal data string of length m×2. .

"Embodiment" An embodiment of the present invention will be described below with reference to the drawings.

One embodiment of the invention is used, for example, to process digital video signals. As mentioned above, in the NTSC Near 7 video signal digitized with a 4 fsc sampling pulse, the number of effective samples in the horizontal section is 768. Further, the number of samples of the digital component video signal is set to be 720 or more. Therefore,
The length of the input data string suitable for the fast Fourier transform device used for digital video signal processing is 768 or 7.
20 are possible. However, the length of the input data string is 72
The fast Fourier transform device of 0 is incapable of processing data strings with a length of 720 or more, and is not sufficient for digital component video signals. Therefore, in one embodiment of the present invention, the length of the input data string is set to 768. By setting the length of the input data string to 768,! 0
, the effective Sansol data of the NTSC video signal can be directly processed, and the data of the component video signal can also be processed by adding some dummy data.

Fourier transform X (k
) is defined as W N=== e −+ (2π/N). Therefore, an N-point Fourier transform of a data string of length N requires exactly one multiplication. For example, a Fourier transform of a data string of length N of 768 requires 7682 multiplications.

Therefore, by dividing the data string and performing Fourier transform, the number of multiplications can be reduced. In other words, the Fourier transform of a data string of length N is performed by dividing the N-point data string into N/2-point data strings and performing Fourier transform on each, when the length N is an even number. If is an even number, it can be determined by dividing the N/2 points into two data strings of 14 points and performing Fourier transform on each.

Therefore, the Fourier transform of a data string with a length N of (N"mX2n) is derived from the Fourier transform of m points, and this reduces the number of multiplications. For example, the Fourier transform of a data string with a length N of 768 is (768=3X2) can be calculated from the Fourier transform of three points.In other words,
Divide the data string of length 768 into data strings of 3 points each,
A 3-point Fourier transform is performed on each data string, and the output of the 3-point Fourier transform is obtained by repeating the butterfly operation.

As an example of a data string obtained from three-point Fourier transform,
FIG. 1 shows an example in which the length N of the data string is 3×2n, where n=4. In Fig. 1, 1 is a rearrangement circuit, and 12 data strings x
(11xl l X2 + X3"'
6゜X10+ xl+ X5+ xo, x3. xl
, Xl+, and the data strings XO, X4 .
X8 is supplied to the 3-point Fourier transform circuit 2A, and the data string x21 x51 xto is supplied to the 3-point Fourier transform circuit 2B.
The data strings X1+X5+xQ are supplied to the three-point Fourier transform circuit 2C, and the data strings x3. X7.
X11 is supplied to the three-point Fourier transform circuit 2D.

The rearranging circuit 1 rearranges the data as follows: data 6- column xo, x+, xz, X31 X41 x5.
xa, X71 xa, x9. x+o.

A three-digit data number 000,001,002°010.
011.012,100,101.

It can be obtained by adding 102.110, 111, and 112 and reversing the digit order of each term.

The three-point Fourier transform circuits 2A, 2B, 2C, and 2D output the Fourier transform in the case of N-3 using the above-mentioned formula 0.
It is realized by hardware or software based on two types.

The outputs of the three-point Fourier transform circuits 2A and 2B are supplied to the butterfly calculation circuit 3A, and the outputs of the three-point Fourier transform circuits 2C and 2D are supplied to the butterfly calculation circuit 3B.

A butterfly calculation circuit 3A performs butterfly calculation on the output of the three-point Fourier transform circuit 2A and the output of the three-point Fourier transform circuit 2B.

A butterfly calculation circuit 3B performs a butterfly calculation on the output of the three-point Fourier transform circuit 2C and the output of the three-point Fourier transform circuit 2D. The output of the butterfly calculation circuit 3A and the output of the butterfly calculation circuit 3B are supplied to the butterfly calculation circuit 4. In the butterfly calculation circuit 4, the output of the butterfly calculation circuit 3A and the output of the butterfly calculation circuit 3B are subjected to butterfly calculation, and a data string X is obtained. ~Fourier transform output yo~''11 of X11 is taken out from the butterfly calculation circuit 4.

The butterfly calculation circuits 3A, 3B, and 4 are realized by hardware or equivalent software having the configuration shown below. The butterfly arithmetic circuit 3A and the butterfly arithmetic circuit 3B have similar configurations, and both are shown in FIG. In the butterfly calculation circuit 3A, the output of the three-point Fourier transform circuit 2A is supplied to terminals 5, 6.7, and terminals 8, 9, .
10 is supplied with the output of the three-point Fourier transform circuit 2B.

In the butterfly calculation circuit 3B, the output of the three-point Fourier transform circuit 2C is supplied to terminals 5 and 6.7, and the output of the three-point Fourier transform circuit 2C is supplied to terminals 8 and 9.1.
0 is supplied with the output of the three-point Fourier transform circuit 2D. Data supplied from terminals 5, 6.7 are supplied to addition/subtraction operation circuits 11, 12.13. Terminal 8, 9.10
Data supplied from the multiplication operation circuits 14, 15.1
6, respectively, and supplied to arithmetic circuits 11, 12, and 13, respectively. The addition and subtraction outputs of the calculation circuits 11, 12, and 13 are output as butterfly calculation outputs to terminals 17°1B, 19,
Retrieved from 20.21.22.

The butterfly calculation circuit 4 is configured as shown in FIG. The output of the butterfly calculation circuit 3A is supplied to terminals 23, 24, 25, 26, 27° 28, and terminals 29, 30, .
The output of the butterfly calculation circuit 3B is supplied to 31, 32, 33, and 34. Terminals 23.24, 25, 26, 27.
28 output is addition/subtraction operation circuit 35.36.37.38
．． 39.

40 respectively. Terminals 29, 30, 31°32.
The output of 33.34 is a multiplication arithmetic circuit 41°42.43,
44, 45, and 46, respectively, and 5.

multiplied by e-6πl, respectively, and the arithmetic circuits 35 and 36°3
Supplied and delivered on 7.38.39.40 respectively. Arithmetic circuit 3
The addition and subtraction outputs of 5 to 40 are taken out to terminals 41 to 58 as butterfly calculation outputs.

The length of the data string used for video signal processing is 768
Since the Fourier transform of is (768=3X28),
Similar to the Fourier transform for a data string with a length of 12 shown in FIG. 1, this is achieved by performing Fourier transform for each three points and then repeating the butterfly calculation.

FIG. 4 shows the configuration of a reordering circuit applied to an embodiment of the present invention for reordering a data string of length 768 applied to, for example, a video signal.

In FIG. 4, 60 indicates a memory circuit. Memory circuit 6
0 has a binary number of 0.1. ．． Three types of 1 each representing 10
0 bit data (0000000000) (000,
00000,01), (0000000010) lO
− is written. First, data indicating 0 (oooooooooo) is read out from the memory circuit 60, and thereafter,
The operation in which data indicating a binary number 1 (0000000001) is read twice and then data indicating a binary number 10 (0000000010) is read once is repeated, and the read data is sequentially supplied to the addition circuit 61. be done.

62 and 63 indicate registers, the register 62 is supplied with data indicating 0 (0000000000) from the terminal 64, and the register 63 is supplied with the output of the adder circuit 61. Latch pulses are supplied to the registers 62 and 63 from terminals 65 and 66, and data from the registers 62 and 63 is selectively output by the latch pulses.

At the beginning of the rearrangement, register 62 is selected and the output of register 62 is supplied to adder circuit 61. After that, the register 63 is selected and the output of the register 63 is sent to the adder circuit 6.
1.

The adder circuit 61 first outputs data indicating O output from the memory circuit 60 (0000000000) and data indicating O output from the register 62 (0000000).
000) is added, the adder circuit 61 outputs data indicating 0 (oooooooooo), and this data is stored in the register 63. Next, the data in the register 63 and the data indicating the binary number 1 (0000000001) output from the memory circuit 60 are added, and the adding circuit 61
Data (0000000001) is output from the register 63, and this data is stored in the register 63.

Since the memory circuit 60 reads data indicating a binary number 1 twice and then reads data indicating a binary number 10, the output of the memory circuit 60 and the output of the register 63 are similarly added. By repeating the process, the addition circuit 61 outputs (ooooooooooo), (ooooo
ooool).

(0000000010), (0000000100)
.

(0000000101), (0000000110)
.

(000°ooooiooo)...... data is sequentially output.

This is because the least significant two bits are considered to be a ternary representation. In other words, the lowest number is expressed in ternary and the other numbers are expressed in binary: (oooooooooo).

(000000001), (000000002).

(000000010), (000000011).

(000000012), (ooooooloooo).

(000000101), . . .

Numbers where the lowest digit is expressed in ternary and the others are expressed in binary, and the number indicating the lowest digit is 0 is indicated by the lower two bits of 00, and the number indicating the lowest digit is 1. 0 in the lower 2 bits
The output of the adder circuit 61 is represented by 1, and the number in which the lowest digit is 2 is represented by 10, which is the lower two bits.

The output of the adder circuit 61 is supplied to a bit reverse order circuit 67. As shown in FIG. 5, the bit reverse order circuit 67 sets the least significant bit as the second most significant bit, the second least significant bit as the most significant bit, and reverses the other bits. Output data fi (000000000
0), (1000000000).

(0100000000), (0010000000)
.

13 - (1010000000), (0110000000)
.

(o o o 1o o o o o o o),...
・・・：! are sequentially supplied to the addresses of the data memory 6B.

Data memory 68 contains data string X. t Xi, X2
゜X3+ X4+ x5. ``'``・''・ is the address (0000000000).

(0000000001), (0000000010)
.

(0000000011), (ooooooooaoo)
.

(0000000101), (0000000110)
..., and by the output of the bit reverse order circuit 67, the data written to each address is read out, and the data string X is read out from the data memory 6B. .

X2561 X5121 X128113841 X6
401 x 64 +--1)".

FIG. 6 shows an example of a three-point Fourier transform circuit applied to an embodiment of the present invention.

As shown in the above equation 0, if the Fourier transform at N points is −1(2π/N) Ne−e, then the Fourier transform output X (k) is 14 − . ■From the formula, the three-point data string x(0), x(1
) , Fourier transform output of x(2) X(0) , X
(1), X(2), X(0) =■(x(0)
+x(1)x(2) )・・・・・・・・・・・・
...... ■I can't stand it.

Fourier transform output X(O) determined by the 000 formula.

x(i), X(2)(7) real part as y(0),
y(1), V(2) and the imaginary part is z(0),
When z(1) and z(2) are shown, X(0)=Y
(0) + i z (0) or 5'(0)=y(
x(0)+x(1)+x(2)L・-・0z(0)=0
...... ■ X (1) = 'I (1) + i z (1), that is, y (1) ='t, (x(0) 2
1) 2 X (2) ) ・= ■1 X (2) = V (2) 10 i z (2) 1 1
1 That is, y (2) - d (x (0) 2 X (1)
τT
)3 2 2 ■2~■ By implementing hardware that performs calculations based on formulas, a three-point Fourier transform output can be obtained.

In FIG. 6, 70 and 71 indicate data memories, and data strings x(0), x(1), x(2) are stored in the data memory 70 in advance. data memory 10
The input data stored in is calculated by the following 12 steps synchronized with the clock, and the real part data y (0) of the Fourier transform outputs X(0), X(1), and X(2) are obtained.

y(1), y(2) are stored in data memory 0, and imaginary part data z(0), z(1), z(
2) is stored in data memory 1.

That is, data x(2) is read out from the data string stored in data memory 0 in step 1 and supplied to registers 2 and 73.

Data X (
2) is supplied to the multiplication circuit 74, and data x(2) stored in the register T3 is supplied to the multiplication circuit 75. Coefficient 1 and coefficient B are supplied from coefficient memories 76 and 77 to multiplication circuit 74 and T5. Also, in this step, data x(1) is read from data memory 0 and supplied to register 2 and T3.

78, and the output J3x(2) of the multiplier circuit 75 is supplied to the ALU 19. The ALUs 78 and 79 have a memory function and a shift function, and by adding and subtracting and shifting bits, for example, the data x (
1) is supplied to multiplier circuits 74 and 75, which sell coefficients and ?
are supplied from coefficient memories 76 and 7T to multiplication circuits T4 and T5.

In step 5, data x (0) is supplied from data memory 0 to register staff 2.

In step 6, data X (
0) is supplied to the multiplication circuit 14, and the coefficient information is stored in the coefficient memory 7.
6 to a multiplication circuit 74. (1)) be harassed.

In step 7, the output a x (0) of the multiplier circuit 74 is A
LU 78 is supplied.

−18− + x (1)) is supplied to the register 80, and the ALU
It costs 79.

In step 9, the output of register 80 -x (0) c-
3°(x(2)+x(1)) is supplied to data memory 0, and the real part data y(2) of the Fourier transform output x(2) is supplied to data memory 0.
) is stored in data memory 0, and the output J of register 81 is
(-x(2)+x(1)) is supplied to data memory 1, and the imaginary part data z(
2) is stored in data memory 1. Also, in this step, 6 is supplied from the ALU 79 to the register 81 (.(2)-.(1)).

In step 10, the output of register 80 a x (0)−
y(x(2)+x(1)) is supplied to data memory 0, and the real part data y(x(2)+x(1)) of the Fourier transform output
1) is stored in the data memory 70, the output (x(2) - x(1)) of the register 81 is supplied to the data memory 71, and the imaginary part data z(
1) is stored in data memory 1.

-t-,x (2)) is supplied to the register 80, and A
A zero is supplied from LU 79 to register 81 .

Output cuff of register 80 at step 12 x (0) +
ax(1)1-Tx(2) is supplied to the data memory TO, and real part data y(0
) is stored in data memory 0, and the Fourier transform output X(
The imaginary part data z(0) of 0) is stored in the data memo I771.

Note that in steps 7 to 12, Step 6 of the Fourier transform of the following three points is performed in parallel.

The butterfly arithmetic circuit can also be constructed in a similar manner using the hardware shown in FIG. However, the coefficient memo value is memorized. The real part data required for the butterfly operation is output from data memory 0 via registers 72.73, and the imaginary part data required for the butterfly operation is output from data memory 1 via registers 82.83. be done.

The processing required for each butterfly operation is carried out by the multiplication circuit 74.7.
5 and ALUs 78 and 79, the real part data of the butterfly calculation is stored in data memory 0, and the imaginary part data of the butterfly calculation is stored in data memory 71.

“Application Example” This invention has a configuration in which, after performing m-point Fourier transform, butterfly calculation is repeated to obtain the Fourier transform output of a data string of length m×2n. A configuration may also be adopted in which a Fourier transform output of a data string having a length of m×2” is obtained by performing the transform.

Further, the present invention can also be applied to the case of performing inverse Fourier transform.

“Effects of the Invention” According to the present invention, the Fourier transform output of a data string with a length of (a
xax2 x4) total of steps (6(n+1)2°)
It is set by the step.

For example, when n = 8 (3X 2 = 768), Fourier transform can be performed in 13,824 steps.

On the other hand, in the conventional fast Fourier transform of a data string with a length of 2n, when two multipliers, two adders/subtractors, and two data memories are arranged, the transformation can be performed in (n×2n+1) steps. For example, in the case of (n=1 o ) (210=1024), 20
480 steps are required. Therefore, for example, the length is 76
When performing Fourier transformation on a video signal of 8 data strings, the processing time can be reduced by 0.675 times compared to conventional high-speed 7-lier transformation.

[Brief explanation of the drawing]

FIG. 1 is a book diagram of an embodiment of this invention, FIGS. 2 and 3 are block diagrams of a butterfly calculation circuit in this embodiment, and FIGS. 4 and 5 are an embodiment of this invention. Block diagram and connection diagram of an example of a rearrangement circuit in, No. 6
The figure is a block diagram of an example of a three-point Fourier transform circuit in an embodiment of the present invention. 1・・・・・・・・・Rearrangement circuit, 2A, 2B
, 2C. 2D・・・・・・・・・3 points Fu IJ engineering conversion circuit, 3A, 3B. 4・・・・・・・・・Butterfly calculation circuit. Agent Tadashi Sugiura Figure 4 Figure 6 767 Fi-kei Ei Toru (Tomori Tomori Gaika 74 Tosan 5 ALLJ 76 ALU Register Regis game o71 11 LSB MSB

Claims (1)

[Claims] Means for rearranging a digital signal data string of length m x 2n, dividing the rearranged data string into m-point data strings, and means for performing m-point Fourier transform on each divided data string. and means for repeating the butterfly calculation of the Fourier transformation output of each m point, and is adapted to Fourier transform the digital signal data string of length m x 2''.