JPS6095941A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6095941A JPS6095941A JP58204310A JP20431083A JPS6095941A JP S6095941 A JPS6095941 A JP S6095941A JP 58204310 A JP58204310 A JP 58204310A JP 20431083 A JP20431083 A JP 20431083A JP S6095941 A JPS6095941 A JP S6095941A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- tape
- semiconductor chip
- bed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の組立構造に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to an assembly structure of a semiconductor device.
〔発明の技術的背景およびその問題点〕第１図を参照し
て従来装置を説明する。第１図は従来装置の一構成例の
断面図である。フレームはベッドｌ、インナーリー２２
およびアウターリード３からなり、ぺ、ｌドｌの上には
Ａｇペースト弘で半導体チップ（ペレツト）Ｓがマウン
トされている。そして、半導体チップＳとインナーリー
ド−の間には金属細繊６がボンディングされ、樹脂７に
よって全体が封止されている。なお、インナーリードコ
のズレ防止のために、長手方向にポリイミドテーゾ等が
貼付される。[Technical background of the invention and its problems] A conventional apparatus will be explained with reference to FIG. FIG. 1 is a sectional view of one configuration example of a conventional device. Frame is bed L, inner 22
and an outer lead 3, and a semiconductor chip (pellet) S is mounted on top of the lead and lead 3 using Ag paste. Fine metal fibers 6 are bonded between the semiconductor chip S and the inner leads, and the entire structure is sealed with resin 7. In addition, to prevent the inner reedco from shifting, polyimide Tezo or the like is pasted in the longitudinal direction.
上記の如〈従来装置では、金属性のベラＰ／に有機性の
Ａｇペーストｑによって半導体チップＳが固着されてい
るために、次のような問題が生じている。In the conventional device as described above, since the semiconductor chip S is fixed to the metal blade P/ by the organic Ag paste q, the following problems occur.
■半導体チップＳのマウントに際してマウント剤が必要
になり、このマウント剤がＡｇペースト等の有機剤であ
るときはそれに含まれるＡ９゜Ｋ等が半導体チップＳに
はい上がり、Ａ１コロ−ジョン等の腐食を起こす。その
ため、耐湿性が低下するという欠点が生じる。■A mounting agent is required when mounting the semiconductor chip S, and if this mounting agent is an organic agent such as Ag paste, the A9°K etc. contained in it will creep onto the semiconductor chip S, causing corrosion such as A1 corrosion. wake up Therefore, there arises a drawback that moisture resistance is reduced.
■金属性のベッドｌ、半導体チップＳおよび樹脂ｇ等の
部材間の膨張係数の差により、ペレットクラック等を生
じ、製品の歩留りが低下するという欠点が生じる。(2) Differences in expansion coefficients among members such as the metal bed 1, the semiconductor chip S, and the resin g cause pellet cracks and the like, resulting in a reduction in product yield.
■樹脂封止の際に、金属細線６が流れて金属細線６とイ
ンナーリードコの間および金属細線６と半導体チップＳ
の間で接触不良を起こし、製品の歩留りが低下するとい
う欠点がある。■ During resin sealing, the thin metal wire 6 flows between the thin metal wire 6 and the inner lead core and between the thin metal wire 6 and the semiconductor chip S.
This has the drawback of causing poor contact between the two, which reduces product yield.
また、従来装置には特開昭３’ｌ −１１９９７５号公
報に示される如く、半導体チップを搭載したベッドとイ
ンナーリーｒの裏面に絶縁性の保持部材を接着したもの
もあるが、全６製ベツドＫＡｇペースト等で半導体チッ
プをマウントするという構成は第１図の構成例と同一で
あるので、上記の欠点を取り除くことはできない。Furthermore, as shown in Japanese Unexamined Patent Publication No. 119975/1983, some conventional devices have an insulating holding member glued to the back surface of the bed on which the semiconductor chip is mounted and the inner reel. Since the configuration in which the semiconductor chip is mounted using a bed KAg paste or the like is the same as the configuration example shown in FIG. 1, the above-mentioned drawbacks cannot be eliminated.
本発明は上記の従来技術の欠点を克服するためになされ
たもので、耐湿性の低下、ペレットクラ・ツクの発生等
を起すことがなく、製品の歩留りを向上させることので
きる半導体装置を提供することを目的とする。The present invention has been made to overcome the drawbacks of the above-mentioned prior art, and provides a semiconductor device that does not cause deterioration in moisture resistance or occurrence of pellet cracks, etc., and can improve product yield. The purpose is to
上記の目的を実現するため本発明は、インナーリードと
アウターリードのみでベッドのないフレームのチンゾマ
ウント領域に、ポリイミドチーシー等の樹脂テープを貼
付け、その上に半導体チップをマウントして樹脂封止し
た半導体装置を提供するものである。In order to achieve the above-mentioned object, the present invention has been developed by attaching a resin tape such as polyimide CHIC to the mount area of a frame with only inner leads and outer leads and no bed, and mounting a semiconductor chip thereon and sealing the semiconductor with resin. It provides equipment.
第一図を参照して本発明の一実施例を説明する。 An embodiment of the present invention will be described with reference to FIG.
第１図は同実施例の断面図で、第１図と同一要素は同一
符号で示しである。インナーリード２およびアウターリ
ード３のみからなるフレームの半導体チップＳをマウン
トする領域（インナーリードコに囲まれた領域）に、接
着剤を付けた一すイミｒテーゾを２００℃前後で熱圧着
する。このとき、ポリイミドチーシは一定の寸法に切り
出されており、インナー＋ｒ−ｐ２を固定する役割も果
たす。FIG. 1 is a cross-sectional view of the same embodiment, and the same elements as in FIG. 1 are designated by the same reference numerals. An adhesive-applied one-swim r tezo is thermocompression bonded at around 200° C. to the area where the semiconductor chip S of the frame consisting of only the inner leads 2 and outer leads 3 is to be mounted (the area surrounded by the inner leads). At this time, the polyimide sheet is cut out to a certain size and also plays the role of fixing the inner +r-p2.
次圧フレームをマウンタでマウント部に搬送し、半導体
チップ３ｆマウント部に固着する（このときのマウント
部は、２００ ’Ｃ前後に保つ）。そして。The next pressure frame is transported to the mount part by a mounter and fixed to the semiconductor chip 3f mount part (the mount part at this time is maintained at around 200'C). and.
金属細線６をボンディングしたのち樹脂封止して、半導
体装置が完成する。After bonding the thin metal wires 6, the semiconductor device is completed by resin sealing.
なお、本発明においては半導体チップは樹脂テープに直
接マウントされ、フレームのベッドにはマウントされな
い（金属性のベッドそのものが不要な構造になっている
）ため、発熱量の少いメモリ装置、ディジタル回路装置
等に特に適している。In addition, in the present invention, the semiconductor chip is mounted directly on the resin tape and is not mounted on the bed of the frame (the structure does not require the metal bed itself), so it is possible to use memory devices and digital circuits that generate less heat. Particularly suitable for equipment, etc.
上記の如（本発明によれば、ベッドのないフレームのチ
ップマウント領域に樹脂テープを貼付け、そこに半導体
チップをマウントして樹脂封止するようにしたので、耐
湿性の低下やペレットクラックの発生等を起すことがな
（、製品の歩留りを向上させることのできる半導体装置
を提供することができる。特に、マウント剤としてＡｇ
ペーストを使わないためＡｇによるＡ１コローノヨン、
マイグレーション等を少なくして耐湿性を向上させるこ
とができ、また金属細線のボンディングにおいて接触不
良を抑えることができるのでモールドする樹脂の選択範
囲を広げることができる。As mentioned above (according to the present invention, a resin tape is pasted on the chip mounting area of the frame without a bed, and the semiconductor chip is mounted there and sealed with resin, so that moisture resistance decreases and pellet cracks occur. It is possible to provide a semiconductor device that can improve product yield without causing problems such as
Since no paste is used, A1 corona is made of Ag.
Moisture resistance can be improved by reducing migration, and contact failure can be suppressed in bonding thin metal wires, so the selection range of resins for molding can be expanded.
さらに、フレームのベッドに要したメッキコストを削減
し、ベッドのボンディングがなくなるの−（−７レーム
の汎用化を図ることかでキ、またマウントの工程を簡略
化（Ｍｏｕｎｔ ｃｕｒθ工程をなくす）してマウント
工程とボンディング工程を一体化することができる。Furthermore, the plating cost required for the frame bed can be reduced, bed bonding can be eliminated (-7) by making the frame more versatile, and the mounting process can be simplified (eliminating the mount curθ process). This allows the mounting process and bonding process to be integrated.
第１図は従来装置の一構成例の断面図、第２図は本発明
の一実施例の断面図である。
ｌ・・・ベッド、コ・・・インナーリーＰ、３・・・ア
ウターリーＰ、弘・・・Ａｇペースト、Ｓ・・・半導体
チップ、６・・・金属＋！１ｉｌＩ線、７・・・樹脂、
ｇ・・・ポリイミドテープ。
出願人代理人 猪 股 清
６１ 圓
も２ 図FIG. 1 is a sectional view of an example of the configuration of a conventional device, and FIG. 2 is a sectional view of an embodiment of the present invention. l...Bed, Co...Innerly P, 3...Outerly P, Hiroshi...Ag paste, S...Semiconductor chip, 6...Metal+! 1ilI line, 7...resin,
g...Polyimide tape. Applicant's agent Kiyoshi Inomata61 Enmo2 Figure
Claims (1)
ームと、 前記インナーリードを相互に固定するように、半導体チ
ップをマウントする領域に貼付けられた高抵抗で化学的
に安定な樹脂テープと、この樹脂テープにマウントされ
た半導体チップと、 前記インナーリーｒ、樹脂テープおよび半導体チ・ツブ
を封止する樹脂とを備える半導体装置。 コ、樹脂テープはポリイミドテーゾである特許請求の範
囲第１項記載の半導体装置う[Claims] 1. A frame consisting of inner leads and outer leads, and a high-resistance, chemically stable resin tape affixed to an area where a semiconductor chip is mounted so as to fix the inner leads to each other. A semiconductor device comprising: a semiconductor chip mounted on the resin tape; and a resin sealing the inner reel, the resin tape, and the semiconductor chip. h. The semiconductor device according to claim 1, wherein the resin tape is a polyimide tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58204310A JPS6095941A (en) | 1983-10-31 | 1983-10-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58204310A JPS6095941A (en) | 1983-10-31 | 1983-10-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6095941A true JPS6095941A (en) | 1985-05-29 |
Family
ID=16488362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58204310A Pending JPS6095941A (en) | 1983-10-31 | 1983-10-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6095941A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6318652A (en) * | 1986-07-11 | 1988-01-26 | Nec Corp | Manufacture of semiconductor device |
| FR2624651A1 (en) * | 1987-12-14 | 1989-06-16 | Sgs Thomson Microelectronics | METHOD FOR PLACING AN ELECTRONIC COMPONENT AND ITS ELECTRICAL CONNECTIONS ON A SUPPORT AND THE PRODUCT THUS OBTAINED |
| FR2673041A1 (en) * | 1991-02-19 | 1992-08-21 | Gemplus Card Int | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT MICROMODULES AND CORRESPONDING MICROMODULE. |
| USRE35578E (en) * | 1988-12-12 | 1997-08-12 | Sgs-Thomson Microelectronics, Inc. | Method to install an electronic component and its electrical connections on a support, and product obtained thereby |
| KR100352120B1 (en) * | 1996-12-06 | 2003-01-24 | 앰코 테크놀로지 코리아 주식회사 | Structure of lead frame and semiconductor package using the same |
| KR100426330B1 (en) * | 2001-07-16 | 2004-04-08 | 삼성전자주식회사 | Ultra-Thin Semiconductor Package Device Using a Support Tape |
-
1983
- 1983-10-31 JP JP58204310A patent/JPS6095941A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6318652A (en) * | 1986-07-11 | 1988-01-26 | Nec Corp | Manufacture of semiconductor device |
| JPH0582981B2 (en) * | 1986-07-11 | 1993-11-24 | Nippon Electric Co | |
| FR2624651A1 (en) * | 1987-12-14 | 1989-06-16 | Sgs Thomson Microelectronics | METHOD FOR PLACING AN ELECTRONIC COMPONENT AND ITS ELECTRICAL CONNECTIONS ON A SUPPORT AND THE PRODUCT THUS OBTAINED |
| US4908937A (en) * | 1987-12-14 | 1990-03-20 | Sgs-Thomson Microelectronics, S.A. | Method to install an electronic component and its electrical connections on a support, and product obtained thereby |
| USRE35578E (en) * | 1988-12-12 | 1997-08-12 | Sgs-Thomson Microelectronics, Inc. | Method to install an electronic component and its electrical connections on a support, and product obtained thereby |
| FR2673041A1 (en) * | 1991-02-19 | 1992-08-21 | Gemplus Card Int | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT MICROMODULES AND CORRESPONDING MICROMODULE. |
| KR100352120B1 (en) * | 1996-12-06 | 2003-01-24 | 앰코 테크놀로지 코리아 주식회사 | Structure of lead frame and semiconductor package using the same |
| KR100426330B1 (en) * | 2001-07-16 | 2004-04-08 | 삼성전자주식회사 | Ultra-Thin Semiconductor Package Device Using a Support Tape |
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