JPH0366152A - Semiconductor integrated circuit module - Google Patents
Semiconductor integrated circuit moduleInfo
- Publication number
- JPH0366152A JPH0366152A JP1203217A JP20321789A JPH0366152A JP H0366152 A JPH0366152 A JP H0366152A JP 1203217 A JP1203217 A JP 1203217A JP 20321789 A JP20321789 A JP 20321789A JP H0366152 A JPH0366152 A JP H0366152A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- module
- leads
- coating material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 238000007789 sealing Methods 0.000 claims abstract description 12
- 230000006835 compression Effects 0.000 claims abstract description 7
- 238000007906 compression Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005452 bending Methods 0.000 claims description 4
- 238000000465 moulding Methods 0.000 abstract description 9
- 239000000853 adhesive Substances 0.000 abstract description 6
- 230000001070 adhesive effect Effects 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 239000000470 constituent Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路モジュールの構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor integrated circuit module.
第４図は従来の半導体集積回路パッケージを示す斜視図
、第５図は第４図に示した半導体集積回路パッケージを
所定のモジュール基板に実装した状態を示す斜視図、第
６図は第５図のように実装した後、さらに成形し、半導
体集積回路モジュールとした状態を示す斜視図、第７図
は第６図の■−■線の半部断面図である。FIG. 4 is a perspective view showing a conventional semiconductor integrated circuit package, FIG. 5 is a perspective view showing the semiconductor integrated circuit package shown in FIG. 4 mounted on a predetermined module board, and FIG. FIG. 7 is a perspective view showing a semiconductor integrated circuit module after being mounted and further molded as shown in FIG.
図において、１はリードであり、インナリード１ａと外
部リードｌｂとから構成されている。２はパッケージ封
止樹脂、３はモジュール用基板、４は上記外部リードｌ
ｂをモジュール用基板３上に設けられた電極（図示せず
〉に接続するための接着材、５はモジュール用封止樹脂
、ｌＯは半導体集積回路チップ、１１はダイパッド、１
２は金属細線である。In the figure, 1 is a lead, which is composed of an inner lead 1a and an outer lead lb. 2 is a package sealing resin, 3 is a module substrate, and 4 is the above external lead l.
an adhesive for connecting b to an electrode (not shown) provided on the module substrate 3; 5 a sealing resin for the module; IO a semiconductor integrated circuit chip; 11 a die pad;
2 is a thin metal wire.
次に製造工程について説明する。半導体集積回路チップ
１０はリードフレームに設けられたダイパッド１１に接
着され、半導体集積回路チップｌＯ上の電極と外部リー
ドｉｂと直結しているインナリード１ａとを金属線１１
１２により接続した後、パッケージ用封止樹脂２で樹脂
封止し、さらに所定の形状に外部リードｌｂを加工する
。このようにして第４図に示す半導体集積回路パッケー
ジができ上がる。Next, the manufacturing process will be explained. The semiconductor integrated circuit chip 10 is bonded to a die pad 11 provided on a lead frame, and the electrodes on the semiconductor integrated circuit chip 10 are connected to the inner leads 1a directly connected to the external leads ib using metal wires 11.
12, the external leads lb are sealed with a package sealing resin 2, and the external leads lb are further processed into a predetermined shape. In this way, the semiconductor integrated circuit package shown in FIG. 4 is completed.
次にモジュール用基板３上に設けられた電極（図示せず
〉と上記半導体集積回路パッケージの外部リード１ｂと
を半田等の接着材４で接続実装する（第５図参照）。さ
らにこの状態でモジュールとしての所定の形状にモジュ
ール用封止樹脂５で成形し半導体集積回路モジュールの
製造が完了する（第６図、第７図参照〉。Next, the electrodes (not shown) provided on the module substrate 3 and the external leads 1b of the semiconductor integrated circuit package are connected and mounted using an adhesive 4 such as solder (see FIG. 5). The semiconductor integrated circuit module is molded into a predetermined shape using module sealing resin 5, and the manufacturing of the semiconductor integrated circuit module is completed (see FIGS. 6 and 7).
従来の半導体集積回路モジュールは以上のように構成さ
れているので、外部リードｌｂ、外部り−ド１ｂとモジ
ュール用基板３の電極とを接着する接着材料４．パッケ
ージ用封止樹脂２．モジュール用封止樹脂５．モジュー
ル用基板３の熱膨張係数及びヤング率がそれぞれ異なる
ために、それらの数値の差により応力が生ずることとな
り、強度の弱い外部リード部１ｂが広温度範囲での試験
において断線する等の問題点があった。Since the conventional semiconductor integrated circuit module is constructed as described above, an adhesive material 4 for bonding the external leads lb, 1b and the electrodes of the module substrate 3 is used. Sealing resin for packages 2. Sealing resin for modules 5. Since the thermal expansion coefficient and Young's modulus of the module substrate 3 are different, stress is generated due to the difference in these values, leading to problems such as the weak external lead portion 1b breaking during tests over a wide temperature range. was there.
この発明は上記の様な従来のものの問題点を除去するた
めになされたものでモジュール成形前の外部リードに後
の試験温度範囲でゴム状を保つコーティング材を曲げ加
工の圧縮側に厚くコーティングすることによってモジュ
ール用封止樹脂での封止後の広温度範囲での試験におい
て断線しない半導体集積回路モジュールを提供するもの
である。This invention was made in order to eliminate the above-mentioned problems with the conventional method. Before molding the module, the external leads are thickly coated on the compression side of the bending process with a coating material that remains rubber-like in the test temperature range. This provides a semiconductor integrated circuit module that does not break during tests over a wide temperature range after being sealed with a module sealing resin.
この発明に係る半導体集積回路モジュールは、モジュー
ル成形前の外部リードに外部リードの曲げ加工の圧縮側
に厚くゴム状態を保つコーティング材を塗布した後にモ
ジュール成形したものである。The semiconductor integrated circuit module according to the present invention is obtained by applying a thick coating material that maintains a rubber state to the external leads before the module is molded on the compression side of the bending process, and then molding the module.
この発明におけるゴム状態を保つコーティング材は、モ
ジュール成形後の信頼性試験等において、半導体集積回
路モジュールを構成する各材料の熱膨張係数の差により
外部リード部にかかる応力を吸収する。The coating material that maintains a rubber state according to the present invention absorbs stress applied to the external lead portion due to the difference in coefficient of thermal expansion of each material constituting the semiconductor integrated circuit module during a reliability test after molding the module.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は半導体集積回路パッケージをモジュール基板に
接着し、外部リードにコーティングを施した状態を示す
斜視図、第２図は第１図に示した（３）
装置をモジュール成形した状態を示す斜視図、第３図は
第２図のＩ−Ｉ線の半部断面図である。Figure 1 is a perspective view showing a semiconductor integrated circuit package adhered to a module board and coating the external leads, and Figure 2 is a perspective view showing the device shown in Figure 1 (3) molded into a module. 3 are half sectional views taken along the line II in FIG. 2.
図中、６は半導体集積回路パッケージのモジュール成形
前の外部リードｔｂに施されたコーティング材である。In the figure, 6 is a coating material applied to the external lead tb of the semiconductor integrated circuit package before module molding.
その他の構成は従来の部材と同様であるので説明を省略
する。The other configurations are the same as those of the conventional members, so explanations will be omitted.
次に組立動作について説明する。まず、半導体集積回路
チップｌＯをリードフレームに設けられたグイパッド１
１に接着し、半導体集積回路チップｌＯ上の電極とイン
ナリードｌａとを金属細線により接続した後、パッケー
ジ用封止樹脂２により樹脂封止し、外部リードｔｂを所
定の形状に加工する。その後、上記半導体集積回路パッ
ケージの外部り一ド１ｂをモジュール用基板３上に設け
られた電極に半田等の接着材４により実装する。Next, the assembly operation will be explained. First, a semiconductor integrated circuit chip 1O is mounted on a lead frame with a guide pad 1 provided on a lead frame.
1, and the electrodes on the semiconductor integrated circuit chip IO and the inner leads la are connected by thin metal wires, and then resin-sealed with a package sealing resin 2, and the outer leads tb are processed into a predetermined shape. Thereafter, the external lead 1b of the semiconductor integrated circuit package is mounted on the electrode provided on the module substrate 3 using an adhesive 4 such as solder.
次に、上記外部リード１ｂに対して、モジュール成形の
保障すべき温度範囲においてゴム状態を保つコーティン
グ材６を塗布する。このとき、第１図及び第３図に示す
ように、上記外部リードｔｂの曲げ加工の圧縮方向に肉
厚に上記コーティング材（４）
６を塗布する。Next, the external lead 1b is coated with a coating material 6 that maintains a rubber state within the temperature range that is required for module molding. At this time, as shown in FIGS. 1 and 3, the coating material (4) 6 is applied thickly in the compression direction of the bending process of the external lead tb.
その後、従来のモジュール化と同様の手順でモジュール
成形され、半導体集積回路モジュールが完成される。Thereafter, the module is molded using the same procedure as conventional modularization, and a semiconductor integrated circuit module is completed.
以上の様にこの発明によれば、モジュール成形前の外部
リードにゴム状を保つコーティング材を外部リードの曲
げ加工部の圧縮方向に肉厚に塗布したので、構成材料の
熱膨張係数の差によって外部リードにかかる応力を、こ
のコーティング材で吸収させることが出来、品質レベル
の高い半導体集積回路モジュールを得ることが出来る。As described above, according to the present invention, since the coating material that maintains a rubber-like state is applied thickly to the external lead before module molding in the compression direction of the bent portion of the external lead, the difference in thermal expansion coefficients of the constituent materials The stress applied to the external leads can be absorbed by this coating material, and a semiconductor integrated circuit module with a high quality level can be obtained.
第１図はこの発明の一実施例に係る半導体集積回路モジ
ュールについて、そのモジュール成形前に外部リード部
分をコーティングした状態を示す斜視図、第２図は第１
図のモジュール成形後の状態を示す斜視図、第３図は第
２図のＩ−ＩＩ線半部断面図、第４図は従来の半導体集
積回路パッケージを示す斜視図、第５図は第４図の半導
体集積回路パッケージをモジュール基板に実装した状態
を示す斜視図、第６図は従来の半導体集積回路モジュー
ルを示す斜視図、第７図は第６図の■−■線半部断面図
である。
図中、１はリード、１ａはインナリード、ｌｂは外部リ
ード、２はパッケージ用封止樹脂、３はモジュール用基
板、４は接着材、５はモジュール用封止樹脂、６はコー
ティング材、１０は半導体集積回路チップ、１１はグイ
パッド、１２は金属細線である。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a perspective view of a semiconductor integrated circuit module according to an embodiment of the present invention, showing a state in which the external lead portions are coated before molding the module, and FIG.
FIG. 3 is a half sectional view taken along line I-II in FIG. 2, FIG. 4 is a perspective view showing a conventional semiconductor integrated circuit package, and FIG. Fig. 6 is a perspective view showing a conventional semiconductor integrated circuit module, and Fig. 7 is a half cross-sectional view taken along the line ■-■ in Fig. 6. be. In the figure, 1 is a lead, 1a is an inner lead, lb is an external lead, 2 is a package sealing resin, 3 is a module substrate, 4 is an adhesive, 5 is a module sealing resin, 6 is a coating material, 10 11 is a semiconductor integrated circuit chip, 11 is a guide pad, and 12 is a thin metal wire. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
にモジュール用封止樹脂により再成形される半導体集積
回路モジュールにおいて、上記モジュール基板上に実装
される半導体装置の外部リード部分にゴム状態を保つコ
ーティング材を、その外部リードの曲げ加工の圧縮方向
に厚く塗布したことを特徴とする半導体集積回路モジュ
ール。In a semiconductor integrated circuit module in which a semiconductor integrated circuit device is mounted on a module substrate and then remolded with a module sealing resin, a coating material that maintains a rubber state on the external lead portion of the semiconductor device mounted on the module substrate is provided. A semiconductor integrated circuit module characterized in that a thick coating is applied in the compression direction of the bending process of the external leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20321789A JP2634249B2 (en) | 1989-08-03 | 1989-08-03 | Semiconductor integrated circuit module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20321789A JP2634249B2 (en) | 1989-08-03 | 1989-08-03 | Semiconductor integrated circuit module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0366152A true JPH0366152A (en) | 1991-03-20 |
| JP2634249B2 JP2634249B2 (en) | 1997-07-23 |
Family
ID=16470403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20321789A Expired - Lifetime JP2634249B2 (en) | 1989-08-03 | 1989-08-03 | Semiconductor integrated circuit module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2634249B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5469333A (en) * | 1993-05-05 | 1995-11-21 | International Business Machines Corporation | Electronic package assembly with protective encapsulant material on opposing sides not having conductive leads |
| FR2753044A1 (en) * | 1996-08-27 | 1998-03-06 | Siemens Automotive Sa | Encapsulated electronic circuit board assembly process |
| JP2006120152A (en) * | 2004-10-19 | 2006-05-11 | Quantum Corp | Method and device for recording state of data storage device in response to device error and computer program product including program code |
| US7339280B2 (en) * | 2002-11-04 | 2008-03-04 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with lead frame as chip carrier and method for fabricating the same |
-
1989
- 1989-08-03 JP JP20321789A patent/JP2634249B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5469333A (en) * | 1993-05-05 | 1995-11-21 | International Business Machines Corporation | Electronic package assembly with protective encapsulant material on opposing sides not having conductive leads |
| FR2753044A1 (en) * | 1996-08-27 | 1998-03-06 | Siemens Automotive Sa | Encapsulated electronic circuit board assembly process |
| US7339280B2 (en) * | 2002-11-04 | 2008-03-04 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with lead frame as chip carrier and method for fabricating the same |
| JP2006120152A (en) * | 2004-10-19 | 2006-05-11 | Quantum Corp | Method and device for recording state of data storage device in response to device error and computer program product including program code |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2634249B2 (en) | 1997-07-23 |
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