JPS6084647A - Structure memory controller - Google Patents

Abstract

PURPOSE:To speed up relocating processing by assigning the identification number of a structure to a block control table through a control part for dynamic allocating processing and garbage collection processing, and using an unused area list to secure a storage area in a main storage. CONSTITUTION:The processor part 130 consisting of a main processor 124 and a cache memory 123, the main storage 110, and memory control part 131 are provided. Further, the control part 131 is provided with a bit map memory 112 stored with pieces of information on an in-use and an unused area, an unused area list memory 121 having a list containing the starting address, etc., of unused areas, a block control table memory 122 holding the relation between the indentification number of the structure and the starting address of the storage area of the main storage 110, and a control part 120 for garbage collection processing. Then the processor part 130 accesses the main storage 110 to confirm that allocation is possible, and then the control part 120 uses the memories 122 and 121 to perform processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic memory management device that dynamically allocates arbitrary length data.

In recent years, as interest in intelligent systems has increased, prologues that can specify arbitrary length structure data have been attracting attention.

For example, in the prologue, the state in which the basket contains Shingo ``Mikan'' and ``None'' can be expressed as follows using the structure ``Cage'' and a structure with a prime number of 3.

Basket (Apples, Oranges, None) Furthermore, the fact that Aobe has this basket money can be described as follows using a structure with a structure of ゛j11゛ and a chivalry prime of 2.

The (fat, basket (shingo, orange, none)) prologue facilitates data description by using a structure with an arbitrary number of elements.

On the other hand, when the prologue is executed, many structures are dynamically created and destroyed. If a new memory area is allocated to the generated structure while leaving the disappeared Inno 4 structure in the entire memory, a large amount of memory cells will be required as the area for the structure. 7, in order to increase the usage efficiency of memory cells, a garbage collection process is performed to collect the memory cells that have become used as a result of the structure disappearing, and to make it possible to store the entire structure again. . However, the processing cost required for garbage collection processing is large, and may amount to 30 to 50% or more of the entire processing cost.

The structure implementation method and conventional garbage collection processing are described below.

One of the well-known methods for realizing a structure is to connect a plurality of regions with a length of li>'' using pointers. Hereinafter, this method will be referred to as the kgl structure realization method. As an example of the first structure realization method, a method using a binary tree list will be described.

Figure 1 shows a structure using binary tree squirrel) 10i.
A conceptual diagram is shown when expressing a basket (apples, oranges, pears). The biggest feature of this method is that the memory cell k 5h
Since the unit for storing i is a fixed length, the unused area does not need to be in a continuous area. That is, to collect used memory cells through garbage collection, it is sufficient to simply connect fixed areas (areas of two consecutive cells in a binary tree list) with pointers.

However, the first structure implementation method has the disadvantage that the overhead of tracing the pointer for accessing the elements of the structure is large. For example, in order to access the nth element of the structure, the pointer must be traced fn times, which causes a memory access bottleneck.

As another method for solving the drawbacks of the first structure realization method, a method is known in which the elements of the structure are arranged in a continuous area and each element is accessed by offset from the header section. Hereinafter, this method will be referred to as a structure realization method of kj42.

FIG. 2 is a conceptual diagram expressing a structure (thick part, basket (apple, orange, none)) according to the second structure realization method. In FIG. 2, 20 is a structure body temperature area, 21 is an element number area, 22 is a mark bit used to indicate that the structure is in use or has been used during govage collection, and 23 is a data section. represents. The three areas, the structure body temperature area 20, the number of elements area 21, and the mark pit 22, are hereinafter particularly referred to as a header area.

In the second dead body realization method, the header part of the structure and the data part 23 storing each element of the structure are allocated to one continuous head. When Shinoko uses a Kuro structure as an element, it stores a pointer to the head of the main body as an element. Furthermore, elements in the structure data section can be accessed at high speed by using offsets in the header section.

However, in the second structure realization method, structures need to be stored in continuous headers of arbitrary length, so the overhead of the garbage collection process of relocating the used area and refilling the unused area is large. There is a problem. Furthermore, due to the nature of structures, there is a possibility that one structure may be shared by a plurality of structures.

FIG. 3 (11, (2)) is a conceptual diagram showing the transition of the memory area due to garbage collection when structure A and structure C share structure B. In FIG.
Reference numeral 30 indicates a memory IJ, 31 indicates a structure area in use, and 32 indicates a used or unused area.

FIG. 3(1) shows the memory state before garbage collection, and FIG. 3(2) shows the memory state after garbage collection.

The garbage collector method in the second structure realization method will be explained. The first stop in the Garpage collection is to mark all of the 47M structures currently in use. When the main processor performs processing, it examines the stack that stores information about the structures currently in use, and
(2) This is achieved by setting the mark pit area of the structure that is directly or indirectly referenced.

The 817 structures for which mark pits were not set in the first process of garbage collection can be collected as [historical areas]. However, simply connecting used areas with pointers as in the first structure implementation method using constant areas [61] does not guarantee a continuous area in which to store a new structure. Therefore, it is impossible to combine unused areas into two continuous areas as shown in Figure 3 (1).
As shown in FIG. 3(2), the in-use structure 31 is relocated to form one continuous used area 33.
It is necessary to make

The problem with the second structure realization method is that when relocating a structure, it is necessary to rewrite all pointers pointing to the relocated structure.

A first object of the present invention is to provide high-speed access to structure elements and to reduce the overhead of relocating an area in use during garbage collection processing.

A second object of the present invention is to process the structure by the main processor and the locating process by the memory management unit.

Furthermore, a third object of the present invention is to provide a structure memory management device a that provides a fast dynamic memory management function that keeps memory usage efficiency in a good state at all times.

According to the present invention, a main memory that stores a structure consisting of a fixed-length header section and an arbitrary-length data section, a main processor that receives and processes the structure on the main memory, and a main processor that stores a structure consisting of a fixed-length header section and an arbitrary-length data section; a cache memory for storing data and providing a temporary unused area to the main processor; a pit map memory for holding information on used areas and unused areas on the main memory; and an unused area on the main memory. an unused area list that is classified into a plurality of groups based on cells that hold start address information and size information and unused area size values of the cells, and that connects cells belonging to the groups with pointers for each valley group; A block management table that stores the sub-alias of the structure that is logically one continuous area, the start address information and size information of the structure storage area on the main memory, and the dynamic allocation of the main memory. The main processor includes a control for controlling processing and garbage collection processing, and when the main processor generates a new structure, 1) allocates an area for the structure in the IJ cache memory and continues processing in the main processor. In parallel, the control unit allocates an identification number of the structure to the block management table and uses the unused area list to secure a storage area on the main memory; and during a garbage collection process. The structure memory management device is characterized in that in the location process, the control unit uses a bitmap memory to search for an area in use on the main memory and performs a relocate process.
,, First, the structure memory management method of the present invention will be explained with reference to the drawings.

FIG. 4 is an example of structure implementation in the structure memory management device of the present invention. Each word in the block management table 40 has a structure identification number 41. It holds the size 42 of the structure and the start address 43 of the continuous area on the main memory 110 that stores the structure.

FIG. 4 shows a state in which "Having a structure (Taabe, X)" and "Having a structure (Hanako, X)" share the structure "Basket (apples, oranges, pears)". The structure multi-region of the structure header section 45 related to "kato" stores the value "1" indicating that it is "kat", and the element number region of the structure stores the number of elements "3'.Data section 46 stores the elements of the structure.

Structure - have (Tabe, X)'' and ゛have (Hanako).

In order for X)'' to share the structure “basket (Shingo, Mikan, None)”, the second element 50 of the structure “Have (Tabe, X)” and “Have (Hanako, X)” The second element 51 contains information indicating that it is one element constituting the structure, as well as the identification number “1” of the structure
' is stored.

Since the structure is stored in a contiguous area on the main memory 110, the structure's elements can be accessed at high speed using the structure's identification number and element number.

In addition, in the conventional second structure realization method, it was necessary to change the elements of other structures that shared the relocated structure, so in processing where there is a large number of shared structures,
The load of relocation processing was extremely large.

However, in the structure memory management device of the present invention, the structure identification number and the main memory 110 are stored in the block management table 40.
Since the relationship between the start addresses of the storage areas above is managed, the address information of the element areas of other structures that share the relocated structure cannot be rewritten as a result of the relocation process during govage collection processing. It is no longer needed.

FIG. 5 is a diagram showing a state in which the main memory 110 in the state shown in FIG. 4 has been subjected to garbage collection processing.

The second element 50 of the structure “has (bold part, X)” and the structure “
There is no need to change the contents of the second element 51 of the structure ``(Hanako, Processing to transfer structure data consisting of four memory cells indicating It is only necessary to rewrite the first address 43 of the word corresponding to the word.

Element 5.0.51 of ``Has two structures that share ``Kat(Apple, Orange, Pear)''' needs to be updated by locating the structure ``Kat(Apple, Orange, Pear)''. There isn't. In conventional equipment, the structure “cage”
Contents of elements 50, 5 so that elements 50 and 51 of ``have'' two structures point to the structure ``Cage (Shingo, Spring Cancer, None)'' when locating the paste. needed to be updated. The problem with the conventional device is element 50.51
The load of the replacement process for updating the contents of is large, but even more so is the load of the process of searching for the elements 50 and 51 to be updated.

In the present invention, the processing necessary for rewriting elements 50 and 51 described above is unnecessary, and the load of relocate processing is reduced.

FIG. 6 is a diagram showing an example of physical wall-to-wall processing in the structure memory management device of the present invention. In Figure 6, the unused area is divided into three groups: groups with sizes of 21 or less, groups with sizes of (2'+1) or more and 22 or less, and groups with sizes of (2''+1) or more, and three unused area lists are created. ) 71.
72.73.

Each unused area list) 71, 72, 73 is a first cell check register 74, 75 which holds a pointer to the first cell.
．． At step 76, addition and deletion of the cell 61 are performed. The cell 61 has the start address 62 . of the unused area managed by the cell. A pointer 64 to the next cell of size 631 is stored.

The distribution of the used area 70 and unused area 690 of the main origin t8110 soil is processed by Dotmanop 65. By setting "0" to "0", dynamic allocation of the area on the main memory 110 is controlled.

Further, during the relocating process during the govage collection process, the relocating process can be speeded up by checking the pit mag 65 when searching for an area in use.

FIGS. 7(a) and 7(b) are diagrams showing the behavior of the unrecorded area list when dynamic area allocation processing is performed.

FIG. 7(a) shows the state with the split before, and FIG. 7(b) shows the state with the split after. Figure 7 shows the processing when the size of the newly generated 444 structure is @3''. 1 cell reference register 75 is selected and the size of the unused area is (2'+1) or more.

Access store 2, which is an unused area that manages the following unused area, and confirm that the first cell 82 can store the newly generated structure. An area 87 of size 3'' is allocated from the start address of the unused area 84 on the main memory 110 managed by the cell 82.

Then, the first cell 82 of the unused area restore 5 that was managing the unused area 84 is erased, and a pointer that refers to the 2nd cell 90 is set in the first cell reference register 75. Among the unused areas 84, an area 86 that is not used as a storage area for a newly generated structure and is left unused is managed from its size "1" to unused areas whose size is 21 or less. A cell storing management information is added as the first cell 85 of unused area restoration 4. In this way, by managing the usage status of the main memory using two unused area list pit maps, dynamic area allocation can be performed both during the process of searching for unused areas and relocating during the gobage collection process. The process of searching for a used area can be sped up.

FIG. 8 is a block diagram of an embodiment of the structure memory management device of the present invention.

The structure memory management device of the present invention includes a processor unit 130 that processes structures, a memory management unit 131 that manages physical space on main memory 110, and main memory 110.

The processor unit 130 includes a main processor 124 that processes structures, and a part of the data in the main memory 110 that is temporarily stored during garbage collection processing when the main processor 124 accesses the structure at high speed. The cache memory 123 provides an unused area.

The memory management unit 131 includes a bitmap memory 11 that holds information about used areas and unused areas on the main memory 110.
2. An unused area list/memo IJ 121 that holds a list consisting of cells that hold the address and size of the unused area, the relationship between the identification number of the structure and the start address of the storage area on the main memory 110 The main units include a block management table memory 122 that holds a block management table memory 122 and a control section 120 that controls gobage collection processing. In addition, there is a data save register 111 that saves the data relocated during the relocate process, and a physical address is generated from the start address of the continuous area on the main memory 1]0 where the structure is stored and the offset within the continuous area. 113. Unused pffl that selects the optimal unused area list from the size of the newly generated structure
It has an ffl try list selection unit as a constituent unit.

Data bus 100 connects main memory 110 . Data save register 1】1. address bus 102. It is used for data transfer between processor unit data buses 107. Internal address bus 1
01 is a bus for sending physical addresses generated by the arithmetic unit 113 to the main memory 110 and bitmap memory 112.

The address bus l02 is connected to the main memory 110 . Block/U table/memory 122° Processor unit address bus 108. Unused area selection unit) 119, compensation 'lJ-unit) 113,
This is for transmitting the structure bell number and intra-structure offset between the control units 120 via the fl+lJ lotus 106.

The offset bus 103 is connected to the processor unit 130 via the address bus 102 or the control unit 120 to the control bus 1.
This is for transmitting an offset address for successively accessing multiple elements of one continuous area on the main memory 110 or the bitmap memory 112 via the 06.

The lit address bus 104 is a used area start address storage area 11 of the block/lid table memory 122.
7 or unused space list memo! The unused area first application address storage area 114 of J121 or the start address of the continuous area sent by the control unit 120 via the control bus 106 is sent to the arithmetic unit 113.

The pointer bus 105 is an unused area list selection unit)
The unused area list memory 121 can be accessed using the contents of the register holding the first cell storage address of the unused area list on the unused area list on 119, or the control unit 120 can access the contents of the register via the control bus 106. It is something that should not be changed.

The control bus 106 connects the control unit 120 with an address bus 102, a block management table memory 1220, a used area size storage area 118. Pointer bus 105. Unused area size storage area 115 of unused area list memory 121.
Pointer heading 116. predecessor address bus 104, offset bus 103. This bus is used to access the bitmap memory 112.

Processor it (data bus 107il:, main processor 124, cache-memory 123. data bus 100
This bus is used to transfer data between the main memories 110 via the main memory 110.

Processor unit address bus 108ulE processor 12
4 is the cache memory 123 or address bus 102
This is the bus used to send the structure number and element number to be accessed.

In a normal access operation of the main memory 110, the processor section 130 accesses the block management table memory 122 via the processor section address bus 108 and the address bus 102.
Access +7# Send the identification number of the silkworm body. The block management table memory 122 latches the sent structure identification number and moves from the first address storage area 117 to the main memory 110 in which the structure with the r1♀ number is stored. The start address of the above continuous area is output to the start address bus 104. Fish J Neyuni, 1-11
．． 3 is light ↓ 1A I Address bus 104 (own address and main processor 124 sends processor A, (li address bus 108. Offset within the structure sent to offset bus 103 via address bus 102) The master address 1.φ, 110 is accessed by the processor unit 130.

Processing of the dynamic area is carried out by the processor section 30 via the processor section address bus 108. The size of the newly generated structure is sent to the unused head list selection unit 119 via the address bus 102. The unused area list selection unit 119 determines an appropriate unused area list from the received size and sends the address of the first cell to the unused area list memory 121. The control unit 120 receives the size of the newly generated structure 119 in parallel with the selection unit 119 for selecting an unused one-top stump. Next, the control section 12
0 is an unused area list selection unit from the unused area size storage area 115 of the unused area list memory 121)
The size of the unused area of the first cell of the unused area list determined by step 119 is read out and compared with the size of the newly generated structure.

When the unused area is unallocatable, the control unit 120
uses the value of the pointer/area 116 to access the unused area list memory 121 and check the next cell.

If possible, use f! ilJ both parts] 20 stores the unused structure identification number in the block management table memory 122.
In the next step, the value of the unused 1wl address address storage area 114 is transferred to the used area destination address storage area 1.
17 and the control unit 20 writes the size of the structure into the used area size storage area 118. Using the value of the unused area head address storage area 114 that has passed through the arithmetic unit 113 in the last step, the control unit 120 performs a write process into the bitmap memory 112 to update the bitmap.

During the relocate process, the control section 120 sends an address to the bitmap memory 112 via the arithmetic unit 113 to search for a used area.

When a used area is discovered, the control unit 120 sends the start address of the used area to the main memory 11θ via the arithmetic unit 113, and the structure identification number stored in the structure header section on the main memory 110 is sent to the block management table.・Memory 12
In parallel with the sending to the data save register 111, the da part of the structure is saved to the data save register 111.

In the next step, the control unit 120 sends the relocation destination address to the main memory 110, the bitmap memory 112, and the used area starting address storage area 117 via the arithmetic unit 113.
, relocate the structure header part on the main memory 110, and reorganize the bitmap memory 112.

After this, the control section 120 saves the data in the data section of the structure to the data save register 111 while sending addresses to the main memory 110 and the beat map memory 112 via the arithmetic unit 113, and in the next step, The process of writing all the data on the data save register 111 to the relocate light is repeated to complete relocating one used area.

After locating all used areas, the control unit 120
deletes all the unused area lists registered in the unused area list selection unit 119, and unused cells in the unused area list corresponding to the size of the unused areas that have been consolidated as a result of the relocate process. It is written in the used area list memory and registered in the unused area list selection unit 119.

During this relocation process, the processor unit 130 independently uses the cache memory! Process the structure using i23.

As described above, the structure memory management method of the present invention has the feature that processing can be performed at high speed when the dynamic area side When there is a large amount of data, the load on the relocate process can be reduced by eliminating the need to sequentially change the data instructions during the relocate process. It has a special feature that allows it to be separated from the system and process structures in parallel.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram when a structure with a structure (fat part, basket (apple, orange, pear)) is realized using the conventional first structure realization method, and Figure 2 is a conceptual diagram of the conventional second structure. A conceptual diagram when realizing a structured silkworm body (fatty part, basket (,!7 apple, orange, none)) using the body realization method, Figure 3 (11, (2+ is the conventional structural tree A) FIG. 4 is a conceptual diagram showing the state transition of a memory area due to garbage collection processing when structure B is shared by structure C and structure B. FIG. FIG. 5 is a conceptual diagram showing the result of relocating the main memory in the state shown in FIG. 4. FIG. 6 is a conceptual diagram showing the result of relocating the main memory in the state shown in FIG. Fig. 7 is a conceptual diagram showing the state of management. Fig. 7 (a) and (b) are conceptual diagrams showing the state of dynamic area allocation based on the unused area list. Fig. 8 is a conceptual diagram showing the state of dynamic area allocation based on the unused area list. 1 is a block diagram of an embodiment of a physical memory management device. 100 is a data bus, 101 is an internal address bus, 102 is an address bus, 103 is an offset bus, 104 is a start address bus, 105 is a pointer bus, and 106 is a control bus. , 107 is a processor section data bus. 108 is a processor section address bus. 110 is a main memory, 111 is a data save register, 112 is a bitmap memory, and 113 is an arithmetic unit).
, 114 is an unused area start address storage area. 115 is an unused area size storage area, ] 16 is a pointer area, and 117 is a used area start address storage area. 118 is a used area size storage area, 119 is an unused area list selection unit), 120 is a control unit, 121 is an unused area list memory with an address latch function,
122 is a block management table memory having an address latch function, 123 is a cache memory, and 124 is a main processor. 130 is a processor section, and 131 is a memory management section. Fig. 1 10 Fig. 2 Fig. 3 (1) (2) Fig. 4 Off Fig. 7I (a) (b) Fig. 78 130

Claims (1)

[Scope of Claims] A main memory for storing a structure consisting of a fixed-length header section and an arbitrary-length data section; a main processor for processing the structure on the main memory; and a main processor for processing the structure on the main memory; a cache memory that stores a portion of the data and provides a temporary unused area to the main processor; a pit map memory that holds information about used areas and unused areas on the main memory; A cell that holds the start address information and size information of the used area, and the above cells are classified into multiple groups based on the size value of the unused area, and for each group, the unused area is connected by all pointers of cells belonging to the group. an area list, an identification name of a structure that is logically one continuous area, a block management table that stores the start address information and size information of the structure storage area in the main memory, and Dynamic allocation includes a control unit that controls processing and garbage collection processing, and when the main processor generates a new structure, it reserves an area for the structure in the cache memory and processes it in the main processor. In parallel with continuing, the control unit 1' allocates the identification number of the structure in the block management table and uses the unused area restructuring to secure a storage area on the main memory. and a structure memory management device characterized in that, in a location process during a gobage collection process, the control unit uses a bitmap memory IJk to search for an area in use on the main memory and performs a relocate process.