KR101061483B1 - Memory circuit and memory circuit access method, memory management system and memory management method - Google Patents

Abstract

The present invention relates to a memory circuit, an access method of the memory circuit, a memory management system, and a memory management method.

The memory circuit according to the present invention includes a shared memory interface coupled between a DRAM, a nonvolatile memory, a DRAM and a nonvolatile memory, and a processor, the processor configured to access the DRAM and the nonvolatile memory in the same manner.

According to the memory circuit according to the present invention, the DRAM and the nonvolatile memory are connected to the same memory interface and mapped to the main memory physical address of the processor so that the processor can directly access the DRAM and the nonvolatile memory.

Hybrid Memory, Nonvolatile Memory, DRAM, Main Memory Management

Description

MEMORY CIRCUIT AND METHOD FOR ACCESSING MEMORY CIRCUIT, SYSTEM AND METHOD FOR MANAGING MEMORY}

The present invention relates to a memory circuit, an access method of the memory circuit, a memory management system, and a memory management method.

Nonvolatile memories, such as phase change memory (PCM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), have non-volatile characteristics, and like DRAM, Because it is accessible at the byte or word level, it can be used alone as a main memory like a DRAM. In addition, depending on the characteristics of each nonvolatile memory has advantages such as cost versus capacity or low power operation compared to DRAM. However, since the non-volatile memory has a disadvantage in that the access speed is lower than that of the DRAM, when using the non-volatile memory alone as the main memory, the performance is lower than when using the DRAM as the main memory.

As a related art, Korean Patent Laid-Open Publication No. 10-2007-0080844 (a method and system for accessing a nonvolatile memory controller and a volatile memory, a nonvolatile memory controller and a volatile memory), and Korean Patent Publication No. 10-2005- 0042183 (memory circuit including a RAM and a nonvolatile RAM), Korean Patent Laid-Open No. 10-2008-7029847 (method and system for a hybrid memory device), etc., a hybrid method of volatile memory (RAM) and nonvolatile memory Documents on how to configure. That is, the present invention relates to a method of connecting a nonvolatile memory through a volatile memory interface.

On the other hand, a nonvolatile memory such as a conventional flash requires erasing operations in units of blocks, and thus data cannot be accessed in units of bytes. Therefore, a method of converting a nonvolatile memory interface into an existing memory interface through an SRAM buffer and a nonvolatile memory management module is proposed. However, in the case of a memory directly accessible to a processor such as a nonvolatile memory, use of a conventional interface conversion method is unnecessary.

In addition, as the prior art, US Patent Publication US5269013 (Adaptive memory management method for coupled memory multiprocessor systems), US Patent Publication US5918249 (Promoting local memory accessing and data migration in non-uniform memory access system architectures), etc. Is a technique for managing memory in the presence of memory. That is, the present invention relates to a method of managing memory according to a location of memory accessed by a plurality of processors. However, a method of tracking the memory access method of each memory with respect to memory having different physical characteristics such as DRAM and nonvolatile memory and a memory page management method through the memory are not proposed.

Accordingly, in order to solve the above problem, the present invention connects the DRAM and the nonvolatile memory to the same memory interface and maps the main memory physical address of the processor so that the processor can directly access the DRAM and the nonvolatile memory. It is an object of the present invention to provide a memory circuit, an access method of the memory circuit, a memory management system, and a memory management method.

In addition, the present invention provides an access method of a memory circuit and a memory circuit, a memory management system, and a memory capable of optimizing memory access performance by allocating, retrieving, and exchanging memory pages in accordance with characteristics of DRAM and nonvolatile memory on the memory circuit. Its purpose is to provide a management method.

In addition, an object of the present invention is to provide a memory circuit memory circuit, an access method of a memory circuit, a memory management system, and a memory management method capable of implementing a large-capacity main memory of a computer system by optimizing memory access performance. do.

In addition, the present invention can be configured a large-capacity memory using a DRAM and a non-volatile memory at the same time through a hybrid memory structure consisting of a DRAM and a non-volatile memory to prevent performance degradation of the entire computer system in the absence of main memory It is an object of the present invention to provide a circuit memory circuit, an access method of a memory circuit, a memory management system, and a memory management method.

In addition, the present invention provides a main memory construction cost while guaranteeing similar performance as compared to a system consisting of DRAMs of the same capacity by enabling accessing frequently accessed pages through a fast DRAM through a DRAM hybrid memory management method. And a memory circuit memory circuit and an access method, a memory management system, and a memory management method which can benefit from main memory power consumption.

The memory circuit of the invention according to claim 1 comprises a shared memory interface coupled between a DRAM, a nonvolatile memory, a DRAM and a nonvolatile memory, and a processor, the processor configured to access the DRAM and the nonvolatile memory in the same manner, the processor comprising: DRAM and nonvolatile memory can be mapped to different physical memory addresses to control access to DRAM and nonvolatile memory.

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A method of accessing a memory circuit of the present invention according to claim 3, comprising: connecting the DRAM and the nonvolatile memory to the processor through the same shared memory interface, and the processor mapping the DRAM and the nonvolatile memory to different physical memory addresses, respectively, shared by the processor. Selecting a physical memory address through the memory interface to regulate access to the DRAM or non-volatile memory.

The memory management system according to claim 4 is a memory management system in which a user process including a plurality of processes is controlled through an operation control unit so that a user process including a plurality of processes is accessed to a main memory including a DRAM and a nonvolatile memory. Allocating and retrieving memory pages according to the virtual memory unit corresponding to each of the processes, the page table mapping the virtual memory address to the physical page of the main memory, DRAM and nonvolatile memory when a plurality of processes access the virtual memory unit. It includes a hybrid memory management module that moves, and changes the page table to control the user process to determine either DRAM or non-volatile memory.

The memory management system of the present invention of claim 5 is the memory management system of the invention of claim 4, wherein the hybrid memory management module collects access information for DRAM and nonvolatile memory, and retrieves and exchanges memory pages to main memory. Control to collect memory access information periodically when memory access information is not collected for a predetermined time in a forced page fault handler, DRAM, and nonvolatile memory, which changes and maintains page information table information according to the location of memory pages. And a memory page allocation module that controls when a forced page fault generator, a new DRAM, and a nonvolatile memory are to be used, a free page that is not currently being used is allocated.

The memory management system of the present invention according to claim 6, the memory management system of the invention according to claim 5, the forced page fault handler is to access from the previous page fault to the present time when a page fault occurs due to improper access to DRAM and nonvolatile memory Memory access information collection module for collecting memory page information, hybrid memory page retrieval module for reclaiming unused memory pages of DRAM and nonvolatile memory in the event that there are not enough free pages remaining in DRAM and nonvolatile memory. Among the pages of the volatile memory, a page having a large difference in page access frequency includes a hybrid memory page exchange module for exchanging memory pages.

The memory management method according to claim 7 is a memory management method which is controlled through an operation control unit such that a user process including a plurality of processes is accessed to a main memory including a DRAM and a nonvolatile memory, the method comprising: (a) a DRAM from a user process And if there is a nonvolatile memory page access, first checking whether a memory page to be accessed is currently allocated; (b) checking a cycle for collecting memory page access information when the memory page is already allocated, and forcibly generating a page fault by generating a forced page fault when it is necessary to collect the memory page access information, (c ) Collect access information for DRAM and nonvolatile memory pages, and based on the collected information, if the number of pages not used for DRAM or nonvolatile memory is high or the number of free pages remaining is small, Performing (d) if recovered DRAM exists, moving pages on non-volatile memory that are currently frequently accessed using DRAM to the DRAM; and (e) swapping when memory pages are moved or swapped between memory pages. Memory page exchange cycle by feeding back the number of memory pages (F) if the allocation, retrieval, and exchange of memory pages occurs, the page mapping information of the page table is updated, and the page access information is updated for each page access, so that future pages can be retrieved and exchanged. Collecting access information.

In the memory management method of the invention according to claim 8, the memory management method of the invention according to claim 7, In step (b), page faults are naturally generated for memory accesses that are not currently allocated, and the DRAM and nonvolatile memory are selectively selected. It further comprises the step of assigning.

In the memory management method of the inventor of claim 9, the memory management method of the invention of claim 7, wherein in step (c), when the number of memories is not necessary, the access number of the DRAM and the nonvolatile memory is compared and the access number is different. If large, that is, pages in nonvolatile memory are accessed more frequently than memory pages in DRAM, memory pages are swapped between DRAM and nonvolatile memory.

As described above, according to the present invention, the DRAM and the nonvolatile memory are connected to the same memory interface and mapped to the main memory physical address of the processor so that the processor can directly access the DRAM and the nonvolatile memory.

In addition, according to the present invention, memory access performance may be optimized by allocating, retrieving, and exchanging memory pages in accordance with characteristics of DRAM and nonvolatile memory on a memory circuit.

In addition, according to the present invention, since the memory access performance is optimized, a large main memory of a computer system can be implemented.

In addition, according to the present invention, a large-capacity memory using both DRAM and non-volatile memory can be configured through a hybrid memory structure composed of DRAM and non-volatile memory, thereby preventing performance degradation of the entire computer system from running out of main memory. Can be.

In addition, according to the present invention, since a frequently accessed page can be accessed through a fast DRAM through the DRAM hybrid memory management method, the main memory construction cost can be guaranteed while comparable performance with that of a system having only DRAM of the same capacity. And main memory power consumption.

Specific matters other than the problem to be solved, the problem solving means, and the effects of the present invention as described above are included in the following embodiments and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the accompanying drawings are only described in order to more easily disclose the contents of the present invention, but the scope of the present invention is not limited to the scope of the accompanying drawings that will be readily available to those of ordinary skill in the art. You will know.

1 is a block diagram illustrating a configuration of a hybrid memory circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a hybrid memory circuit according to an embodiment of the present invention includes a processor 101, a shared memory interface 102 (ADR / DATA), a DRAM 103, and a nonvolatile memory 104. do.

The processor 101 is connected to the DRAM 103 and the nonvolatile memory 104 through the shared memory interface 102. Accordingly, since there is no difference between the approach of the DRAM 103 and the approach of the nonvolatile memory 104, the processor 101 may have the same effect as using a single memory. For example, by mapping the DRAM 103 and the nonvolatile memory 104 to different physical memory addresses 105, the processor 101 accesses the DRAM 103 when accessing the physical address from 0x000000000 to 0x03FFFFFFF. When accessing the physical address 105 from 0x03FFFFFFF to 0x1FFFFFFFF, the nonvolatile memory 104 is accessed. Thus, by adjusting the mapping of the physical address 105 accessed by the processor 101 in the present invention, the page accessed by the processor 101 can be changed to the DRAM 103 or the nonvolatile memory 104.

2 is a diagram illustrating a structure of a memory management system according to another exemplary embodiment of the present invention.

As shown in FIG. 2, a memory management system according to another exemplary embodiment of the present invention includes a user process 201, an operation controller 202, and a main memory 204. Here, the memory management system according to another embodiment of the present invention basically uses a virtual memory management method used in a general memory management system.

When the user process 201 has its own virtual memory unit 208 and each process (process 1, process 2, process 3 ...) approaches the virtual memory unit 208, the operation control unit ( 202 maps the virtual memory address to the physical page of the actual hybrid main memory 204 through the internal page table 207. At this time, it is determined whether the operation controller 202 approaches the DRAM 205 or the nonvolatile memory 206 according to which physical memory address the virtual memory address is mapped to via the internal page table 207. In addition, the hybrid memory management module 203 of the operation control unit 202 allocates, retrieves, and moves memory pages according to the features of the DRAM 205 and the nonvolatile memory 206. In this way, by changing the page table 207, the user process 201 can determine which of the DRAM 205 and the nonvolatile memory 206 to use. In this case, the user process 201 may know only information about the virtual memory unit 202 to which the user process 201 accesses. In addition, the determination of which of the DRAM 205 or the nonvolatile memory 206 to use on the hybrid main memory 204 is entirely determined by the hybrid memory management module of the operation controller 202 regardless of the user process 201. 203).

3 is a diagram illustrating a structure of a hybrid memory management module according to another embodiment of the present invention.

As shown in FIG. 3, the hybrid memory management module 304 of the hybrid memory management system according to another exemplary embodiment allocates, retrieves, and exchanges memory pages of the main memory 308 within the operation controller. do. It also serves to change and maintain page table 301 information according to memory page locations.

The hybrid memory management module 304 collects access information for each memory in order to manage memory pages of the DRAM 307 and the nonvolatile memory 308. However, collecting and managing access information for every memory access involves a lot of overhead. Accordingly, the hybrid memory management module 304 may access the memory page information accessed from the previous page fault to the present through the memory access information collection module 312 only when a page fault occurs due to a bad page access. Will be collected and managed. However, in the case of normal memory access, a page fault does not occur, which causes a problem that memory access information cannot be collected for too long. To prevent this, the page fault handler 302 is periodically called through the forced page fault generator 303 and the memory access information collecting module 312 is operated to collect memory access information.

When a new memory is required to be used in the operation control unit or the user process, a free page which is not currently being used by the memory page allocation module 309 in the hybrid memory management module 304 is allocated to the operation control unit or the user process. do. At this time, based on the collected memory access information 312 and the free page number information on the DRAM 307 and the nonvolatile memory 308, it has been used for a long time to be selectively allocated from the DRAM 307 and the nonvolatile memory 308. When the number of memory pages is large and the number of free pages remaining in each memory is large, more memory is allocated in proportion thereto. After the memory is allocated, the page table 301 information is modified to access the allocated physical memory address through the virtual memory address.

When the page fault handler 302 processes the page fault, if the free page remaining in the DRAM 307 or the nonvolatile memory 308 is insufficient, the page recall module 311 does not use the main memory 306. Memory pages are retrieved. After memory page reclamation, the recovered DRAM 307 or nonvolatile memory 308 page remains as a free page. At this time, by moving the memory that was frequently accessed on the existing nonvolatile memory 308 directly to the newly created free page of the DRAM 307, the frequently accessed page can be accessed using the fast access time DRAM 307. Make sure After page retrieval, as with page allocation, the page table 301 is modified to display free pages, or the physical address of the virtual memory address is stored for pages moved from nonvolatile memory 308 to DRAM 307. Change the memory address mapping.

Also, if pages frequently accessed in hybrid main memory 306 are present in non-volatile memory 308 with slow access, and conversely, pages that are not frequently accessed are in DRAM 307, average main memory 306 Approach speed will slow down. Therefore, in the process of processing the page fault in the page fault handler 302, in the case of pages with a large difference in page access frequency among the memory pages of the DRAM 307 and the nonvolatile memory 308, the memory page swap module ( The memory page is exchanged through 310. As a result, the frequently accessed pages are accessed in the DRAM 307, resulting in an increase in the average performance of the main memory 307. However, page exchanges between DRAM 307 and non-volatile memory 308 require page-by-page data copies, so if page exchanges occur too often, they are averaged due to page exchange overhead. Memory access performance may be degraded.

Therefore, in the present invention, the memory page exchange period is adjusted by receiving feedback of the number of memory pages exchanged in the past, so that page exchange is frequently performed when many page exchanges are necessary. In the opposite case, the number of page exchanges is reduced, so that only optimal page exchanges are performed when necessary. After the page exchange, the exchanged pages are also exchanged with mapping information on the page table 301 so that the exchanged page can be accessed even if the user process needs to access a memory page later.

4 is a flowchart illustrating a procedure of a memory management method according to another embodiment of the present invention.

As shown in FIG. 4, the hybrid memory management module according to another embodiment of the present invention first checks whether a physical memory to be accessed is currently allocated when there is a memory page access (401).

At this time, a page fault naturally occurs for the memory access that is not currently allocated (405), and selectively allocated between DRAM and nonvolatile memory by the memory page allocation module (406).

In addition, if the access page has already been allocated, the period for collecting page access information is checked (402). In this case, when collection of page access information is required, a forced page fault is generated (403), and a page fault is forcibly generated (404). Then, access information for DRAM and nonvolatile memory pages is collected (407). On the basis of the collected information, if the number of pages not used in the DRAM or nonvolatile memory is large or the number of free pages remaining is small (410), memory page retrieval is performed (409). Then, if there is a recovered DRAM memory (408), it moves the page on the currently frequently accessed non-volatile memory to the DRAM (411).

On the other hand, when memory reclamation is not needed, if the access numbers of the DRAM and the nonvolatile memory are compared and the difference in access numbers is large (413), that is, the pages in the nonvolatile memory are accessed more frequently than the memory pages in the DRAM. In operation 412, memory pages between the DRAM and the nonvolatile memory are exchanged.

When the memory page is shifted or exchanged between the memory pages, the memory page exchange cycle is adjusted by feeding back the number of memory pages exchanged and moved (step 415). In addition, when memory page allocation, retrieval, and exchange have occurred, the page mapping information of the page table is updated (414), and the page access information is updated (416) every time all pages are accessed. Then, later page access information is collected to enable page retrieval and exchange.

According to the memory circuit and the method of accessing the memory circuit, the memory management system and the memory management method according to the present invention as described above, the DRAM and the nonvolatile memory is connected to the same memory interface, the processor is mapped to the main memory physical address of the processor Directly access DRAM and nonvolatile memory. In addition, according to the present invention, memory pages can be allocated, retrieved, and exchanged on memory circuits to match the characteristics of DRAM and nonvolatile memory, thereby optimizing memory access performance, and optimizing memory access performance. Large main memory can be implemented.

In addition, according to the present invention, it is possible to configure a large-capacity memory using both DRAM and non-volatile memory through a hybrid memory structure consisting of DRAM and non-volatile memory to prevent performance degradation of the entire computer system in the absence of main memory. In addition, the DRAM hybrid memory management method allows frequently accessed pages to be accessed through fast DRAMs, which guarantees comparable performance compared to a system with only DRAM of the same capacity, while maintaining main memory construction cost and main memory power consumption. You can benefit from

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and their All changes or modifications derived from equivalent concepts should be construed as being included in the scope of the present invention.

1 is a block diagram showing a configuration of a hybrid memory circuit according to an embodiment of the present invention.

2 is a diagram illustrating a structure of a memory management system according to another embodiment of the present invention.

3 is a diagram illustrating a structure of a hybrid memory management module according to another embodiment of the present invention.

4 is a flowchart illustrating a procedure of a memory management method according to another embodiment of the present invention.

Claims (9)

DRAM; Nonvolatile memory; And A shared memory interface coupled between the DRAM and the nonvolatile memory and a processor, the processor configured to access the DRAM and the nonvolatile memory in the same manner; Including, The processor may control access to the DRAM and the nonvolatile memory by mapping the DRAM and the nonvolatile memory to different physical memory addresses, respectively. Memory circuits. delete Coupling a DRAM and a nonvolatile memory with a processor through the same shared memory interface, wherein the processor maps the DRAM and the nonvolatile memory to different physical memory addresses; And The processor selecting the physical memory address through the shared memory interface to regulate access to the DRAM or nonvolatile memory; Comprising a; a method of accessing a memory circuit. A memory management system in which a user process including a plurality of processes is controlled through an operation control unit to access a main memory including a DRAM and a nonvolatile memory. The operation control unit, A virtual memory unit corresponding to each of the plurality of processes; A page table for mapping a virtual memory address to a physical page of the main memory when the plurality of processes access the virtual memory unit; And A hybrid memory management module for allocating, retrieving, and moving memory pages according to the DRAM and the nonvolatile memory, and changing the page table to control the user process to determine one of the DRAM and the nonvolatile memory. ; / RTI > Memory management system. 5. The method of claim 4, The hybrid memory management module, A forced page fault handler that collects access information about the DRAM and the nonvolatile memory, retrieves and exchanges memory pages to the main memory, and changes and maintains the page information table information according to the location of the memory pages. ; A forced page fault generator which controls to periodically collect memory access information when the memory access information is not collected in the DRAM and the nonvolatile memory for a predetermined time; And A memory page allocation module that controls when a new DRAM and the nonvolatile memory are to be used, a free page that is not currently being used is allocated; Including, a memory management system. The method of claim 5, The forced page fault handler is A memory access information collection module for collecting memory page information accessed from a previous page fault to the present when a page fault occurs due to an erroneous access to the DRAM and the nonvolatile memory; A hybrid memory page retrieval module for reclaiming unused memory pages of the DRAM and the nonvolatile memory when the free pages remaining in the DRAM and the nonvolatile memory are insufficient; And A hybrid memory page exchange module for exchanging memory pages in a case of pages having a large difference in page access frequency among pages of the DRAM and the nonvolatile memory; Including, a memory management system. A memory management method in which a user process including a plurality of processes is controlled through an operation controller to access a main memory including a DRAM and a nonvolatile memory. (a) if there is access to the DRAM and the nonvolatile memory page from the user process, first checking whether a memory page to be accessed is currently allocated; (b) checking the period for collecting the memory page access information when the memory page is already allocated, and forcibly generating a page fault by generating a forced page fault when the memory page access information collection is necessary; ; (c) collecting access information about the DRAM and the nonvolatile memory page, and based on the collected information, the number of unused pages or the number of free pages remaining in the DRAM or the nonvolatile memory is small. Performing memory page retrieval; (d) if the recovered DRAM is present, moving pages on nonvolatile memory that are currently frequently accessed using the DRAM to the DRAM; (e) adjusting a memory page exchange cycle by feeding back the number of memory pages exchanged and moved when the memory page is moved or the memory page is exchanged; And (f) when the allocation, retrieval, and exchange of memory pages have occurred, updating page mapping information of a page table, and collecting page access information at a later time to enable page retrieval and exchange by updating page access information for each page access. ; Including, the memory management method. The method of claim 7, wherein In the step (b), a page fault is naturally generated for a memory access that is not currently allocated, and further includes selectively allocating one of the DRAM and the nonvolatile memory. Memory management method. The method of claim 7, wherein In step (c), When the number of times of memory is not necessary, the number of accesses of the DRAM and the nonvolatile memory are compared, and if a difference in the number of accesses is large, the memory pages between the DRAM and the nonvolatile memory are exchanged. Memory management method.

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