JPS6080387A - Digitizing circuit of color video signal - Google Patents

Abstract

PURPOSE:To obtain a digitized circuit with high stability and ease of circuit integration by digitizing a color video signal with a sampling clock in synchronizing with a color subcarrier in the color video signal. CONSTITUTION:An NTSC composite color television signal fed from an input terminal 90 is converted into an 8-bit digital data at an A/D converting circuit 31 by using a sampling clock of a frequency 4fsc from a clock generating circuit 33. The converted output is fed to a Y/C separation circuit 91, where the signal is separated into a luminance signal data and a chrominance signal data including a burst. Then the chrominance signal data is fed to a burst gate circuit 96 via a gate circuit 92, a polarity inverting circuit 93, and only a data of a burst signal period is fed to a digital integration circuit 98. The output of the integration circuit is subject to D/A conversion and fed to the clock generator 33 as a control voltage and a sampling clock in synchronizing with the subcarrier is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to circuits for digitizing color video signals.

"Background Art and its Problems" When a composite color video signal based on the NTSC system is digitized using a sampling clock with a frequency of 4 fsc (fsc: color subcarrier), for example,
This sampling clock is synchronized with the color subcarrier in the input color video signal. However, when a phase variation occurs in the input color subcarrier, there is a problem in that when a fixed phase sampling clock is used, the synchronization with the color subcarrier is lost. In order to solve this problem, conventionally,
An APC (automatic phase control) circuit configured as an analog circuit has been used, but it has disadvantages in that it has poor temperature characteristics, changes over time, and is difficult to integrate and miniaturize the circuit.

``Object of the Invention'' The present invention is a color video signal digitization circuit that digitizes a color video signal using a sampling clock synchronized with color subcarriers in an input color video signal, which is highly stable and can be integrated into an integrated circuit. The purpose of this invention is to provide an easy digitization circuit.

"Summary of the Invention" The present invention provides an A/D converter to which a color video signal including a burst signal is supplied, a clock generation circuit that generates a sampling clock for the A/D converter,
comprising a circuit that detects a phase difference between a burst signal in a digital color video signal output from an A/D converter and a sampling clock from a clock generation circuit,
This is a color video signal digitization circuit that controls a clock generation circuit to cancel out this phase difference.

Embodiment FIG. 1 shows the overall configuration of a color video signal recording and reproducing apparatus to which the present invention can be applied. This color video signal recording and reproducing apparatus uses a fixed magnetic head 1 to print one frame (one frame) on a magnetic sheet (not shown).
This system records color still image signals (of good quality in the field) as one or two circular racks. One magnetic sheet is rotatably housed within a hard shell and can form several dozen circular tracks.

The magnetic sheet cassette is small and can be used as a recording medium for still image video cameras.

FIG. 1 shows the configuration of signal processing when recording and reproducing color video signals. This signal processing will be summarized below.

This embodiment can record both, for example, an NTSC composite color video signal and a component color video signal consisting of three primary color signals. The main playback output is a composite color video signal, with component color video signals being output for monitor use. The signal recorded on the magnetic sheet consists of a vFM modulated luminance signal YFM and an FM modulated line sequential color signal. Figure 2 shows the frequency spectrum of the recording signal, and the signal Y
The FM center frequency fY is set to a predetermined frequency within the range of 6 to 7.5 tvlHz, the FM modulation center frequency fR of the red color difference signal R-Y is set to, for example, 1.2 MHz, and the FM modulation center frequency fR of the red color difference signal R-Y is set to, for example, 1.2 MHz. For example, if the FM modulation center frequency fB is 1 or 3
'Ml-1z. These two color difference signals are IH (
The lines are sequentially arranged so that they appear alternately in f77 (one horizontal period). By line sequentialization, the recording signal band can be narrowed. The reason why the center frequencies of the two color difference signals have an offset from each other is to identify a line-sequential color sequence.

In addition, most of the signal processing is performed digitally, thereby stabilizing the operation and facilitating the implementation of an integrated circuit configuration. Furthermore, the A/D converter provided on the input side of the signal processing section and the D/A converter provided on the output side thereof are as follows.
It is commonly used in both recording circuits and reproduction circuits.

A (7) D/A converter is further provided to form a component color video signal for monitoring.

The configuration of signal processing for recording and reproduction will be described in further detail with reference to FIG. In Figure 1, 2 is an input terminal to which an NTSC color video signal is supplied, 3, 4 and 5 are input terminals from a color video camera, microcomputer, etc.
An input terminal 6 is supplied with the primary color signals R, G, and B, respectively, and an input terminal 6 is supplied with a composite synchronization signal 5YNC corresponding to a component color video signal composed of the three primary color signals.

The three primary color signals are supplied to the matrix circuit 7 and converted into a luminance signal Y, a red color difference signal RY, and a blue color difference signal B-Y. The two color difference signals output from the matrix circuit 7 are supplied to the input terminal of the switching circuit 80, and are taken out to the output terminal thereof alternately for each IH by a switching pulse from the terminal 9. This switching time M8U
, generates a line sequential color signal LSC. In FIG. 1, the luminance signal is represented as Y, and the red color difference signal and the blue color difference signal are represented as Y, without distinguishing between analog signals and digital signals, and similarly without distinguishing between recording signals and playback signals. The composite color video signal is represented as NTSC, the line sequential color signal is represented as LSC, and each component of the three primary color signals is represented as R, G, B. has been done.

11, 12. 13,14. '15. 16. 1
7 is a recording/reproduction changeover switch, respectively. These recording/reproduction changeover switches 11 to 17 each have a recording side terminal (indicated by a black circle) and a reproduction side terminal (indicated by a white circle).

In FIG. 1, these recording/playback selector switches 11 to 17
indicates the connection status at the time of recording. 18 is a switch that can be switched depending on the difference between composite input and composite I input.

The composite color video signal from input terminal 2 is output to switch 18.
The luminance signal from the matrix circuit 7 is supplied to the input terminal 20 of the switch 18, and one signal selected by the switch 18 is sent to the A/D converter 31 via the recording/reproduction changeover switch 11. Supplied. The line sequential color signal LSC from the switching circuit 8 is sent to the A/D converter 32 via the recording/reproduction changeover switch 12.
supplied to

The A'/D converter 31 includes a clock generation circuit 3.
A sampling clock of 3 to 4 fsc (fsc: color subcarrier frequency) is supplied. A sampling clock from a clock generation circuit 33 is supplied to the A/D converter 32 via a 1/2 frequency divider circuit 34. At the output of each of these A/D converters 31 and 32, digital data of 8 bits per sample is obtained. By applying the present invention, the clock generation circuit 33 generates a sampling clock whose frequency and phase are synchronized with the input signal, and this sampling clock is supplied to the digital decoder 35 and is control data is supplied to the clock generation circuit 33.

The output data of the A/D converter 31 is sent to the digital decoder 35 through the recording side terminal of the recording/reproduction changeover switch 13.
supplied to The digital decoder 35 separates the composite color video signal into a luminance signal and a carrier color signal;
A process of generating a control signal for the clock generation circuit 33 from a burst signal included in a carrier color signal, a process of digitally demodulating the carrier color signal, and converting two color difference signals that are demodulated outputs into a line sequential color signal LSC. and the processing to be performed.

The luminance signal from the digital decoder 35 is supplied to a digital pre-emphasis circuit 41.

The line sequential color signal LSC from the digital decoder 35 has a sumbling rate of 2 fsc, and this line sequential color signal r, sc is applied to one input terminal 37 of the switch
supplied to Manually peeling off the other side of the switch 36 1 crystal 38
A line sequential color signal LSC is supplied from the A/D converter 32 via the recording/reproduction changeover switch 14 . The line sequential color signal passed through this switch circuit 36 is supplied to an adder circuit 39.

ID data is supplied to the adder circuit 39 from a terminal 40 . This ID data has different values between the line of the red color difference signal RY and the line of the blue color difference signal B-Y. By this ID data, the frequencies when FM modulation is not performed are made different between the two color difference signals. The output of the adder circuit 39 is sent to the digital pre-emphasis circuit 42.
supplied to The respective outputs of the pre-emphasis circuits 41 and 42 are supplied to digital FM modulators 43 and 44, and the modulated outputs of both are mixed by a mixer 45. The signal is supplied to the D/A converter 46 through the D/A converter 46. An analog recording signal having a frequency spectrum shown in FIG. 2 is taken out from this D/A converter 46. This recording signal is supplied to the magnetic head 1 via the recording side terminal of the recording/reproduction changeover switch 16, the recording amplifier 47, and the recording side terminal of the recording/reproduction changeover switch 17. A recording signal is recorded on the magnetic sheet I by this magnetic head 1.

A signal reproduced from the magnetic sort by the magnetic head 1 is supplied to a no-pass filter 52 and a low-pass filter 53 via a reproduction amplifier 51.

An FM-modulated luminance signal is taken out from the high-pass filter 52, and an FM-modulated line-sequential color signal is taken out from the low-pass filter 53. Bypass filter 52
and the output of the low-pass filter 53 is analog FM.
The demodulated outputs are supplied to demodulation circuits 54 and 55, and the respective demodulated outputs are supplied to de-emphasis circuits 56 and 57.

One luminance signal Y754 taken out from the de-emphasis circuit 56 is supplied to the A/D converter 31 through the playback side terminal of the self-recording/playback switch 11, and is converted into a digital signal by the A/D converter 31. Line sequential color signal LS taken out from the emphasis circuit 57
C is connected to A through the playback side terminal of the recording/playback selector switch 12.
The signal is supplied to the A/D converter 32, and converted into a digital signal by the A/D converter 32. A digital luminance signal from the A/D converter 31 is supplied to the delay circuit 61 through the reproduction side terminal of the recording/reproduction changeover switch 13. The digital line sequential color signal from the A/D converter 32 is supplied to the synchronization circuit 62 through the reproduction side terminal of the recording/reproduction changeover switch 14 .

The synchronization circuit 62 converts the two line-sequential color difference signals into two I
Supplied to the series connection of the H delay circuit, the input and output of the series connection of this IH delay circuit are added, and this added output is halved.
The output terminal is connected to the first and third output terminals, and the second and fourth output terminals are output from the connection point of the IH delay circuit.

The average value of the color difference signals of one of the first and third lines of the three consecutive lines is extracted from the first and third output terminals of the synchronization circuit 62, and the average value of the color difference signal of the other of the second line is extracted. Color difference signals are taken out to second and fourth output terminals. Therefore, the synchronized red color difference signal RY can be separated by a switch circuit that selects one of the first and second output terminals, and a switch circuit that selects one of the third and fourth output terminals. Accordingly, the synchronized blue color difference signal B-Y can be separated.

An ID detection circuit 63 is provided to ensure that the switch circuit of the synchronization circuit 62 operates correctly. I
The D detection circuit 63 detects II) data added at the time of recording, and determines the correct phase of the pulse that controls the switch circuit based on the detection. Two color difference signals taken out from the synchronization circuit 62 are supplied to interpolation circuits 64 and 65. These interpolation circuits 64 and 65 interpolate, for example, the average value of two data before and after this data, and the interpolation circuits 64 and 65 output color difference signals RY and RY whose sampling rate has been converted to 4 fsc. B-Y is obtained. This sampling rate conversion is necessary to achieve the same sampling rate as the digital luminance signal.

Digital color difference signals taken out from each of interpolation circuits 64 and 65 are supplied to a hue correction circuit 66. The hue correction circuit 66 adjusts the phase, that is, the hue, of the color signal when the two color difference signals are combined by changing the values of the two color difference signals.

The color difference signal taken out from the hue correction circuit 66 and the luminance signal from the delay circuit 61 are supplied to a digital camera (IJ) circuit 67. The delay circuit 61 has the same amount of delay as the delay of the color difference signal that occurs between the synchronization circuit 62 and the input 1 of the matrix circuit 67.

The digital three primary color signals taken out from the matrix circuit 67 are supplied to a color temperature correction circuit 68.

Correction data is supplied to the hue correction circuit 66 and color temperature correction circuit 68 from a control section 69 consisting of a microprocessor and memory. The data for correction is sent to terminal 70.
specified by control signals from. This control signal is generated by the operator operating keys and levers while monitoring the hue and color temperature of the monitor image.

The digital three primary color signals taken out from the color temperature correction circuit 68 are supplied to a digital matrix circuit 71 and D/A converters 72, 73, and 74. These D/A converters 72. 73. 74 respective output terminals 75,
At 76 and 77, analog component color video signals R, G, and B are taken out. Although not shown, this component color video signal is supplied to an input terminal of a color monitor receiver.

The digital matrix circuit 71 outputs a gain-tal luminance signal and two digital color difference signals that have been corrected for hue and color temperature. The output of this matrix circuit 71 is supplied to a color encoder 78. In connection with color encoder 78, synchronization signal 5YNC
and a synchronization and burst flag generation circuit 79 that generates a burst flag pulse BFP. The output of this color encoder 78 is a digital NT.
The SC composite color video signal is taken out, and this composite color video signal is supplied to the D/A converter 46 through the reproduction side terminal of the recording/reproduction changeover switch 15 . A playback signal in the form of an analog composite color video signal is output from the output of the D/A converter 46 to the output terminal 80 through the playback side terminal of the recording/playback switch.

The present invention provides A of the above-mentioned color video signal recording/reproducing circuit.
This is applied to digitization in the /D converter 31 or the idA/D converter 32. That is, the clock generation circuit 33 is controlled by the control signal from the digital decoder 35, and the clock generation circuit 33 is controlled by the control signal from the digital decoder 35, and
It is assumed that the sampling clock for the D converter 32 is synchronized with the burst signal in the input G-video signal.

A circuit for generating this control signal is provided within the digital decoder 35.

Further, an embodiment of the present invention will be described with reference to FIG.

Analog NT from the input terminal shown at 90 in Figure 3
The SC composite color video signal is supplied to A/D converter 31. The A/D converter 31 is supplied with a sampling clock having a frequency of 4 fsc from the clock generation circuit 33, and the A/D converter 31 converts one sample into 8-bit digital data. As the clock generation circuit 33, for example, a VCO (voltage controlled oscillator) is used.

The output of the A/D converter 31 is supplied to a Y/C separation circuit 91 composed of a comb filter and a bandpass filter, and is separated into luminance signal data in the color video signal and carrier color signal data including burst signals. Ru. The separated luminance signal data is supplied to the pre-emphasis circuit 41, and the carrier chrominance signal data including the divided #1 burst signal is extracted for digital demodulation and is supplied to the gate circuit 92. Gate circuit. For example, when the l sample is 8-bit data, the gate circuit 92 uses eight AND gates, each bit of data is supplied to one input terminal of each AND gate, and the other input terminal of each AND gate is supplied to one input terminal of each AND gate. They are commonly connected and a clock is supplied to this common connection point, and the gate circuit 92 allows the output data to be taken out as is only during the period in which the clock from the /2 frequency divider circuit 94 is at a high level.

The output taken out from the gate circuit 92 is sent to the polarity inversion circuit 9.
3. The polarity inversion circuit 93 is supplied with a clock having a frequency fsc from the clock generation circuit 33 via a /2 frequency divider circuit 94.95.

In the polarity inversion circuit 93, for example, when one sample is 8-bit data, eight exclusive ○R gates are used, and each bit of data is supplied to one input terminal of each exclusive OR gate. , the other input terminals of each are commonly connected, a clock is supplied to this common connection point, and 1 is added to the least significant bit by the clock. The polarity inversion circuit 93 inverts the polarity of the two's complement code data only when the clock from the 1/2 frequency divider 95 is at high level, and outputs the data as is when the clock is at low level.

The output taken out from the polarity inversion circuit 93 is supplied to the burst gate circuit 96. A burst flag pulse is supplied from a terminal 97 to the burst gate circuit 96, and the burst gate circuit 96 supplies only data in the burst signal section to a digital integration circuit 98. The output of the shiburst gate circuit 96 is integrated by the integrating circuit 98.
This integrated data is converted into an analog signal by a D/A converter 99 and supplied as a control voltage to the clock generation circuit 33 via a low-pass filter 100.

The clock generation circuit 33 changes its frequency according to the limiting voltage so as to eliminate the phase difference.

In the digitizing circuit configured as described above, when a burst signal having the phase fluctuation shown in FIG. Sampling is performed as shown in Figure B. Although the sampled data is digitized by the A/D converter 31, it will be explained below using an analog waveform for the sake of simplicity.

A burst signal digitized by a sampling clock having a frequency of 4 fsc shown in FIG. 4B is supplied to a gate circuit 92 via a Y/C separation circuit 91. The gate circuit 92 is supplied with a clock having a frequency of 2 fsc as shown in FIG. 4C. Since the gate circuit 92 extracts data when the clock is at a high level, among the sampled data shown in FIG. 4B, the data shown in FIG.
Data is taken out every other data by the gate circuit 92 at the high level timing of the clock shown in FIG. The polarity inversion circuit 93 is supplied with a clock having a frequency fsc shown in the fourth diagram. Since the polarity inversion circuit 93 inverts the polarity of the data when the clock is at the low level and outputs the data when the clock is at the low level, the data taken out from the gate circuit 92 is Then, the polarity of every other piece of data is inverted at the timing of the NO level of the clock shown in the fourth diagram.

In other words, by the gate circuit 92 and the polarity inversion circuit 93,
The data shown in FIG. 4E is retrieved. Polarity reversal circuit 9
The data shown in FIG. 4E taken out at the output of No. 3 indicates the phase difference between the input burst signal and the sampling clock. In other words, a burst signal digitized by a sampling clock with a frequency of 4 fsc is
If the synchronization is complete and there is no phase difference, 1
Since O data of the burst signal is sampled for each sample, the polarity inversion circuit 93 outputs zero data. Also, if a phase difference occurs,
Data corresponding to the phase difference is output from the polarity inversion circuit 93.

The output of the polarity reversing circuit 93 shown in Figure 4E is supplied to the integrating circuit 98 via the
Integral data shown in Figure F is formed. The output of the integrating circuit 98 is converted into an analog signal by a D/A controller 99, and then sent to a VC
It is supplied as a control voltage to the clock generation circuit 33 having the configuration shown in FIG. The clock generation circuit 33 changes the frequency according to the voltage supplied from the D/A controller 99 via the low-pass filter 100, and synchronizes the sampling clock and the burst signal.

The clock generation circuit 33 may be a clock generation circuit using a digital circuit instead of a clock generation circuit using an analog circuit such as CO, and the frequency may be varied according to the detected phase difference. In that case, the D/A controller 99 becomes unnecessary.

Alternatively, the burst gate 1 circuit 96 may be placed before the gate circuit 92, and only the -(-st 11,'i) signal may be extracted in advance to detect the phase difference.

"Effects of the Invention-1 According to this invention, even if a phase fluctuation occurs in the input color subcarrier, the clock generation circuit can be controlled to generate a sampling clock that follows this phase fluctuation. A color video signal can be converted into a digital signal using a sampling clock synchronized with the subcarrier.Furthermore, according to the present invention, since a digital circuit is used for detecting the phase difference, the stability is high. A color video signal digitization circuit that can be easily integrated into a circuit can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a color video signal recording and reproducing circuit to which the present invention can be applied, FIG. 2 is a frequency spectrum diagram of a recorded signal, and FIG. 3 is a block diagram of an embodiment of the present invention. FIG. 4 is a time chart used to explain one embodiment of the present invention. 3 i --A/D converter, 33. Clock generation circuit, 92 Gate circuit, 931 Functional inversion circuit representative Masato Sugiura Figure 2 Figure 3 Figure 4 Upper fsc

Claims (1)

[Claims] A color video signal including a burst signal is supplied; l”L
an A/D converter, a clock generation circuit that generates a sampling clock for this A/D converter; A circuit for digitizing a color video signal, comprising a circuit for detecting a phase difference with a sampling clock, and controlling the clock generation circuit to cancel the phase difference.