JPH0548034B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a circuit for digitizing color video signals.

"Background technology and its problems" When a composite color video signal based on the NTSC system is digitized using a sampling clock with a frequency of 4fsc (fsc: color subcarrier), for example, this sampling clock is It is designed to be synchronized with the color subcarrier in the signal. However, when a phase variation occurs in the input color subcarrier, there is a problem in that when a fixed phase sampling clock is used, the synchronization with the color subcarrier is lost. To solve this problem, an APC (automatic phase control) circuit with an analog circuit configuration has been used in the past, but it has poor temperature characteristics and changes over time, making it difficult to integrate and miniaturize the circuit. be,
There was a drawback.

``Object of the Invention'' The present invention provides a color video signal digitization circuit that digitizes a color video signal using a sampling clock synchronized with a color subcarrier in an input color video signal, and which is highly stable and integrated in an integrated circuit. The purpose of this invention is to provide a digitization circuit that is easy to implement.

``Summary of the Invention'' The present invention provides an A/D converter that is supplied with a color video signal including a burst signal and outputs a digitized color video signal, a clock generation circuit that generates a sampling lock for the A/D converter, and an A/D converter that outputs a digitized color video signal. Detects the phase difference between the burst signal in the digital color video signal output from the /D converter and the sampling clock from the clock generation circuit, and controls the phase of the sampling clock so that this phase difference has a predetermined relationship. A 1/2 frequency divider circuit that divides the frequency of the sampling clock by 1/2,
a gate circuit that outputs a digitized color video signal when the logic level of the output of the 1/2 frequency divider circuit is a predetermined logic level; and a 1/4 frequency divider circuit that divides the frequency of the sampling clock by 1/4; When the logic level of the output of this 1/4 frequency divider circuit is at a predetermined logic level,
A polarity inversion circuit that inverts the polarity of the digitized color video signal output from the gate circuit and detects the phase between the digitized color video signal and the sampling lock, and a polarity inversion circuit that integrates the burst signal output from this polarity inversion circuit and converts the burst signal and sampling. This is a color video signal digitizing circuit that includes an integrating circuit that integrates the phase difference with the clock, and controls the phase of the sampling clock according to the output of the integrating circuit.

Embodiment FIG. 1 shows the overall configuration of a color video signal recording and reproducing apparatus to which the present invention can be applied. This color video signal recording/reproducing device uses a fixed magnetic head 1 to record one frame (or even one field) of a color still image signal on a magnetic sheet (not shown) as one or two circular tracks. It is something to remember. One magnetic sheet is rotatably housed within the hard shell and can form several dozen circular tracks. This magnetic sheet cassette is small and can be used as a recording medium for a still image video camera.

FIG. 1 shows the configuration of signal processing when recording and reproducing color video signals. This signal processing will be summarized below.

First, this embodiment can record both a multi-color video signal of the NTSC system and a component color video signal consisting of three primary color signals, for example. The main playback output is a composite color video signal, with component color video signals being output for monitor use. The signals recorded on the magnetic sheet are the FM modulated luminance signal Y _FM and FM
a modulated line-sequential color signal. Second
The figure shows the frequency spectrum of the recorded signal.
The center frequency f _Y of Y _FM is set to a predetermined frequency within the range of 6 to 7.5 MHz, the FM modulation center frequency f _R of the red color difference signal R-Y is set to, for example, 1.2 MHz, and the center frequency f Y of the blue color difference signal B-Y is set to 1.2 MHz. For example, the FM modulation center frequency f _B is 1.3MHz
It is said that These two color difference signals are line-sequentialized so that they appear alternately every 1H (one horizontal period). By line sequentialization, the recording signal band can be narrowed. The reason why the center frequencies of the two color difference signals have an offset from each other is to identify a line-sequential color sequence.

In addition, most of the signal processing is performed digitally, with the aim of stabilizing the operation and facilitating the implementation of an integrated circuit configuration. Further, the A/D converter provided on the input side of the signal processing section and the D/A converter provided on the output side thereof are used in common for both the recording circuit and the reproducing circuit. A D/A converter is further provided for forming component color video signals for monitoring.

The configuration of signal processing for recording and reproduction will be described in further detail with reference to FIG. In Figure 1,
2 is an input terminal to which an NTSC color video signal is supplied; 3, 4, and 5 are input terminals to which three primary color signals R, G, and B are respectively supplied from a color video camera, microcomputer, etc.; and 6 is an input terminal from which the three primary color signals are supplied. This is an input terminal to which a component color video signal and a corresponding composite synchronization signal SYNC are supplied.

The three primary color signals are supplied to the matrix circuit 7,
The signal is converted into a luminance signal Y, a red color difference signal RY, and a blue color difference signal B-Y. Two color difference signals outputted from the matrix circuit 7 are supplied to the input terminal of the switching circuit 8, and are taken out to the output terminal thereof alternately every 1H by a switching pulse from the terminal 9. This switching circuit 8 generates a line sequential color signal LSC. In FIG. 1, analog signals and digital signals are not distinguished, and recording signals and playback signals are similarly not distinguished.
The luminance signal is represented as Y, the red color difference signal and the blue color difference signal are represented as R-Y and B-Y, respectively, the composite color video signal is represented as NTSC, and the line sequential signal is represented as LSC. Wasare, 3
Each component of the primary color signal is represented as R, G, and B.

11, 12, 13, 14, 15, 16, 17
are respectively recording/reproduction switching switches. These recording/reproduction changeover switches 11 to 17 each have a recording side terminal (indicated by a black circle) and a reproduction side terminal (indicated by a white circle). FIG. 1 shows the connection state of these recording/reproduction changeover switches 11 to 17 during recording. 18 is a switch that can be switched depending on the difference between composite input and component input. The composite color video signal from the input terminal 2 is supplied to the input terminal 19 of the switch 18, the luminance signal from the matrix circuit 7 is supplied to the input terminal 20 of the switch 18, and one signal selected by the switch 18 is recorded and reproduced. The signal is supplied to the A/D converter 31 via the changeover switch 11. The line sequential color signal LSC from the switching circuit 8 is sent to the A/D converter 3 via the recording/reproduction changeover switch 12.
2.

The A/D converter 31 receives 4fsc (fsc: color subcarrier frequency) from the clock generation circuit 33.
sampling clock is provided. A sampling clock from a clock generation circuit 33 is supplied to the A/D converter 32 via a 1/2 frequency divider circuit 34. At the output of each of these A/D converters 31 and 32, digital data of 8 bits per sample is obtained. The clock generation circuit 33 generates a sampling clock whose frequency and phase are synchronized with the input signal by applying the present invention, and this sampling clock is supplied to the digital decoder 35 and is also control data is supplied to the clock generation circuit 33.

Output data from the A/D converter 31 is supplied to the digital decoder 35 through the recording side terminal of the recording/reproducing switch 13. The digital decoder 35 separates the composite color video signal into a luminance signal and a carrier color signal, generates a control signal for the clock generation circuit 33 from a burst signal included in the carrier color signal, and digitally demodulates the carrier color signal. processing, and processing for converting two color difference signals, which are demodulated outputs, into a line sequential color signal LSC.

The luminance signal from the digital decoder 35 is supplied to a digital pre-emphasis circuit 41.
Line sequential color signal from digital decoder 35
The LSC has a sampling rate of 2 fsc, and this line sequential color signal LSC is supplied to one input terminal 37 of the switch 36. The other input terminal 38 of the switch 36 is supplied with the line sequential color signal LSC from the A/D converter 32 via the recording/reproduction changeover switch 14. The line sequential color signal passed through this switch circuit 36 is supplied to an adder circuit 39.

ID data is supplied to the adder circuit 39 from a terminal 40 . This ID data is the red color signal R-
The values are different between the Y line and the blue color difference signal B-Y line. With this ID data,
The frequencies when FM modulation is not performed are different between the two color difference signals. The output of adder circuit 39 is supplied to digital pre-emphasis circuit 42. The outputs of the pre-emphasis circuits 41 and 42 are connected to digital FM modulators 43 and 44, respectively.
and the modulated outputs of both are sent to mixer 4.
Mixed with 5.

The output of the mixer 45 is the recording/playback switch 1.
The signal is supplied to the D/A converter 46 through the recording side terminal 5. From this D/A converter 46,
An analog recording signal with the frequency spectrum shown in the figure is taken out. This recording signal is supplied to the magnetic head 1 via the recording side terminal of the recording/reproduction changeover switch 16, the recording amplifier 47, and the recording side terminal of the recording/reproduction changeover switch 17. Recording signals are recorded on the magnetic sheet by this magnetic head 1.

A signal reproduced from the magnetic sheet by the magnetic head 1 is supplied to a high-pass filter 52 and a low-pass filter 53 via a reproduction amplifier 51.

The FM modulated luminance signal is taken out from the high pass filter 52, and the brightness signal is taken out from the low pass filter 53.
An FM modulated line sequential color signal is retrieved.
High pass filter 52 and low pass filter 53
The output of the husband is sent to the analog FM demodulation circuits 54 and 5.
5, and the respective demodulated outputs are supplied to de-emphasis circuits 56 and 57.

The luminance signal Y taken out from the de-emphasis circuit 56 is supplied to the A/D converter 31 through the reproduction side terminal of the recording/reproduction changeover switch 11, and is converted into a digital signal by the A/D converter 31. The line sequential color signal LSC taken out from the digital phasing circuit 57 is supplied to the A/D converter 32 through the playback terminal of the recording/playback switch 12, and is converted into a digital signal by the A/D converter 32. The digital luminance signal from the A/D converter 31 is sent to the delay circuit 61 through the playback terminal of the recording/playback switch 13.
supplied to The digital line sequential color signal from the A/D converter 32 is sent to the recording/reproducing switch 1.
The signal is supplied to the synchronization circuit 62 through the reproduction side terminal No. 4.

The synchronization circuit 62 supplies two line-sequential color difference signals to two 1H delay circuits connected in series.
Add the inputs and outputs of the series-connected delay circuits, halve this added output, take it out to the first and third output terminals, and take out the second and fourth output terminals from the connection point of the 1H delay circuit. It is of composition. The average value of the color difference signals of one of the first and third lines of the three consecutive lines is extracted from the first and third output terminals of the synchronization circuit 62, and the average value of the color difference signal of the other of the second line is extracted. Color difference signals are taken out to second and fourth output terminals. Therefore,
A switch circuit that selects one of the first and second output terminals generates a synchronized red color difference signal R-Y.
The synchronized blue color difference signal B-Y can be separated by a switch circuit at one of the third and fourth output terminals.

In order to ensure that the switch circuit of the synchronization circuit 62 operates correctly, an ID detection circuit 63 is provided. The ID detection circuit 63 detects ID data added at the time of recording, and uses this detection to correctly define the phase of the pulse that controls the switch circuit. Two color difference signals taken out from the synchronization circuit 62 are supplied to interpolation circuits 64 and 65. These interpolation circuits 64 and 65 interpolate, for example, the average value of two data before and after this data, and from the interpolation circuits 64 and 65, the color difference signals R-Y and B whose sampling rate has been converted to 4fsc are obtained. -Y is obtained. This sampling rate conversion is necessary to achieve the same sampling rate as the digital luminance signal.

Digital color difference signals taken out from each of interpolation circuits 64 and 65 are supplied to a hue correction circuit 66. The hue correction circuit 66 adjusts the phase, that is, the hue, of the color difference signal obtained by combining the two color difference signals by changing the values of the two color difference signals. The color difference signal taken out from the hue correction circuit 66 and the luminance signal from the delay circuit 61 are supplied to a digital matrix circuit 67. The delay circuit 61 connects the synchronization circuit 62 to the matrix circuit 67.
The amount of delay is the same as the delay of the color difference signal that occurs until the input of the color difference signal.

The digital three primary color signals taken out from the matrix circuit 67 are supplied to a color temperature correction circuit 68. Hue correction circuit 66 and color temperature correction circuit 68
Correction data is supplied to the controller 69 from a control section 69 consisting of a microprocessor and memory. The correction data is specified by a control signal from the terminal 70. This control signal is
The image is formed by the operator operating keys and levers while monitoring the hue and color temperature of the monitor image.

The digital three primary color signals taken out from the color temperature correction circuit 68 are supplied to a digital matrix circuit 71 and D/A converters 72, 73, and 74. These D/A converters 72, 73, 74
Analog component color video signals R, G, and B are taken out to output terminals 75, 76, and 77, respectively. Although not shown, this component color video signal is supplied to an input terminal of a color monitor receiver.

The digital matrix circuit 71 outputs a digital luminance signal and two digital color difference signals that have been corrected for hue and color temperature. The output of this matrix circuit 71 is supplied to a color encoder 78. Associated with the color encoder 78 is a synchronization and burst flag generation circuit 79 that generates a synchronization signal SYNC and a burst flag pulse BFP. The output of this color encoder 78 includes a digital
The NTSC composite color video signal is taken out, and this composite color video signal is sent to the recording/playback switch 1.
The signal is supplied to the D/A converter 46 through the reproduction side terminal of No. 5. A playback signal in the form of an analog composite color video signal is taken out from the output of the D/A converter 46 to the output terminal 80 through the playback side terminal of the recording/playback switch.

The present invention is applied to digitization in the A/D converter 31 or 32 of the above-mentioned color video signal recording/reproducing circuit. In other words, the clock generation circuit 33 is controlled by the control signal from the digital decoder 35, and the sampling lock for the A/D converter 31 or 32 is synchronized with the burst signal in the input color video signal. . A circuit for generating this control signal is provided within the digital decoder 35.

Further, an embodiment of the present invention will be described with reference to FIG.

An analog NTSC composite color video signal is supplied to the A/D converter 31 from an input terminal indicated at 90 in FIG. A sampling clock with a frequency of 4fsc is supplied from the clock generation circuit 33 to the A/D converter 31.
1 converts one sample into 8-bit digital data. As the clock generation circuit 33, for example, a VCO (voltage controlled oscillator) is used.

The output of the A/D converter 31 is a Y/C composed of a comb filter and a bandpass filter.
The signal is supplied to a separation circuit 91 and separated into luminance signal data in the color video signal and carrier color signal data including a burst signal. The separated luminance signal data is supplied to a pre-emphasis circuit 41, and the carrier chrominance signal data including the separated burst signal is extracted for digital demodulation and is supplied to a gate circuit 92. A clock having a frequency of 2fsc is supplied to the gate circuit 92 from the clock generation circuit 33 via a 1/2 frequency divider circuit 94. For example, in the gate circuit 92, one sample is 8
For bit data, eight AND gates are used, each bit of data is fed to one input terminal of each AND gate, the other input terminal of each is connected in common, and a clock signal is applied to this common connection point. The output data is taken out as is by the gate circuit 92 only during the period in which the clock from the 1/2 frequency divider circuit 94 is at a high level.

The output taken out from the gate circuit 92 is supplied to a polarity inversion circuit 93. The polarity inversion circuit 93 includes a 1/2 frequency divider circuit 94 from the clock generation circuit 33,
A frequency fsc clock is supplied via 95.
In the polarity inversion circuit 93, for example, when one sample is 8-bit data, eight exclusive OR gates are used, and each bit of data is supplied to one input terminal of each of the exclusive OR gates. The other input terminals of each are commonly connected, a clock is supplied to this common connection point, and 1 is added to the least significant bit by the clock. 1/2 frequency dividing circuit 95 by polarity inversion circuit 93
The polarity of the two's complement code data is inverted only when the clock from the clock is at a high level, and when the clock is at a low level, the data is output as is.

The output taken out from polarity inversion circuit 93 is supplied to burst gate circuit 96 . The burst flag pulse is connected to the burst gate circuit 96 at terminal 9.
7, and a burst gate circuit 96 supplies only the data of the burst signal section to a digital integration circuit 98. The output of the burst gate circuit 96 is integrated by the integrating circuit 98, and this integrated data is converted into an analog signal by the D/A converter 99, and then passed through the low-pass filter 100.
It is supplied as a control voltage to the clock generation circuit 33 via the clock generator circuit 33. The clock generating circuit 33 changes its frequency according to the control voltage so as to eliminate the phase difference.

In the digitizing circuit configured as described above, when a burst signal having the phase fluctuation shown in FIG. 4A is supplied from the input terminal 90, the digitization circuit shown in FIG. Sampling is performed as follows. The sampled data is digitized by the A/D converter 31,
In order to simplify the explanation, analog waveforms will be used below.

A burst signal digitized by a sampling clock having a frequency of 4 fsc shown in FIG. 4B is supplied to a gate circuit 92 via a Y/C separation circuit 91. The gate circuit 92 is supplied with a clock having a frequency of 2fsc as shown in FIG. 4C. Since the gate circuit 92 extracts data when the clock is at a high level, out of the sampling data shown in FIG. Data is taken out by gate circuit 92 and supplied to polarity inversion circuit 93 . The polarity inversion circuit 93 includes
A clock having a frequency fsc shown in FIG. 4D is supplied. Since the polarity inversion circuit 93 inverts the polarity of the data when the clock is at high level and outputs the data as it is when the clock is at low level, among the data taken out from the gate circuit 92, the data shown in FIG. The polarity of every other piece of data is inverted at the high level timing of the clock shown in D.
That is, the data shown in FIG. 4E is extracted by the gate circuit 92 and the polarity inversion circuit 93. The data shown in FIG. 4E taken out at the output of the polarity inversion circuit 93 indicates the phase difference between the input burst signal and the sampling clock. In other words, if a burst signal digitized using a sampling clock with a frequency of 4fsc is completely synchronized and there is no phase difference, 0 data of the burst signal will be sampled for each sample. Data of 0 is output from the polarity inversion circuit 93. Further, when a phase difference occurs, data corresponding to the phase difference is output from the polarity inversion circuit 93.

The output of the polarity inverting circuit 93 shown in FIG. 4E is supplied to an integrating circuit 98 via a burst gate 96, and integrated data shown in FIG. 4F is formed. The output of the integrating circuit 98 is converted into an analog signal by the D/A converter 99, and then passed through the low-pass filter 10.
0 as a control voltage for a clock generation circuit 33 configured by, for example, a VCO. The clock generating circuit 33 changes the frequency according to the voltage supplied from the D/A converter 99 via the low-pass filter 100 to synchronize the sampling clock and the burst signal.

Instead of a clock generating circuit using an analog circuit such as a VCO as the clock generating circuit 33, a clock generating circuit using a digital circuit may be used, and the frequency may be varied according to the detected phase difference. In that case, the D/A converter 99 becomes unnecessary.

Alternatively, the burst gate circuit 96 may be placed before the gate circuit 92, and only the burst signal may be extracted in advance to detect the phase difference.

"Effects of the Invention" According to the present invention, even if a phase variation occurs in the input color subcarrier, the clock generation circuit can be controlled to generate a sampling clock that follows this phase variation. Color video signals can be digitized with a sampling clock synchronized with the subcarrier. Further, according to the present invention, since a digital circuit is used for phase difference detection, etc., it is possible to realize a color video signal digitization circuit with high stability and easy integration into an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a color video signal recording/reproducing circuit to which the present invention can be applied.
FIG. 2 is a frequency spectrum diagram of a recording signal, FIG. 3 is a block diagram of an embodiment of the invention, and FIG. 4 is a time chart used to explain an embodiment of the invention. 31...A/D converter, 33...Clock generation circuit, 92...Gate circuit, 93...Polarity inversion circuit.

Claims (1)

[Scope of Claims] 1. An A/D converter to which a color video signal including a burst signal is supplied and outputs a digitized color video signal; a clock generation circuit that generates a sampling clock for this A/D converter; The phase difference between the burst signal in the digital color video signal output from the /D converter and the sampling clock from the clock generation circuit is detected, and the sampling clock is adjusted so that this phase difference has a predetermined relationship. In a color video signal digitization circuit that controls the phase, there is a 1/2 frequency divider circuit that divides the frequency of the sampling clock by 1/2, and a logic level of the output of this 1/2 frequency divider circuit that is at a predetermined logic level. When the logic level of the output of the gate circuit that outputs the digitized color video signal, the 1/4 frequency divider circuit that divides the frequency of the sampling clock by 1/4, and the 1/4 frequency divider circuit is set to a predetermined logic level. a polarity inverting circuit for inverting the polarity of the digitized color video signal output from the gate circuit and detecting the phase of the digitized color video signal and the sampling clock when the signal level is the same; a burst signal output from the polarity inversion circuit; and an integrating circuit that integrates the phase difference between the burst signal and the sampling clock, and a color video signal digitization circuit that controls the phase of the sampling clock according to the output of the integrating circuit. .