JPS607819B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to protection of a specific area on a main storage device.

Conventional memory protection is generally performed as follows. For example, the main storage device is divided into old units, each has a corresponding key, and one key is also assigned to the processing device side, and when processing information accesses the main storage device,
The main memory was protected by comparing the processing unit's key with the key on the main memory. More specifically, the keys on the main memory that contain the operating system, which is a fundamental part of the software, are assigned zero, and the keys on the main memory of the user area where the user program runs are assigned keys other than zero. It will be done. Furthermore, when a program for managing a system such as an operating system is run, zero is generally assigned to the key of the processing device, and when a user program is run, the same key as the respective area is assigned. A program with a processor key of zero can access any area. Although memory protection is performed in this way, there are the following problems. There is no protection against programs running with the processor key zero. In other words, if there is a mistake in a program that manages a system, such as an operating system, the contents on the main storage device may be corrupted, leading to a system failure. In particular, if the low address area (for example, 0 to 409 clause field) on the main memory that contains important parts of the management program is destroyed due to a program error, not only will the system go down, but the cause will have to be investigated afterwards. It can also cause serious problems. Considering the protection of the low address area (from address 0 to the maximum address that can be expressed by displacement) on the main memory, there are two possible methods for accessing this area. In other words, there are two methods: specifying number zero as the base register (when specifying number zero, the value zero is treated as the content of the base register, not the contents of register number zero), and addressing only by displacement, and This method specifies the value of the contents of this register plus the displacement to be within the low address area address. Programs that manage systems such as operating systems use the former method, that is, when accessing low area addresses that can be accessed only by displacement, use number zero as the base register, specify the address by displacement only, and use the base register. The contents of the registers used as is always a value larger than the maximum address that can be expressed by displacement. However, due to a mistake in the program that manages the system, such as the operating system, the contents of the base register may be destroyed, resulting in a value that is smaller than the maximum address that can be expressed by displacement, and this may destroy the low address area. There is a possibility that An object of the present invention is to provide an information processing apparatus which eliminates the above-mentioned conventional problems and has the effect of protecting a low address area.

The feature of this invention is that when generating an address, a register other than number zero is specified as the base register,
The present invention detects that the content of the register is smaller than the maximum value that can be specified by the displacement, and protects the low address area on the main memory that can be specified by the zero base register and the displacement. One embodiment will be described in detail with reference to the drawings.

FIG. 1 shows part of an example of an instruction format indicating the location of data. In this instruction, the location of data is defined by B (base register number) and O (displacement). If the contents of the register indicated by B are (B), then the address on the main storage device is expressed as {(B)+D}. FIG. 2 is a diagram showing an example of an information processing device that is an embodiment of the present invention and a conventional address generation device. For example, assume that the arithmetic function is configured in units of 32 bits, and the displacement is expressed in 12 bits. Instructions are read from memory 7 and sent to an instruction processing unit (not shown). Next, the address creation process will be briefly explained.

First, D (displacement) from the instruction processing unit.
is set in register BIO through BUS-A.
Of course, since D is 12 bits, the first 20 bits are set to zero. Next, the contents (B) of the general-purpose register designated by B (base register number) in FIG. 11 are sent to register A9 through BUS-A. Next, register A9 and register BIO are connected to 32-bit adder 11.
and the operation result is set in register CI2.
The contents of register CI2 are set in memory address register (MAR) 8 at the time of memory access to designate a memory address. Next, a device added in the present invention will be explained.

Detector 1 is a detector that detects that a general-purpose register other than number zero is designated. An AND circuit 2 combines the output of the detector 1 and a control signal 5 indicating that the current general-purpose register access is an access as a base register.
This is a circuit that takes ND. The detector 3 is a detector that detects whether the 8th to 19th bits of the contents of the register A9 are zero (assuming the memory address is 24 bits). A
The ND circuit 4 is a circuit that ANDs the output of the detector 3 and the output of the AND circuit 2, and outputs an error signal 6 when a condition is satisfied. Next, the operations of these devices during address generation will be described.

When generating an address, a general-purpose register other than number zero is specified,
When the control signal 5 indicates that it is a base register, a control signal is output from the AND circuit 2, and when the contents of this general-purpose register are set in register A9, the detector 3
detects whether bits 8 to 19 of the contents of register A9 are zero (detects whether they are within the 0 to 4 KB area), and
An error signal 6 is output by the ND circuit 4, indicating that an error has occurred. Access to the memory is prohibited by this error signal 6, and memory protection can be achieved. Since the configuration is as described above, the following effects can be obtained in the present invention.

1. Low address area can be protected.

2. Be able to check for improper use of registers.

(Check that the value of a general-purpose register used as a base register must be larger than the maximum value that can be expressed by displacement) If we consider only 1 above, after adding the contents of the base register and displacement, It is possible to protect the low address area by checking whether the address is smaller than the maximum value that can be expressed in the statement and whether this address uses the zeroth register as the base register. needs to check the contents of the general-purpose register that serves as the base register before creating the main memory address.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing part of an instruction format indicating the location of data, and FIG. 2 is a block diagram showing an embodiment of the present invention.

Explanation of symbols, 1, 3...detection circuit, 2, 4...
...AND circuit, 5...Control signal, 6...
Error signal, 7...Memory, 8...Memory address register, 9, 10, 12...Register, 11...Adder.

O Zuko 2

Claims (1)

[Claims] 1 A processing device that expresses an address using a base register that indicates the address that is the base point of a program and a displacement from that base point. In particular, when number zero is specified as the base register number, , in an address creation method processing device that treats the value zero as the content of the base register, there is a device that detects that a register other than zero is specified as the base register when generating an address, and a device that detects that a register other than zero is specified as the base register when generating an address, and and a device that detects that the value is smaller than the maximum value that can be specified by the displacement, and the device detects the address area in the main memory that can be specified by the base register numbered zero and the displacement. An information processing device that detects access to the area using a register other than the register and protects the area.