JPS6035694B2 - Main memory protection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a main memory protection system, and in particular, when a main memory is provided with a main memory key and the main memory is accessed from a central processing unit, the protection key provided inside the central processing unit and the main memory are protected. Relating to a main memory protection method that eliminates the need to rewrite the conventional protection key in the program state word each time the main memory is accessed in a data processing system that protects the main memory by comparing it with a key. .

Generally, in data processing systems, a main memory protection function using a main memory key and a protection key is employed to prevent the contents of main memory from being destroyed or improperly read due to program errors.

This gives, for example, a 4-bit code (main memory key) to each block of 204 & 2 in the main memory,
On the other hand, if the 4-bit code (protection key) in the program status word (PSW) does not match, access is restricted. In this way, when each key consists of 4 bits, it is possible to identify 16 ways as a target for memory protection, and therefore the hardware can protect a maximum of one program in the main memory at the same time. It becomes like this. By the way, when a program accesses a main memory area that is being used by another program, the program status can be determined by having the other program notify the address of the main memory area and the main memory key. Access is performed after rewriting the protection key within the word.

Therefore, for example, if a program alternately accesses its own main storage area and the main storage area belonging to another program, the protection key in the program state word must be rewritten each time the program accesses the main storage area. This has the problem that it is complicated to create. The present invention addresses the above problems and provides a protection key in the base register used when accessing the main memory, thereby making it possible to protect the main memory without changing the protection key in the program state word. Therefore, the present invention provides a main memory key in the main memory, and when the main memory is accessed from the central processing unit, a protection key prepared inside the central processing unit is compared with the main memory key. In a data processing system that protects main memory by performing, the above-mentioned protection key is provided both in the program state word and in the base register, and the protection key in the above-mentioned program state word is compared with the protection key in the above-mentioned base register. and a second comparing means for comparing the protection key in the base register and the main memory key,
Based on the comparison results of the first and second comparison means,
The present invention is characterized in that access to the main memory is controlled.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a diagram showing the location of each key responsible for main memory protection, and FIG. 2 is a block diagram of a data processing device according to an embodiment of the present invention. In Figure 1, 1
is a program state word that exists only once in the central processing unit (
The protection key (hereinafter referred to as the PSW key) within the PSW (PSW)
k), 2 is the protection key (Rk) in the base register, 3 is the address you want to access in the base register (R^),
4 is a main memory key (M ratio), and 5 is a main memory area (M) corresponding to the main memory key 4.

In Figure 2, 1 is the PSW key, same as 1 in Figure 1, and 1 is the base register number (B) in the instruction register.
, 12 is the index register number (
13 is a displacement (D), 14 is a check circuit that determines whether Pk is "0", 15 is an Rk key that calculates the base register from the base register number (B) and calculates the Rk of the base register. A reading circuit, 16, a main memory address creation circuit that calculates the main memory address to be accessed based on the base register number (B), index register number (x), and displacement (D); 17, a comparison between Pk and Rk; Comparison circuit 18 is M for determining the main memory key (M ratio) of the main memory area indicated by the main memory address to be accessed.
19 is a comparison circuit for comparing Rk and Mk, 2 is an error notification circuit, 21 is an access enable signal generation circuit, 22 is a main memory access circuit, and 3 are main memories.

The operation of the embodiment shown in FIG. 2 will be explained below. When the central processing unit retrieves a certain command from a certain program, the PSW key 10 contains the PSW of that program.
key is set.

The instruction held in the instruction register is composed of an instruction part and an address part (base register number 11, index register number 12, displacement 13). ○｝
If the PSW key 10 is "0", the check circuit 14 determines the value of the PSW key 10 in order to permit access as a privileged program regardless of the value of the main memory key.

If the value of the PSW key is "0", the main memory 30 is immediately accessed based on the address obtained by the main memory address generation circuit 16. On the other hand, the PSW key 10 is “
0”, the check circuit 14 to the comparison circuit 17
The value of Pk is sent to. ■ Rk key Kendori circuit 15 is
The protection key Rk in the base register is determined from the base register number 11 and sent to the comparison circuit 17.

[3' The main memory address creation circuit 16 adds the value in the base register specified by base register number 11, the value in the index register specified by index register number 12, and the value of displacement 13, Find the main memory address you want to access.

The obtained main memory address is sent to the main memory access circuit 22 and also to the M ratio key reading circuit 18 at the same time.
[4' The Mk key reading circuit 18 finds the main memory key Mk of the main memory indicated by the address to be accessed, and the comparison circuit 1
Send to 9.

[5} On the other hand, the comparison circuit 17 compares the key from the check circuit 14 and the key from the Rk key reading circuit 15, but it does not compare all the keys, but rather determines whether the problem program is a problem program or the monitor based on the value of the key. Determine whether it is a program.

For example, if key values from 0 to n are used in the monitor program, and values from n+1 to m are used in the problem program, when Pk = 0 to n, all are accessed, and Pk = n + 1 to m and Rk = n+1 to m, access is possible, and if Pk = n11 to m and Rk = 0 to n, it is an error, then all You can allow access to a memo of key values.

On the other hand, in the case of a problem program, the problem program itself can only access memory whose key values are allowed. If the comparison circuit 17 allows access, the key Rk is sent to the comparison circuit 19.
Further, if an error occurs in the comparison circuit 17, an error signal is sent to the error notification circuit 20. (6' Comparison circuit 1
9 is a circuit that generates an error if the key values do not completely match.

In the comparison circuit 19, if a mismatch is detected, an error signal is sent to the error notification circuit 20, and if a match is detected, an accessible signal is sent to the accessible signal generating circuit 21. '7} When the error notification circuit 20 receives an error signal from the comparison circuit 17 or the comparison circuit 19, it transmits a program error signal.

'8) When the check circuit 14 determines that Pk=0, the access enable signal generation circuit 21
9 detects Rk=Mk, it sends an access enable signal to the main memory access circuit 22.

'9) The main memory access circuit 22 receives the access enable signal from the access enable signal generation circuit 21 and accesses the main memory using the address sent from the main memory address generation circuit 16.

By configuring as described above, it is possible to access a main storage area having a different main storage key without changing the PSW key. That is, in general, monitor programs etc. often access main memory areas with several different main memory keys, and in such cases, conventionally, PS
The W key was changed each time, but according to this method, by storing in advance the main memory address to be accessed and the corresponding different protection keys in multiple base registers allowed by the central processing unit, PSW
Main memory access can be performed using the protected key in the base register in use without changing the key. For example, when main memory areas A, B, and C having different main memory keys a, b, and c are accessed alternately, in the conventional method, the contents of the PSW key are changed from a → b → c→a→b→c・・・・・
However, according to this method, base registers B^, BB, and Bc are allocated to main storage areas A, B, and C, respectively, and the protection keys in the base registers are rewritten in advance. If the settings are set to be a, b, and c, there is no need to change the PSW key even when the main storage areas A, B, and C are accessed alternately as described above.

As explained above, according to the present invention, the main memory can be accessed without changing the protection key in the PSW of the central processing unit while satisfying the main memory protection, which is an excellent feature of facilitating program creation. be effective.

Furthermore, the present invention has the effect of being able to handle main memory protection when the value of the protection key is further increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the location of each key responsible for main memory protection, and FIG. 2 is a block diagram of a data processing apparatus according to an embodiment of the present invention. In the figure, 1 and 10 are PSW keys, 2 is a protection key in the base register, 4 is a main memory key, 5 is a main memory area, 11 is a base register number, 12 is an index register number,
13 is a displacement, 14 is a check circuit, 15 is an Rk key reading circuit, 16 is a main memory address creation circuit, 17 is a comparison circuit, 18 is an Mk key reading circuit, 19 is a comparison circuit, 2 rivers and error notification circuits, 21 is a Accessible signal generation circuit, 22
is the main memory access circuit, and the main memory is the main memory. Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. In a data processing system in which a main memory key is provided in a main memory, and when the main memory is accessed from a central processing unit, a protection key prepared inside the central processing unit is compared with the main memory key. , a first comparing means for providing the protection key in both the program state word and the base register, and comparing the protection key in the program state word with the protection key in the base register; A second step that compares the protection key in the main memory key with the main memory key.
1. A main memory protection system, comprising a comparison means, and main memory access is controlled based on the comparison results of the first and second comparison means. 2. When accessing multiple main memories with different main memory keys, by assigning different base registers to each main memory, main memory access can be performed without changing the protection key in the program state word. The main memory protection system according to claim 1, wherein the main memory protection system enables