JPS6073758A - Disk cache control system - Google Patents

Abstract

PURPOSE:To improve throughput by installing a controller with a cache memory between a main memory unit and a disk driving device and processing data load. CONSTITUTION:It is assumed that a CPU10 comes to require input processing for a disk driving device 18a during program execution of the CPU10, and actuates a channel 12a. The channel 12a gives indications of reading data from said device 18a for a director 15a. When the data do not exist in a cache memory 17, the director 15a tries to read out the data directly from the disk driving device 18a. When this bus is processing, the director must wait until the processing finishes. Therefore the director 15a executes command re-trial, and set a channel switch 19a to a by-pass position. A director 15b is aware that a by-pass action is conducted and asks for issuing a re-trial command. Then the director 15b receives the command and resumes procesing. In such a constitution, throughput can be improved.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a disk cache control method, and in particular, the present invention relates to a disk cache control method. This invention relates to a disk cache control method that can prevent such problems and improve throughput.

[Background of the invention]

The degree of improvement in the access speed of disk devices in the disk subsystem is determined by the central processing unit (rCPUJ).
However, the access speed of the disk device has been a bottleneck from the perspective of improving the throughput of the entire system.

One method to solve this problem is to provide a cache memory between the main storage device and the disk drive, and to store data that is likely to be referenced by the CPU in the future in the cache memory, which allows high-speed input/output processing. A so-called disk cache has been realized.

When performing disk cache processing, the following new processing is often added for cache control. That is, as described above, in order to always hold data that is likely to be referenced by the CPU in the cache memory, a process is performed in which data accessed by the CPU is taken into the cache memory. This is because, in general, only a small number of files on the disk device are in use, and data near the data referenced by the CPU is considered to belong to the files currently in use. , data near the data referenced by the CPU is more expensive than other data.
This is because there is a high possibility that it will be referenced by U.

The above-mentioned process is a process that accompanies the input/output process from the CPU to the conventional disk drive device, and is necessarily necessary due to the presence of a cache. Generally, the above-mentioned loading process to the cache memory is performed for one track or several tracks, and for this process, the cache control unit is exclusively occupied for one to several disk revolutions, which reduces path usage efficiency. Undesirable.

Therefore, as a countermeasure to this problem, Hondekata first filed a patent application in 1983-
As proposed in No. 209420, "Parallel Transfer Type Director Device," it has independent cache memory write and read logic, and at the same time as data is loaded from the disk drive to the cache memory, other data in the cache memory is channel-transferred. , it is conceivable to adopt a so-called parallel transfer method. According to this method, an input/output command can be accepted while data is being loaded into the cache memory, and the input/output command is an input command to be transferred to the main memory, and the data targeted by the input command is the cache memory. input instructions can be executed in parallel with the load operation.

However, checking whether the target data exists in the cache memory involves accepting the input/output command and determining the location of the data targeted by the input/output command (address of the disk drive device).

cylinder head address or data ID, etc.) j
− If it turns out that the target data does not exist in the cache memory, or if it is an output instruction, the above input/output instruction cannot be processed on a separate data bus, and the cache There is a problem in that the above input/output command cannot be executed until the data load process is completed.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to prevent the cache control unit from becoming a bottleneck due to the addition of new processing due to the introduction of disk cache, especially when the above parallel transfer method is adopted. The object of the present invention is to provide a disk cache control method that prevents this from occurring.

[Summary of the invention]

The data bus utilization between the CPU and the disk drive is
Although various methods have been used to achieve uniformity, it is generally not uniform. The key point of the present invention is that the disk control device itself detects paths that are not used for data loading processing into the cache memory, and passes input/output operations to those paths, thereby increasing the efficiency of path usage. be.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration diagram of a computer system showing an embodiment of the present invention. In the figure, 10 is a CPU, 11 is a main storage device, 12a and 12b are channels, 14 is a disk control device, and 18a to 18n are a group of disk drive devices.

The CPU 10 decodes program commands and, if there is an input/output command for a disk drive in the disk drive groups 18a to 18n, sends the command to the channel 12a or channel 12.
It has the function of issuing commands to b. Also,
The main storage device 11 has a function of storing the calculation results of the CPU 10 and data from the disk drive device.

The channels 12a and 12b have the function of transferring data between the main storage device 11 and the disk control device 14, and other functions associated therewith. Furthermore, the disk controller 14 has data transfer between the channels 12a and 12b and the disk drive groups 18a to 18n, and functions associated therewith. The disk drive groups 18a-18n include C
Data is stored according to instructions from the PU 10. In addition,
The channel 12a and the channel 12b are the structure 2
They have the same function.

The internal structure of the disk control device 14 will be described below with reference to FIG.

The disk control device 14 includes a cache memory 17 for temporarily storing data, and a path control information buffer 16.

The channel 12a and disk drive groups 18a to 18
The director 15a performs data transfer and cache processing between the channel 12b and the disk drive groups 18a to 18n. Note that the director 15a and the director 15b have the same structure and function.

Here, the director 15a and the director 15b adopt the parallel transfer method, and the disk drive groups 18a to 1
It is assumed that a write operation from 8n to the cache memory 17 and a read operation from the cache memory 17 to the channel 12a or channel 12b can be performed simultaneously.

As described above, the cache memory 17 is a memory that stores data that is most likely to be referenced by the CPU in the near future among the data existing in the disk drive groups 18a to 18n. , control data indicating which part of which disk drive the block of data to be stored corresponds to (disk drive address).

It is also possible to store information such as cylinder addresses, etc.

The path control information buffer 16 is a buffer that stores the operating status of the director 15a and director 15b. A channel switch with a bypass mechanism (hereinafter simply referred to as a "channel switch") 19a has a function of bypassing activation from the channel 12a and passing it to the director 7-12b according to instructions from the microprogram of the director 15a. has the same configuration 9 as that provided in the director 15a.
It has a function.

The data bus between channel 12a and director 15a is
08. A data bus bypass path from the director 15a to the director 15b is designated as 21a. Symmetrical to this,
2 data buses between channel 12b and director 15b
0b, and the bypass route of the data bus from the director 15b to the director 15a is designated as 21b.

The addresses at both ends of the bypass paths 21a and 21b are made to match, so that even if activation is bypassed, it can be accepted at the end.

An outline of the operation of this embodiment configured as described above will be explained below. Note that in the following description, it is assumed that the parallel transfer method is adopted.

Assume that the CPU 10 now needs to perform input processing to the disk drive 18a in the disk drive group 18a to 18n while executing a program, and activates the channel 12a. The channel 12a instructs the director 15a to read the data from the disk drive 18a, but if the data does not exist in the cache memory 17, it tries to read it directly from the disk drive 18a. . Here, due to the parallel transfer operation, the director 15a transfers data to the disk drive device ta.
As mentioned above, if the data load process is being performed from b to the cache memory 17, in order to execute the direct read process using the path, it is necessary to wait until the data load process is completed. In order to avoid this, the present embodiment performs the following operation.

When the above-mentioned standby state is reached, the director 15a retries the command, and after confirming that the command retry has been accepted by channel L2b, sets the channel switch 19a to the bypass position.

At the same time, control information (including information necessary to continue the command chain) for informing the director 15b that the channel switch has been passed is stored in the path control information buffer 16.

When the director 15b is not performing input/output processing or data loading processing, the director 15b checks the contents of the path control information buffer 16 and learns that the director 15a has performed the bypass operation. A retry command issuance request is made, the command is received, and processing is resumed.

When the command chain ends, the director 15b
sets a flag indicating the end of processing in the path control information buffer 16, and the director 15a detects this flag and releases the bypass state of the channel switch 19a, returning the activation acceptance to the permitted state.

The above-mentioned channel switches 19a and 19b normally connect a channel and a corresponding director, but
It has a function of connecting to a director different from the corresponding director according to a bypass instruction, and can be realized by a hardware or software switch.

〔Effect of the invention〕

As described above, according to the present invention, a computer system including a main storage device and a plurality of disk drive devices includes a control device having a cache memory between the main storage device and a plurality of disk drive devices; In a disk subsystem in which a plurality of data buses connecting a main storage device, a cache memory, and a disk drive device exist, a data bus switching logic and control information regarding the switching logic are provided,
By referring to the control information, input/output processing is executed using a data bus that is not exclusively used by other input/output accesses or loading data from the disk drive device to the cache memory. By introducing this method, the increased processing can be smoothly processed, especially when the above-mentioned parallel transfer method is adopted. This has the remarkable effect of realizing a disk cache control method that prevents the cache control unit from becoming a bottleneck.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a computer system showing an embodiment of the present invention, and FIG. 2 is an internal configuration diagram of a disk control device which is a main part thereof. 11-10: CPU, 11: Main storage device, 12a, 12
b: Channel, 14: Disk control device, 15a,
15b: Director, 16: Path control information buffer, 17: Cache memory, 18a to 18n: Disk drive, 19a, 19b: Channel switch,
20a, 20b: Channel interface/data bus, 21a, 21b? Data bus bypass route. 12-

Claims (1)

[Claims] (1) A computer system including a main storage device and a plurality of disk drive devices, including a control device having a cache memory between the main storage device and the disk drive device, the main storage device, the cache memory and the disk drive device. In a disk subsystem in which there are a plurality of data buses connecting drive devices, the present invention has a data path switching logic and a storage means for storing control information regarding the switching logic, and refers to the storage means for the control information. , the switching logic is switched to perform input/output via a data bus that is not occupied by other input/output accesses or data loads from the disk drive to the cache memory.