JPS6055776A - Television receiver - Google Patents

Television receiver

Info

Publication number
JPS6055776A
JPS6055776A JP16476083A JP16476083A JPS6055776A JP S6055776 A JPS6055776 A JP S6055776A JP 16476083 A JP16476083 A JP 16476083A JP 16476083 A JP16476083 A JP 16476083A JP S6055776 A JPS6055776 A JP S6055776A
Authority
JP
Japan
Prior art keywords
circuit
supplied
screen
signal
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16476083A
Other languages
Japanese (ja)
Inventor
Tetsuo Kuchiki
朽木 哲雄
Toyokatsu Koga
豊勝 古賀
Makoto Kawachi
誠 河内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16476083A priority Critical patent/JPS6055776A/en
Publication of JPS6055776A publication Critical patent/JPS6055776A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To obtain smoothly and simultaneously the picture information on other channels through a single CRT and by means of a tuner selection circuit and a VIF video wave detecting circuit, by clamping the level of a video signal obtained before switching. CONSTITUTION:A signal (c) subjected to the video processing is supplied to a memory 20 and processed by clocks (a) and (b) to be supplied to a slave screen inserting circuit 18. While the output of a master screen video signal processing circuit 14 is divided into two parts. One of these two divided outputs is supplied to a switching circuit 23: while the other is supplied to the circuit 23 via a blanking signal inserting circuit 21 and a clamping circuit 22. Then the output of the circuit 23 is supplied to an inserting circuit 18, and the output of the circuit 18 is supplied to a CRT19. In such a constitution, the picture information on other channels can be obtained smoothly and simultaneously through a single CRT and by means of a tuner selection circuit 12 and a VIF video wave detecting circuit 13.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、受信中のテレビジフン画像の一部に他の番組
の映像を表示するテレビジョン受像機に関するもので、
いわゆるPicture in Picture(以−
ドPin Pと記す)と呼ばれているものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a television receiver that displays images of other programs as part of the television receiver image being received.
The so-called Picture in Picture
It is called ``PinP''.

従来例の構成とその問題点 近年、P+nPのテレビジョンが発表されている。Conventional configuration and its problems In recent years, P+nP televisions have been announced.

この方式の考え万を以下に示す。The idea behind this method is shown below.

第1図はPinPの概念図であり、(イ)はテレビジョ
ン受像機、(ロ)は親画面部、(/→は他のテレビ画面
を1+i小して挿入した子画面部である。
FIG. 1 is a conceptual diagram of PinP, in which (a) is a television receiver, (b) is a main screen area, and (/→ is a child screen area inserted by subtracting another television screen by 1+i).

第2図は従来のテレビジョン受像機の要部の回路ブロッ
ク図で、(υはアンテナ、(2a)(2b)はそれぞれ
親一部用および子画面用のチューナ・選局回路、(3a
)(3b)はそれぞれ親画面用および子03II向用の
■・映像検波回路、(4a ) (4b )はそれぞれ
親画面用および子画面用の映像信号処理回路、(5a)
(5b)はそれぞれ親画面用および子画面用の同期分離
回路、(6)は読み出し用クロック発生回路、(7) 
1i>J、を込み用クロック発生回路、(8)はメモI
J 、(9)は子■面挿入回路、叫はプラクン管である
。子画面用の信号は、同期分離回路(5b)で得られる
同期信号を用いて書込み用クロック発生回路(7)で得
られるクロックによりメモリ(8)に記憶される。更に
読み出し用クロック発生回路(6)で得られる読出用ク
ロスフにより、子画面信号をメモリ(8)より読み小腰
子画面挿入回路(9)で親画面1U号に挿入し、プラク
ン管叫tζ出力する。
Figure 2 is a circuit block diagram of the main parts of a conventional television receiver, where (υ is an antenna, (2a) and (2b) are tuner and channel selection circuits for the parent screen and child screen, respectively, and (3a)
) (3b) are video detection circuits for the main screen and child 03II, respectively, (4a) and (4b) are video signal processing circuits for the main screen and child screen, respectively, (5a)
(5b) is a synchronization separation circuit for the main screen and child screen, respectively, (6) is a readout clock generation circuit, and (7)
1i>J, is the clock generation circuit for inclusion, (8) is memo I
J, (9) is the small side insertion circuit, and the name is the Plaquen tube. The signal for the child screen is stored in the memory (8) by the clock obtained by the write clock generation circuit (7) using the synchronization signal obtained by the synchronization separation circuit (5b). Furthermore, the readout clock generated by the readout clock generation circuit (6) reads the child screen signal from the memory (8), and the child screen insertion circuit (9) inserts it into the main screen No. 1U, and outputs the plackon signal tζ. .

しかしながらこのようなテレビジョン受像機では、子画
面待、用のチューナ・MPA回路(2b)およびVIP
・映像検波回路(3b)を必要とし、コストの高いもの
でめった。
However, in such a television receiver, a tuner/MPA circuit (2b) for sub-screen standby and a VIP
- Requires a video detection circuit (3b), which is expensive and rare.

そこで、1つのチ1.−す・選局回路及びVIF・映像
検波回路でもってPinP回路を構成して、成るチャン
ネルの番組を児ながら他のチャンネルの番組を確かめる
方法が考えられた。その−例として、選局チャンネルを
記憶しておくチャンネルメ七り−に2つの番地を設けて
、現在選局中のザーヤンネ/I/(親画面)と前回選局
されていたチャンネルとを記憶させて、子画面に前回選
局されていたチャンネルの静止画を表示させるという方
法がある。この動作を具体的に説明すると、gf1回A
chを見ていたものとし、現在B cb (親画面)を
見ているとする。PinP他画面用スイッチキーを押す
と選局はBch −” Ach −+ Bchと行なわ
れる。この動作の原理的な時間変化を第3図に示す。す
なわち、PinP他画面スイッチキーを押すと、選局電
圧はvBからVAへ変化し、親画面はBchからAch
に切換わる。この時子画面は、Achの静止+1Ij(
1)の状態から、信号が完全にAchとなってからAc
h動画のモードとなる。そして動画の最終状態〔2〕か
ら親画面がAchの間に静止画モードに切換わるように
することにより、子画面はAch静止画〔1〕→Ach
静止画〔2〕へと変化し、同一チューナ・選局回路及び
VIP・映像検波回路でもって2C11を1つの画面で
見ることが可能となる。
Therefore, one chi 1. A method has been devised in which a PinP circuit is configured with a channel selection circuit and a VIF video detection circuit to check programs on other channels while checking the programs on that channel. As an example, two addresses are provided in the channel menu that stores the selected channel, and the currently selected channel (main screen) and the previously selected channel are stored. There is a method of displaying a still image of the channel that was previously selected on the sub screen. To explain this operation specifically, gf 1 time A
It is assumed that the user was watching CH and is currently viewing B cb (main screen). When the PinP other screen switch key is pressed, channel selection is performed as Bch -" Ach - + Bch. The principle of this operation over time is shown in Figure 3. In other words, when the PinP other screen switch key is pressed, The station voltage changes from vB to VA, and the main screen changes from Bch to Ach.
Switch to . At this time, the child screen is Ach still + 1Ij (
From state 1), after the signal becomes completely Ach, it becomes Ach.
h video mode. Then, from the final state of the video [2], by making the main screen switch to still image mode while Ach, the child screen changes from Ach still image [1] to Ach.
The image changes to a still image [2], and it becomes possible to view 2C11 on one screen using the same tuner/channel selection circuit and VIP/video detection circuit.

しかしこの場合には次のような欠点がある。現実問題と
して、選局は第3図に示したように急激に変化対応はで
きず、UHFのローチャンネルとノ・イチャンネル等の
場合、VB→vA→vBの大化ザイクルは0.15〜0
.3 secかかるのが通常でるる。その他、VIP 
−AGCの応答速度等で時間がかかる。人間の目は変化
が0.2 m以下でも十分に対層できるので、第3図の
ようにBchの親画面を見ている時、P inP他画面
画面スィッチキーすと、親画面にはAchの画面が映り
、さらにBch −) Ach 1八ch−”Bchの
過渡期の不要信号も人間の目に認知でき、見苦しい画像
となる。
However, this case has the following drawbacks. As a practical matter, the channel selection cannot respond to sudden changes as shown in Figure 3, and in the case of UHF low channels and no channels, the large cycle of VB → vA → vB is 0.15 ~ 0
.. It usually takes 3 seconds. Others, VIP
- It takes time due to AGC response speed, etc. The human eye can sufficiently see the contrast even if the change is less than 0.2 m, so when you are looking at the Bch main screen as shown in Figure 3, if you press the P inP other screen switch key, the Ach The screen of ``Bch-) Ach 18ch-'' is also visible to the human eye during the transition period of Bch, resulting in an unsightly image.

発明の目的 本発明は上記従来の欠点を解消するもので、PinP他
画面スイッチキーを押して、イ也チャンネルの映像信号
を子画面に静止状態で映し出す時、親画面の1+!Il
像を見ている人に不快感を与えることのないテレビジョ
ン受像機を提供することを目的とするO 発明の構成 上記目的を達成するため、本発明のテレビジョン受像機
は電子チューナと、この電子チューナを制御する制御手
段と、前記電子チューナにより選択受1ビされたテレビ
ジョン信号を陰極線管に映出させる映出手段と、前記電
子チューナによる1つの選局系統により選択受信されか
つ前記陰極線管に映出された画像の一部に同じ選局系統
により受信されたテレビジョン信号をメモリ手段を用い
て挿入する挿入手段と、前記陰極線管に供給されるイぎ
号を所定期間にわたってそれ以前の映像信号の平均電圧
レベルに応じた電圧の信号に切シ換える9J換手段とを
備えた構成である。
OBJECTS OF THE INVENTION The present invention solves the above-mentioned drawbacks of the conventional technology.When the PinP other screen switch key is pressed to display the video signal of the Iya channel on the sub screen in a static state, the 1+! Il
SUMMARY OF THE INVENTION In order to achieve the above object, the television receiver of the present invention includes an electronic tuner and an electronic tuner. a control means for controlling an electronic tuner; a projection means for projecting a television signal selectively received by the electronic tuner onto a cathode ray tube; insertion means for inserting a television signal received by the same channel selection system into a part of the image projected on the tube using memory means; This configuration includes a 9J switching means for switching to a signal with a voltage corresponding to the average voltage level of the video signal.

実施例の説明 以下、本発明の一実施例について、図面に基づいて説明
する。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

第4図は本発明の一実施例におけるテレビジョン受像機
の要部の回路ブロック図で、αυはアンテナ、(6)は
チューナ・選局回路、頭はVIP・映像検波回路、u4
105は映像信号処理回路、QfHす同期分離回路、(
17)は読み出し・書込みタロツク発生回路、a樽は子
画面挿入回路、cIIは陰極線管、翰はメモリ、なりは
ブランキング信号挿入回路、(ホ)はクランプ回路、轍
はスイッチング回路である。子画面用の映像1ぎ号処理
畑れた信号tc)が映像信号処理回路αQからメモリ(
イ)に入力され、読み出し・書込みタロツク発生回路α
ηからの読み出し用クロック(at及び書込み用クロッ
ク(blで処理された後、子両而沖人回路(ト)に入力
され、その出力は1会極線管(11に出力される。現画
面用映像信号処理回路(14)の出力は、−がブランキ
ング信号挿入回路シυとクランプ回路翰とを通して他山
面切換時用スイッチング回路に)の端子(23b)に入
力され、残部が他山面切換時用スイッチング回路に)の
端子(23a)に入力され、Cのスイッチング回路(2
)の出力が子;曲面挿入回路08)に人力される。他部
面切換時用スイッチング回路脅にはチューナ・選局回路
α′4よりスイッチング信号が加えられている。
FIG. 4 is a circuit block diagram of the main parts of a television receiver according to an embodiment of the present invention, αυ is an antenna, (6) is a tuner/channel selection circuit, the head is a VIP/video detection circuit, and u4 is a tuner/channel selection circuit.
105 is a video signal processing circuit, a QfH synchronization separation circuit, (
17) is a read/write tarlock generation circuit, a barrel is a small screen insertion circuit, cII is a cathode ray tube, 翺 is a memory, nari is a blanking signal insertion circuit, (e) is a clamp circuit, and rut is a switching circuit. The video signal processing field tc) for the child screen is transferred from the video signal processing circuit αQ to the memory (
A) is input to the read/write tarlock generation circuit α
After being processed by the read clock (at) and the write clock (bl) from η, it is input to the secondary Okinawa circuit (G), and its output is output to the 1st electrode ray tube (11).Current screen The output of the video signal processing circuit (14) is inputted to the terminal (23b) of the switching circuit for switching the other side through the blanking signal insertion circuit υ and the clamp circuit, and the remaining part is input to the terminal (23b) of the switching circuit for switching the other side. It is input to the terminal (23a) of the switching circuit for plane switching (23a) of the C switching circuit (23a).
) is manually input to the child curved surface insertion circuit 08). A switching signal from the tuner/channel selection circuit α'4 is added to the switching circuit for switching other parts.

第3図において親画面がB cbO時、第4図に示すス
イッチング回路(ハ)は端子(23a)側に切換わった
状態でおり、通常の信号を陰極線管0呻に送っている。
In FIG. 3, when the main screen is BcbO, the switching circuit (c) shown in FIG. 4 is switched to the terminal (23a) side and sends a normal signal to the cathode ray tube 0.

次に他山面切換スイッチキーを押すと、チューナ・選局
回路(2)よりスイッチング回路(2)を制御する信号
が加えられて、スイッチング回路に)は端子(23b)
側に切換わる。第3図で現画面がBchの時、プランキ
ンゲイ=号挿入回路Qυは端子(21a)側に9ノ換わ
った状f、Iになっており、映像信号処理回路Q弔の出
力は、クランプ回路四を通じて他11而切換時用スイッ
チング回路脅の端子(23b) Vこ入力される。ブラ
ンキング信号挿入回路eυは第3図でAchの状態にな
ると端子(21b)側にvJ換わり、スイッチング回路
翰の出力にはクランプ回路(2)の出力が出る。このク
ランプ回路(2)は今まで映し出されていたBchの信
号レベルを記憶している回路、例えば容量等で平均電圧
をある期間蓄積できる回路であればよい。
Next, when the other side changeover switch key is pressed, a signal to control the switching circuit (2) is applied from the tuner/tuning circuit (2), and the switching circuit is connected to the terminal (23b).
Switch to the side. In Fig. 3, when the current screen is Bch, the Plankingey signal insertion circuit Qυ is switched to the terminal (21a) side and becomes f, I, and the output of the video signal processing circuit Q is a clamp. Through the circuit 4, the other 11 is inputted to the terminal (23b) of the switching circuit for switching. When the blanking signal insertion circuit eυ enters the Ach state in FIG. 3, VJ is switched to the terminal (21b) side, and the output of the clamp circuit (2) is output from the switching circuit. This clamp circuit (2) may be any circuit that stores the Bch signal level that has been displayed up until now, such as a circuit that can store an average voltage for a certain period of time using a capacitor or the like.

このように、親画面がある時間だけ他のチャンネルに切
り替る時、QJシ替る前の親画面の映像信号の平均電圧
レベルまたはその電圧レベルに応じた電圧の映像信号に
なるので、テレビ受像機を見ている者にとって述和感が
ない。また他チャンネルか映ったり、不要モードが映る
こともない。
In this way, when the main screen switches to another channel for a certain period of time, the average voltage level of the video signal on the main screen before QJ switching or the video signal with a voltage corresponding to that voltage level, so the TV receiver There is no sense of harmony for those watching. Also, other channels or unnecessary modes will not be displayed.

かくして、1つのチューナ・選局回路@及び■正・映像
検波回路−を用いて、逮和感なく他チャンネルの画像情
報を同時に1つの陰極線管U口jじて得ることができる
。またこのPinP他画面スイッチキーヲロる周期で繰
り返し押す(パルスを発生させる)ことによシ、他チャ
ンネルのこま送りも可能である。
Thus, by using one tuner/channel selection circuit and one positive/video detection circuit, it is possible to simultaneously obtain image information of other channels through one cathode ray tube U without any sense of incongruity. Also, by repeatedly pressing this PinP other screen switch key (generating pulses) at the cycle of rotation, it is also possible to advance frames of other channels.

発明の詳細 な説明したように本発明によれば、各々1つのチューナ
・選局回路及びVIF・映像検波回路を用いて、才和感
なく、他チャンネルの11像情報を同時に1つの陰極線
管を通じて得ることができる。
DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, 11 image information of other channels can be simultaneously transmitted through one cathode ray tube using one tuner/channel selection circuit and one VIF/video detection circuit. Obtainable.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は受信中のテレビジョン画像の一部に他の香組を
写し出すようにしたテレビジョン受像機の映出状態を示
す概念図、第2図は従来のテレビジ3ン受像機の要部の
回路ブロック図、第3図は同テレビジョン受像機の動作
説明図、第4図は本発明の一実施例におけるテレビジョ
ン受像機の要部の回路ブロック図でおる。 o′4・・・ヂ、−す・選局回路、u:1・・・VIF
・映像検波回路、(1410〜・・・映像信号処理回路
、叫・・同期分離回路、αη・・・読み出し・書込みク
ロ7り発生回路、α稗・・・子画面挿入回路、01・・
・陰極線管、四・・・メモリ、&I)・・・ブランキン
グ信号挿入回路、(2)・・・クランプ回路、翰・・・
スイッチング回路 第1図 43b 第3図 B!tPJ 第4図
Figure 1 is a conceptual diagram showing the image state of a television receiver that projects other incense groups in a part of the television image being received, and Figure 2 is the main part of a conventional television receiver. FIG. 3 is an explanatory diagram of the operation of the television receiver, and FIG. 4 is a circuit block diagram of essential parts of the television receiver according to an embodiment of the present invention. o'4...di, -s/tuning circuit, u:1...VIF
・Video detection circuit, (1410~...Video signal processing circuit, Message...Synchronization separation circuit, αη...Read/write black 7 generation circuit, αι...Small screen insertion circuit, 01...
・Cathode ray tube, 4...memory, &I)...blanking signal insertion circuit, (2)...clamp circuit, wire...
Switching circuit Figure 1 43b Figure 3 B! tPJ Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1、を子チューナと、この電子チューナを制御する制御
手段と、前記電子チューナにより選択受信されたテレビ
ジョン信号を陰極線管に映出させる映出手段と、前記電
子チューナによる1つの選局系統によシ選択受信されか
つ前記陰極線管に映出された画像の一部に同じ選局系統
により受信されたテレビジョン信号をメモリ手段を用い
て挿入する挿入手段と、前記陰極線管に供給される信号
を所定期間にわたってそれ以前の映像信号の平均電圧レ
ベルに応じた電圧の信号に切り換える切換手段とを備え
たテレビジョン受像機。
1, a slave tuner, a control means for controlling the electronic tuner, a projection means for projecting a television signal selectively received by the electronic tuner onto a cathode ray tube, and one channel selection system including the electronic tuner; insertion means for inserting, using memory means, a television signal received by the same channel selection system into a part of the image selectively received and projected on the cathode ray tube; and a signal supplied to the cathode ray tube. and switching means for switching over a predetermined period of time to a signal with a voltage corresponding to the average voltage level of the previous video signal.
JP16476083A 1983-09-06 1983-09-06 Television receiver Pending JPS6055776A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16476083A JPS6055776A (en) 1983-09-06 1983-09-06 Television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16476083A JPS6055776A (en) 1983-09-06 1983-09-06 Television receiver

Publications (1)

Publication Number Publication Date
JPS6055776A true JPS6055776A (en) 1985-04-01

Family

ID=15799401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16476083A Pending JPS6055776A (en) 1983-09-06 1983-09-06 Television receiver

Country Status (1)

Country Link
JP (1) JPS6055776A (en)

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