JPS6055129U - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPS6055129U JPS6055129U JP14723983U JP14723983U JPS6055129U JP S6055129 U JPS6055129 U JP S6055129U JP 14723983 U JP14723983 U JP 14723983U JP 14723983 U JP14723983 U JP 14723983U JP S6055129 U JPS6055129 U JP S6055129U
- Authority
- JP
- Japan
- Prior art keywords
- output
- output circuit
- transistors
- high impedance
- impedance state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の出力バッファ回路を示す。第２図は本考
案の一実施例を示すための出力バッファ回路図。第３図
は従来の出力バッファ回路を説明するためのタイミング
図、第４図本考案あ一実施例の出力バッファ回路を説明
するためのタイミング図。
なお図において、Ｑ１〜Ｑ６・・・・・・トランジスタ
、ＶＤＤ・・・・・・電源、ＯＵＴ・・曲出力端子、Ｖ
ｌ。FIG. 1 shows a conventional output buffer circuit. FIG. 2 is an output buffer circuit diagram showing an embodiment of the present invention. FIG. 3 is a timing diagram for explaining a conventional output buffer circuit, and FIG. 4 is a timing diagram for explaining an output buffer circuit according to an embodiment of the present invention. In the diagram, Q1 to Q6...transistor, VDD...power supply, OUT...music output terminal, V
l.
Claims (1)
電源間に複数個の出力トランジスタが接続され前記複数
個の出力トランジスタの出力端子が共通に外部出力端子
に接続され、前記複数個の出力トランジスタにおける高
インピーダンス状態及び能動状態を選択するための制御
信号を前記出力トランジスタに加えるタイミングを個々
の出力トランジスタ毎にずらすようにしたことを特徴と
する出力回路。In an output circuit with an output high impedance state,
A plurality of output transistors are connected between power supplies, output terminals of the plurality of output transistors are commonly connected to an external output terminal, and a control signal for selecting a high impedance state and an active state of the plurality of output transistors. 1. An output circuit characterized in that the timing at which the ? is added to the output transistor is shifted for each output transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14723983U JPS6055129U (en) | 1983-09-22 | 1983-09-22 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14723983U JPS6055129U (en) | 1983-09-22 | 1983-09-22 | Output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6055129U true JPS6055129U (en) | 1985-04-18 |
Family
ID=30327492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14723983U Pending JPS6055129U (en) | 1983-09-22 | 1983-09-22 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6055129U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63259592A (en) * | 1987-04-16 | 1988-10-26 | セイコーエプソン株式会社 | Multi-output driver |
| JPS63309992A (en) * | 1987-06-10 | 1988-12-19 | セイコーエプソン株式会社 | Multi-output driver |
-
1983
- 1983-09-22 JP JP14723983U patent/JPS6055129U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63259592A (en) * | 1987-04-16 | 1988-10-26 | セイコーエプソン株式会社 | Multi-output driver |
| JPS63309992A (en) * | 1987-06-10 | 1988-12-19 | セイコーエプソン株式会社 | Multi-output driver |
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