JPS6039127U - power circuit - Google Patents
power circuitInfo
- Publication number
- JPS6039127U JPS6039127U JP13257383U JP13257383U JPS6039127U JP S6039127 U JPS6039127 U JP S6039127U JP 13257383 U JP13257383 U JP 13257383U JP 13257383 U JP13257383 U JP 13257383U JP S6039127 U JPS6039127 U JP S6039127U
- Authority
- JP
- Japan
- Prior art keywords
- output
- transistor
- base
- input
- output transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の電源回路の構成を示す図、第２図は同、
説明図、第３図は本考案の電源回路の一実施例の構成を
示す図、第４図は同、説明図である。
１は入力端子、２は出力トランジスタ、３は出力端子、
４は制御トランジスタ、５は時定数回路である。Figure 1 shows the configuration of a conventional power supply circuit, Figure 2 shows the same configuration,
An explanatory diagram, FIG. 3 is a diagram showing the configuration of an embodiment of the power supply circuit of the present invention, and FIG. 4 is an explanatory diagram of the same. 1 is an input terminal, 2 is an output transistor, 3 is an output terminal,
4 is a control transistor, and 5 is a time constant circuit.
Claims (1)
タ２のコレクタに接続し、このコレクタを第１の抵抗Ｒ
１を介して上記出力トランジスタ２のベースに接続する
とともにエミッタから出力端子３を通して直流出力電圧
を取り出すようにした構成において、上記出力トランジ
スタ２のベースを制御トランジスタ４を介して接地する
ととも。 に、上記入力端子１を時定数回路５を介して接地し、こ
−の時定数回路５により上記制御トランジスタ４を直流
入力電圧印加後の一定時間導通状態に保持することを特
徴とする電源回路。[Claims for Utility Model Registration] An input terminal 1 to which a DC input voltage is input is connected to a collector of an output transistor 2, and this collector is connected to a first resistor R.
In the structure in which the base of the output transistor 2 is connected to the base of the output transistor 2 through the control transistor 1 and the DC output voltage is taken out from the emitter through the output terminal 3, the base of the output transistor 2 is grounded through the control transistor 4. A power supply circuit characterized in that the input terminal 1 is grounded via a time constant circuit 5, and the time constant circuit 5 maintains the control transistor 4 in a conductive state for a certain period of time after application of a DC input voltage. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13257383U JPS6039127U (en) | 1983-08-26 | 1983-08-26 | power circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13257383U JPS6039127U (en) | 1983-08-26 | 1983-08-26 | power circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6039127U true JPS6039127U (en) | 1985-03-18 |
Family
ID=30299339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13257383U Pending JPS6039127U (en) | 1983-08-26 | 1983-08-26 | power circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6039127U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0381229U (en) * | 1989-12-07 | 1991-08-20 |
-
1983
- 1983-08-26 JP JP13257383U patent/JPS6039127U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0381229U (en) * | 1989-12-07 | 1991-08-20 |
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