JPS6051891A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a display device that provides a suitable matrix display when applied to a multi-channel PCM recorder remote controller and the like.

BACKGROUND TECHNOLOGY AND PROBLEMS A display device such as the one shown in FIG. 1 is used in a remote controller of a PCM recorder to display a display corresponding to a key operation or a state of a controlled part controlled by the key operation. There is.

In the figure, (11 indicates a key display section connected in a matrix, and this example shows an example of (4x4) Ma) IJ Fu2 display. In order to control the display state of the key display section (11), a source circuit (21) is provided on the column line side of the key display section (11).
The clock CK is sent to the selector (5) via the counter (4).
), the signal selected by the selector (5) is supplied to the source circuit (2), and a display drive signal (current) is sequentially supplied to the corresponding column line at a predetermined period.

A tank circuit (61) is provided on the row line side.Terminal 1 (7
The input data (display data) supplied through 1 is supplied to the register (8), and the output data is sent to the sink circuit (
6), the corresponding indicator light L (in this example, a light emitting diode element) of the key display section (1) is driven according to the display data supplied to the terminal (71), and the light is turned on or off. will be carried out.

The display data is data corresponding to a key operation or a control state of a controlled unit caused by the key operation.

By the way, in this display device 01, since the display data supplied to the terminal (7) is only a command signal for turning on and off the indicator light, only the on and off states of key operations can be displayed. Therefore, for example, a so-called response mode (a third mode other than on and off) cannot be displayed until the controlled unit starts operating in response to a key operation.

In fact, the response time from a key operation to the start of operation of the controlled part related to that key operation differs depending on the controlled part, so the operator should keep in mind the response time of the controlled part in advance and select the next operation mode. Operation timing must be determined. Therefore, a display device without a response mode cannot accurately select a mode.

Since the response mode only needs to be distinguishable from other modes, the mode can be displayed by, for example, blinking an indicator light. 1st
In order to realize this response mode with the configuration shown in the figure, for example, the sink circuit (6) is supplied with a blinking control pulse PFL of a predetermined period, for example, a period of 1 second, from the terminal (9). It is sufficient to gate the display data supplied to each provided row line for a predetermined period of time, in this example 0.5 seconds, by means of this blinking control pulse PFL.

That is, as shown in FIG. 2, if the blinking control pulse PFL is supplied during the response period of the controlled part as shown in FIG. 2B by the pulse PON obtained by key operation, the indicator light will blink during the response period. , while it is blinking, it can be visually confirmed that the controlled unit is responding. When the controlled part is in the operation mode, the indicator light is turned on by holding the flashing control pulse PFL at a high level, for example, with the output that detects this mode, and the transition from the response mode to the operation mode is confirmed. You can visually check it again and know the timing of the operation accurately.

By the way, in order to achieve the third display state as described above, the flashing control pulse PFL as described above is applied to the sink circuit (61).
, it is necessary to provide a gate circuit for display data and blinking control pulse PFL for each row line, so as the number of key display sections +11 increases, the number of gates used increases. The disadvantage is that the circuit becomes complicated and the circuit scale increases.

Furthermore, when controlling the flashing of the indicator light using the flashing control pulse PFL, key operations occur asynchronously with the flashing control pulse PFL, so for example, as shown in FIG. 3B, during the low level period of the flashing control pulse PFL. When a key is operated, the blinking control pulse PFL 17) During the low level period, the indicator light does not light up at all. This display mode time delay gives the operator the illusion that the input instruction itself has been delayed, causing discomfort and being forced to constantly check whether the indicator light is lit, which is extremely inconvenient in terms of operation.

The same effect can be achieved even if the display data itself supplied to the terminal (7) is inverted at the cycle of the blinking control pulse PFL during the response period of the controlled section, instead of supplying the blinking control pulse PFL to the sink circuit (6). The third display state can be realized.

However, this method has the following drawbacks.

That is, since the CPU provided in the remote controller normally processes bytes, information on indicator lights to be blinked must be stored in byte format. As shown in Figure 4, if the MSB bit (bit 7) of the display data composed of 8 bits is used as a blinking display bit, this MSB bit is periodically inverted based on the blinking display command. Ru. By repeating the MSB bits l'' and 0', the corresponding indicator light can be set to display the response mode.

However, in this case, it is necessary to perform bit conversion processing from byte format to bit format, so as the number of indicator lights for blinking control increases, bit conversion processing takes time, and the conversion processing time is not constant. cannot be secured. Therefore, the original processing time in the controller is reduced and many temporal uncertainties are included, and it is necessary to take into consideration the temporal uncertainties in display processing when performing this processing.

Purpose of the Invention Therefore, in the present invention, when the state of a controlled part controlled by a key operation is displayed by turning on, off, or blinking an indicator light, it is possible to reduce the burden on this process due to the blinking conversion process, and to reduce the overhead. It is designed to reduce the amount of

Summary of the Invention Therefore, in the present invention, a display device is configured as follows. That is, the display device ID is determined by a data supply unit having an image memory that supplies display data to the display unit that displays the state in response to key operations, and a display data control unit that sends display data to this data supply unit. This display data control unit has a logic unit including a CPLI that converts input data according to key operations etc. into display data, and first and second memories (first and second memories) that store the output of this logic unit. A second table) and a gate section that alternately gates the display data output from these memories at a predetermined period, and by supplying the gated display data to the image memory, the display data can be used to control the display section. The above object has been achieved by controlling the lighting state of the lamp.

Embodiment Next, a case in which an example of the display device of the present invention is applied to a display device of a remote controller in a PCM recorder or the like will be described in detail with reference to FIG. 5 and subsequent figures.

In FIG. 5, a9 is a data supply unit for supplying display data to the display unit fi+, which includes the above-mentioned counter (4), selector (51) and register (8).
), the image memory (16+) with a memory capacity corresponding to the array of indicator lights (11) is provided, and its output data is processed by the selector a71 in synchronization with the signal output from the counter (41). The output data is selected for each line, and its output data is written into a register (81).
That is, the lighting of the indicator light is controlled based on the display data.

Further, αchin is a display data sending unit, and C11l is a conversion logic unit. The data sent from the data sending section (a) is data indicating the state of the controlled section that is controlled in response to the key operation. The conversion logic unit (21+) has a CPU and a memory, and converts into display data corresponding to row lines and column lines for matrix display.

The display data output from the conversion logic unit CIJI is stored in the first and second memories (2) forming the display data control unit.
2aχ (22b). Memory (22a), (
22b) is for buffering one display data of the conversion logic section, and is configured as a matrix image table. These memories (22a),
(22b) stores display data for controlling lighting, turning off, and blinking of a plurality of indicator lights.

The output data of the memories (22a) and (22b) are supplied to a gate section (c) composed of analog gates (23a) and (23b), respectively.

(23a) and (23b) have terminal Q
1, a blinking control pulse PFL having the above-mentioned period is supplied. However, the inverted output is supplied to one of the two game consoles (23b). The output of the gate section (c) and the lighting display data formed in the conversion logic section (211) are directly supplied to the image memory 4 via the OR circuit (c).

Here, the conversion logic section (
As shown in FIG. 3B, the display data from 211 is displayed by key operation.
This is display data for controlling 1 to turn on.

An example of display data written to the above-mentioned memories (22a) and (22b) will be explained with reference to FIG. 6. now,
Focusing on one indicator light among the plurality of indicator lights, when turning on this indicator light, a logic level "m" is set in the corresponding addresses of the first and second memories, respectively.
1'' data, and conversely, to turn off the light, write data of logic level e+O*.Also, when you want to make the indicator light blink, refer to the first memo I) (22a)
The logic level "1" data is stored in the second memory (22b
) may be written with logic level "0" data.

That is, by writing such data based on the input data of the data sending section (1), one AND gate (23a) is turned on and the first memory (22a) is turned on during the period FA shown in FIG. 3C. ) The display data written to the image memory (161) is written to the register (8) via the selector a71 for each line, and the indicator light of the display section (1) is switched on based on the display data. The lighting is controlled.In the next period PB, the other AND/GO (23b) is opened and the second memory (23b) is opened.
Since the data written in 22b) is written into the image memory [e, the lighting of the corresponding indicator light is similarly controlled.

The display data from the conversion logic unit 121) is
', regardless of the blinking control pulse PFL,
If it is always on and the display data is ``θ'', it is always off. Then, 1'' is displayed in the first memory (22a) and 0'' is displayed in the second memory (22b). When data is written, the light is turned on during the period PA and turned off during the period FB, and as a result of repeating this, the indicator lamp becomes a blinking state and the response mode is displayed.

In this way, the first and second memories (22a), (2
For 2b), display data corresponding to the display mode is generated by the conversion logic unit +21J and 1 is written only when a state in which the data should be written occurs. Since new data is written into the image memory ae at the same time as this writing, in the present invention, the operation mode is controlled by independent routines as shown in FIGS. 7 and 8.

That is, during the pause period PA shown in FIG. 7, the first memory (22
The display data of a) is output and written to the image memory ae, and in the next pause period PB, the display data of the second memory (22b) is output in synchronization with the falling edge of the pause period PB and is written to the image memory α. be included.

On the other hand, as shown in FIG. 8, when data is input from the data sending section (a), for example when there is key human power, only then the display data generated by the conversion logic section 2+1 is 1 and 2nd memory (22a), (
22b). The display data is stored in memory until the next data change.

The routine that generates ON, OFF, and blinking control data for the indicator lamps is executed by the operating system provided in the conversion logic section (21+) and stored in the first and second memories (21+) independently of the routine shown in FIG. 22
The data contents of a) and (22b) are rewritten. Therefore, even if the number of indicator lights to be subjected to blinking control increases, changes in display data can always be processed within a certain period of time. Therefore, it is possible to ensure the consistency of the processing time required for blinking display processing, and the time required for the original processing of the controlled part controlled by the remote controller is constant, eliminating temporal uncertainties. can. Further, by simply providing the display data control section, the third display state on the display section ti+ can be realized through constant conversion processing without causing an increase in overhead.

As described in detail, according to the configuration of the present invention, it is possible to realize the third display mode extremely easily, thereby reducing overhead. The processing time for controlling the control target is always constant, and the load on the main processing for controlling the controlled unit can be reduced.

Furthermore, in the case of the configuration shown in FIG. 5, the routine shown in FIG. 7 and the routine shown in FIG. There is no. Moreover, the first and second memories (2
2a) and (22b), the data contents of the image memory (16) can be rewritten simultaneously, and the display data from the conversion logic section 011 is directly transferred to the image memory (2) via the OR circuit (2). 16
1, it is possible to control the lighting of the indicator light at the same time as the pulse PON generated by key operation. This prevents the operator from having the illusion that input instructions are delayed.

Furthermore, as shown in FIG. 6, the blinking phase of the blinking control can be changed by simply changing the data content of the display data stored in the first and second memories (22a) and (22b). It is also extremely easy to perform reversal for each indicator light.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a display device to explain this invention, FIGS. 2 to 4 are diagrams to explain its operation, and FIG. 5 is a block diagram showing an example of a display device according to this invention. , and FIGS. 6 to 8 are diagrams for explaining the operation. tm is a display device, (II is a display part, L is a display part, (2)
1 is a source circuit, (6) is a sink circuit, 1 is a data supply section, 1 is a display data control section, 12II is a conversion logic section, (22a) and (22b) are first and second memories, (
C) is the gate section, (161 is the image memory. ``7''''# 's, i,', ;:, :) Figure 1 Figure 3 Figure 4 Figure 6 v!i

Claims (1)

[Claims] It consists of a display section that displays the status in response to key operations, a data supply section that has an image memory that supplies display data to this display section, and a display data control section that sends display data to this data supply section. , this display data control section includes a logic circuit that converts input data according to key operations etc. into display data, first and second memories that store the output of this logic circuit, and a display output from these memories. and a gate section that gates data alternately at a predetermined period, and the gated display data is supplied to the image memory, and the display data controls the lighting and blinking states of the display section. display device.