JPS6047664B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus such as an electronic computer, and particularly to an information rewriting mechanism of a storage element.

The information rewriting mechanism of such a conventional memory element will be explained with reference to FIGS. 1 and 2. Figure 1 shows 1
FIG. 2 is a circuit diagram of an information rewriting device that uses control command signals from four control command storage devices to simultaneously rewrite the storage contents of four control storage elements into information on information buses connected to the respective control storage devices; .

Such a conventional information rewriting device includes one control memory element 2, an OR gate 3, a first AND gate 4, and a second AND gate.
AND gate 5 and output line 9 as one block 1, and similar blocks 1', 1'', 1''' are arranged in parallel with block 1 on control signal lines 8 and 8'. .

In each block, one information bus 6 is connected to the input terminal of the first AND gate 4, a control signal line 8 from the control command signal terminal 10 is connected to the other input terminal, and the second N gate 5 is connected to the control signal line 8 from the control command signal terminal 10. A control signal line 8' for supplying the output of the inverter 7 is connected to one input terminal of , and the output of the control memory element 2 is connected to the other input terminal, and furthermore, the first and second AND gates 4 and 5 are connected to each other. The output of is input to the OR gate 3, and the output terminal of the OR gate 3 is connected to the input terminal of the control storage element 2. In the information rewriting device of FIG. 1 having such a configuration, when the control signal applied to the control signal input terminal 10 from the control command storage device is not output, that is, when the control signal is ``0'', the first AND The output of the gate 4 always maintains a "0" state regardless of the information on the information bus 6, and therefore the information on the information bus cannot be written into the control storage element.

On the other hand, since the control signal is inverted by the inverter 7 and '1' is generated on the control signal line 8', the output of the second 5AND gate 5 outputs information according to the memory contents of the control memory element. Therefore, since the output of the second AND gate 5 is input to the control memory element 2 via the OR gate 3, the contents stored in the control memory element 2 are retained. On the other hand, when the control signal, that is, the signal "1" is output from the control command storage device, the output of the second AND gate 5 becomes "0" regardless of the storage contents of the control storage element 2.
Since the output of the first AND gate 4 becomes equal to the information given to the information bus 6, the information on the information bus is written to the control storage element through the first AND gate 4 and the 0R gate 3. The contents are output from the output line 9.

In this manner, the information rewriting device shown in FIG. 1 can simultaneously write information on four information buses into the corresponding control storage elements using one control signal. However, when you want to change only a specific control memory element out of multiple control memory elements to the information bus content, check the contents of the control memory element that should not be changed in advance, and write the same content to the information bus. After applying the control signal to the information bus line corresponding to the control storage element, the control signal must be applied to the control signal input terminal 10 to rewrite the memory contents of the control storage element. Therefore, there are disadvantages in that the number of steps required to rewrite the stored contents not only makes the program more complicated, but also increases the processing time. In order to eliminate this inconvenience, an information processing apparatus having a configuration as shown in FIG. 2 is also commonly used.

The information processing device shown in FIG. 2 has the same configuration of each block 1, 1'', 1'', and B'' as shown in FIG. The control signal from the device is transmitted to each corresponding block 1, 1'', bi,
1″″ control signal input terminal triplet 12, 12″, 12″, 1
2""", and a control signal is applied only to the block where information is to be rewritten.

For each block 1, 1'', bi, 1'''', the control signal is connected to the control signal line 13, 13'', 13'', 13''''''
through the first AND3. The control signal applied to the gate 4 and inverted by the inverter 11,1'', 11'', 1'''' is applied to the control signal lines 14,14'', 14'',
1"" to the second AND gate. According to the information processing device having such a configuration, by inputting a control signal to a specific control 4C control signal terminal 12, 12'', 12'', 12'''', only a specific control memory element 2 corresponding to the control signal is input. The contents of the information bus 6 can be rewritten to the contents of the information bus 6, and the disadvantages of the conventional example shown in FIG.
When rewriting the contents of the control memory element 2 to the information bus 6, a control signal is independently sent to each of the nine control signal terminals 12, 12'', 12'', 1 to each control memory element.
Since the control commands must be given to 2""", a large number of control command storage devices are required.Therefore, there are disadvantages such as an increase in the size of the device and an increase in cost.The object of the present invention is to It is also possible to eliminate the drawbacks and rewrite the contents of multiple control storage elements into information bus information simultaneously with one control signal without increasing the size of the device, or to rewrite only the contents of any control storage element. An object of the present invention is to provide an information processing device that can also be rewritten.An object of the present invention is to provide a plurality of storage units, an information bus line that provides rewriting information to these units, and a system that writes information on the information bus line to all of the plurality of storage units. Is it crowded?
or means for controlling whether to write only to the selected storage section, and the control means includes a plurality of selection sections provided corresponding to the storage sections, and whether to control these individually or simultaneously. a selection signal for rewriting instructions generated individually for each storage section based on a rewriting instruction signal obtained by decoding the control command and information set in a part of the instruction code; Accordingly, there is provided an information processing device which can arbitrarily control rewriting the contents of all of the storage sections at the same time and rewriting the contents of only a selected one.

According to the present invention, it is possible to simultaneously write the contents of a plurality of information buses into a plurality of corresponding control storage elements using one control signal, or to write the contents of a specific information bus into a plurality of control storage elements. It is also possible to write to a corresponding specific control storage element.

Furthermore, since the operation can be performed with one control signal, only one control command storage device is required to provide this control signal, so the configuration is simple and the cost does not increase.Hereinafter, the present invention will be described with reference to the drawings. will be explained in more detail. FIG. 3 is a circuit diagram showing one embodiment of the information processing device according to the present invention,
FIG. 4 is an example of an instruction code in which a selection signal (hereinafter referred to as a field signal) for determining whether or not to rewrite the i-content of the control storage element with the contents of the information bus line is added in a form.

The information processing device according to this embodiment includes a first and a second AND
Gates 17, 18, inverter 21, 0R gate 19
, the information bus line 22 connected to the control memory element 20 and the single power terminal of the first AND gate 17, and the output line 25 from the control memory element! in one block 15,
Each block 15'' having the same configuration as this block 15
, 15'', 15'''' are arranged, each block 15, 1
Third AND gates 16, 16'', 16'', 16'''' are installed corresponding to the gates 5'', 152, 15''''. ,1
The output of each block 15, 15'',
15'' and 15'''' are connected to the single power terminals of the first M gates 17 and the input terminals of the inverter 21, respectively.
Further, the control signal line -25 is connected to each third terminal from the control signal command terminal 23.
The third AND gate 16,
The other input terminals 16'', 16'', 16'''' have corresponding field signal terminals 24, 24'', 2'', 2
4″″ to field signal lines 26, 26″, 26″
, 26''''. Furthermore, the configuration of each block 15, 15'', 15S, 15'''' is as follows:
The third AND gate is connected to the single-power terminal of the first AND gate 17.
The output of the gate 16 is inputted, the information bus 22 is connected to the other input terminal, the output of the inverter 21 is inputted to the single power terminal of the second M gate 18, and the other input terminal is connected to the information bus 22. The output of the memory element 20 is input.

Also, the outputs of the first and second AND gates 17 and 18 are 0R.
It is connected to a control memory element 20 via a gate 19, and the contents of the control memory element 20 are outputted from an output line 25.
According to the information processing apparatus of this embodiment configured in this manner, when the control command signal of level ゜゛1゛ is not inputted to the control command signal terminal 23 from the control command storage device, each block 15, 15'', The output level of the third AND gate 16, 16'', 16'', 16'''' corresponding to 15'', 15'''' is at 0, and as a result, the information bus 2
The output level of the second AND gate 17 is the "0" level regardless of the information content of the second AND gate 17.

On the other hand, the third AND gate 16 is
, 16'', 16'', 16'''' is inverted and input to the second AND gate 18 as the level ``゜1''. An information level equal to the memory content of the element 20 is output, and is input to the control memory element 20 through the 0R gate 19 to hold the content of each control memory element.On the other hand, a level ゜゜ is applied to the control command signal terminal 23. When a control command signal of 1'' is input, the corresponding field signal terminals 24, 24'' are input according to the instructions in fields 28, 29, 30, 31 added to the command code 27 shown in FIG. ，
Field signals from 24'', 2'''' pass through field signal lines 26, 26'', 26'', 26'''' to the third AND gate 16, 16'', 16'' connected to the block whose contents are to be rewritten. , 16'''' is inputted with a field signal of level "1".

As a result, the output of the third AND gate to which both the control signal and the field signal are input becomes the "R5 level," and the second N1 gate 1, which had previously outputted the "'r" level,
8 is set to the "0" level so that the memory contents of the control storage element 20 are not output.Furthermore, the first AND gate 1
Since the '6r1 level is added to the input terminal of 7,
This first AND gate 17 is in a state of a signal level according to the information on the information bus 22, and the content of the information bus 22 is set to 0.
It is written into the control storage element 20 through the R gate 19. On the other hand, when the control signal is ゛“1” and the field signal is “0”
A third AND gate 176,1 to which each signal of
The output pattern of 6″, 162, 16″″ becomes “0”.

Blocks 15, 15'', 15'', 15'''' connected to the third AND gate to which this level 6'0, is output
The operation is similar to that when the control signal is ゜゜0゛, and the contents of the control storage element 250 are retained. According to the information processing apparatus of this embodiment based on such an operating principle, all the field signal terminals 24, 24'' are added to the fields 28, 29, 30, 31 added to the instruction code 27 shown in FIG. , ``024'', 24'''', it is possible to simultaneously rewrite the contents of all control storage elements to the contents of the information bus.

Furthermore, by programming to output field signals only to specific fields, only the contents of the necessary control memory elements are rewritten to the information bus contents, and the contents of the remaining control memory elements remain unchanged. You can also keep it in this state. Also, since only one control command signal is required,
A low-cost and efficient information rewriting device can be provided without increasing the control command storage device. Furthermore, such an information rewriting device is particularly effective as a mechanism for temporarily storing data in the RAM in response to commands in the ROM and controlling input/output devices based on the stored contents. Although this embodiment shows an example of an information rewriting device including four control memory elements, any number of such control memory elements may be included, and the position of the field added to the instruction code is determined by the instruction code. It can be placed anywhere, such as before or after the cord.

Further, the information processing device of the present invention configures a logic circuit using two signals, a control signal and a field signal, as input signals,
Although the contents of the information bus are written into the control storage element, the configuration of such a logic circuit is not limited to this embodiment.
The effects of the present invention can also be obtained by appropriately combining logic elements so that the contents of the information bus can be written into the control storage element using at least two inputs of control signal No. 2 and field signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional information rewriting device, and FIG. 2 is a circuit diagram showing another example of the conventional information rewriting device. FIG. 3 is a circuit diagram showing an embodiment of the information rewriting device of the present invention, and FIG. 4 is a diagram showing an example of an instruction code for operating the embodiment of the present invention. 1,1″,1″
, 1''''...Logic circuit block including one control memory element, 2...Control memory element, 3...
...0R gate, 4...First AND gate, 5...Second AND gate, 6...
・Information bus, 7... Inverter, 8...
Control signal line, 9, 25... Output line of control storage element, 10... Control command signal terminal, 11, 1'', 1
1″, 1″″...Inverter, 12, 12″, 12″
, 12″″″... Control command signal terminal, 13, 1
3″, 13″, 13″″″...control signal line, 15,
15″, 15″, 15″″″...Logic circuit block including one control memory element, 16, 16″, 16″, 1
6″″″...Third AND gate, 17...
...First AND gate, 18...Second AND gate, 19...0R gate, 20...Control memory element, 21...Inverter, 22...・・・
...Information bus line, 23...Control command signal terminal, 24
, 24'', 24'', 24''''...Field signal terminal, 25...Control signal line, 26, 26'', 26
″, 26″″″...Field signal line.

Claims (1)

[Claims] 1. A plurality of storage units for storing information, an information bus line connected to each of the plurality of storage units to provide rewriting information, and an information bus line connected to each of the plurality of storage units and configured to correspond to the rewriting information. It has a plurality of first gate parts for selecting whether or not to be applied to the storage part, and a plurality of second gate parts provided corresponding to each of the plurality of first gate parts, and the second gate part is provided corresponding to each of the plurality of first gate parts. The two gate sections commonly receive a rewrite instruction signal obtained by decoding the control command, and the plurality of first gate sections
A plurality of selection signals obtained from a field section provided in a part of the instruction code are independently received so as to correspond to the gate section of the instruction code, and the rewriting instruction signal and the selection signal are used to select the plurality of storage sections. An information processing device characterized in that the information processing device is configured to instruct whether to rewrite the contents simultaneously or individually.