JPS6051142B2 - Logging error control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logging error control method that records errors when they are detected on a memory device, and in particular records errors at the same address and the same syndrome only once to prevent intermittent failures. This invention relates to a logging error control method that prevents duplicate recording, makes effective use of a limited error accumulation area, and shortens failure analysis time.

In conventional memory devices, in order to improve the reliability of read data, ECC (Error Control) is applied along with the data.
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If a bit error exists, it is corrected to provide correct data, and if a 2-bit error exists, it is detected. In the case of any of these errors, these are recorded in a logging file that records the failure status, so that they are useful for failure analysis. Then, the data corrected by the 1-bit error using ECC is written to the memory element, and the corrected data is reread and checked to see if it has been stored correctly, but the same error occurs again after this retry. If so, try writing and reading again after correcting this. If a correct reading result cannot be obtained, this retry is performed a predetermined number of times. However, the logging file records the address where the error occurred in the memory element and its syndrome, but even after retrying as described above, when the same error occurs, that is, an error with the same syndrome occurs at the same address. Even when the error occurred, all error information was recorded in the logging file. Furthermore, even if the same error that occurred earlier occurred later, the same error information was recorded in the logging file. Therefore, in conventional logging files, the same error information is written in duplicate, which poses a problem in terms of effective use of the logging file, which is limited in size.
There was a problem in that failure analysis took time because unnecessary and identical error information was entered. Therefore, an object of the present invention is to provide a logging error control method that improves these problems and prevents the same error information from being written in the logging file twice. The logging error control method according to the invention includes a processor and a memory, and corrects the error when there is a 1-bit error in the read data based on the ECC added with the data read from the memory, and also collects this error information. In the logging file method in which the data is stored in the logging file,
Provided with error information entry means for recording error information including at least the address where the error occurred, and comparison means for investigating whether data related to the 1-bit error has already been entered in the error information entry means when a 1-bit error occurs, When a 1-bit error is detected in the memory, the error information including at least the address where the error occurred is compared with the data written in the error information writing means to avoid writing the same error information twice. It is characterized by

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 is a flowchart explaining its operating state.

In the figure, 1 is a memory, 2 is a memory access control unit, 3 is a processor, and 4 is a local storage.

The memory 1 stores various data necessary for data processing together with ECC.

The memory access control unit 2 controls access to the memory 1 according to instructions from the processor 3, and
A first false information storage address register (FSAR) 2-1 that stores a 1-bit error detection address and a syndrome holding register 2-2 are provided, and are used to check whether or not there is an error in data read from the memory 1. , and 1
It has a function to correct bit errors in the case of bit errors. The processor 3 is provided with a second erroneous information storage address register 3-1, which not only generates a control command to the memory access control unit 2 but also detects the existence of an error in the data read from the memory 1 by the memory access control unit. 2, the address where this error occurred is written in the second erroneous information storage address register 3-1, and whether or not the address has ever caused an error is written in the local storage 4. Research based on data.

If an error has already occurred at the same address, the syndromes are compared to detect whether the newly occurring error is the same as the error that occurred in the past. . In the local storage 4, addresses and syndromes of error information that has occurred in the memory 1 and are stored in the logging file are written. Next, the present invention will be explained based on FIG. 1 while referring to the flow chart of FIG.

(1) When data is first read from the memory 1, the memory access control unit 2 detects whether there is an error in the data.

Then, the existence of an error is detected, and if it is a 1-bit error, its address is written in the first erroneous information storage address register 2-1, and its syndrome is written in the syndrome holding register 2-2. At the same time, these error data are also temporarily written in the logging file area in the memory 1 and then stored back. This address and syndrome are also written in the local storage 4 held by the processor 3. Then, the memory access control unit 2 corrects the data in which the 1-bit error occurred based on the address written in the first erroneous information storage address register 2-1 and the syndrome written in the syndrome holding register 2-2. Then, it is stored in the memory 1 again. (
2) Thereafter, when a 1-bit error is detected in the data read from the memory 1, the address where the error occurred is stored in the second erroneous information storage address register 3- of the processor 3.
1 and compare it with the address written in the local storage 4 due to an error occurring in the past.

At this time, if there is an error with the same address, then the syndromes are compared to detect whether the newly occurring error has the same contents as the error that occurred in the past. If the resulting syndromes also match, the newly generated error is the same as the error already stored in the logging file, so the so-called exit processing is performed so that it is not written to the logging file or local storage again. Let's do it. However, if the addresses match but the syndromes differ, this is different error information, so the addresses and syndromes are stored in the logging file and written in the local storage 4. After correcting the 1-bit error using this address and syndrome, correct data is written into memory 1. (3) However, in (2) above, the error that occurred in memory 1 does not match the address in the error information written in local storage 4, and if the error occurs at a new address, the following (
The fixed burst error check described in 4) is performed to identify whether or not it is a fixed failure.

(4) In other words, as in (3) above, when an error occurs at a new address, in order to investigate the state of the data stored in the addresses before and after that address, The bits are sequentially inverted and the data and syndromes in a certain range before and after are checked.

If all the checked items show errors with the same syndrome, this indicates that a fixed failure has occurred, so this is stored in the Machine Check Interruption Code (MCIC) area of the logging file. register. At this time, if an error occurs with the same syndrome for some items, this is also MC.
Register in the IC area. (5) However, when the fixed burst error check is completed with the result that no error has occurred in other addresses or that an error has occurred in another syndrome, this is a hard error. It is assumed that it is not,
The processor 3 instructs the memory access control unit 2 to correct the detected one-bit error.

Based on this, the memory access control unit 2 reads the data from the memory 1 again using the address written in the first erroneous information storage address register 2-1, performs 1-bit correction, and then transfers the data to the memory 1. write to. Then read this rewritten data, and if there is no error, 1
Since the bit error has been corrected, exit processing will be performed. (6) However, if the same error exists when the rewritten data is read, a retry is performed to correct this error and rewrite again.

If an error still exists even after performing such retries a specified number of times, write this address and syndrome in the local storage 4, and also write the address and syndrome in the logging file M.
This will be registered in the CIC area. Therefore,
According to the present invention, when a 1-bit error is detected in memory, a syndrome code that analyzes the error occurrence address and error bit stored in hardware determines that a continuous fixed bit error has occurred at the address and bit. After confirming that there is no error, write correction data to the bit.

After this, the data at the relevant address is read and it is detected whether the state is the same as when the error was detected. If the state is not the same, the error that occurred in the relevant bit is an intermittent fault, so it is treated as a soft error. shall be excluded from the scope of
Of course, if there is an error when corrected data is written and read, a retry will be performed, but the address and syndrome will not be stored in the logging file each time the retry is made, as is the case with conventional methods. After retrying, if the same error exists, the error information is displayed only once. Therefore, it prevents the contents of intermittent failures (soft errors) from being stored in the error accumulation area held by the operating system, and also prevents the same error information from being recorded redundantly. It is possible to effectively utilize the error accumulation area that has been created, and furthermore, it is possible to shorten the failure analysis time.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 is a flowchart explaining its operating state. In the figure, 1 is a memory, 2 is a memory access control unit, 3 is a processor, and 4 is a local storage.

Claims (1)

[Claims] 1 includes a processor and a memory, and has an ECC (Error Corr) attached to the data read from the memory.
In a logging file method in which if there is a 1-bit error in the read data based on the read data, the error is corrected and this error information is stored in the logging file, error information that includes at least the address where the error occurred. and a comparison means for checking whether data related to the 1-bit error has already been written in the error information entry means when a 1-bit error is detected in the memory. A logging error control method characterized in that error information including the address where the error occurred is compared with data written in the error information entry means to prevent the same error information from being written twice.