JPS6029097A - Picture information extract system - Google Patents

Abstract

PURPOSE:To set the access to high speed by setting the picture memory to the two-dimensional address system and simultaneously multi-processing the memory in accordance with the number of picture element to be read. CONSTITUTION:A picture memory 1, horizontal direction address X-ADDRESS assignment circuit 3, vertical direction address Y-ADDRESS assignment circuit 32 and parallel processing circuit 4 are installed. And, when the co-ordinate of the fixed picture element P5 in the memory 1 is assigned by the X-Y address, the picture data P1 - P9 located at the local plane of the 3X3 picture element nearby are latched from the memory 1 and is removed through a parallel processing circuit 4 in a simultaneous and parallel way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an image processing device for processing captured images obtained through a horizontal and vertical scanning type imaging device such as an industrial television camera (ITV) camera, and in particular to The present invention relates to an image information extraction system that extracts desired image information. Generally, in this type of image processing device, in order to process captured images at high speed, it is desirable to be able to process them in parallel on a two-dimensional plane.

[Prior art and its problems]

Figure 1 is a conceptual diagram showing a parallel processing system for a portion (local) of an image, and Figure 2 is a schematic diagram showing a specific example thereof.

What is shown in FIG. 1 is a local region (x, y) including the pixel of interest P (
In other words, images of 3×3 pixels are sequentially taken out by the scanning circuit 3, and the images are subjected to parallel arithmetic processing by the parallel processing circuit 4, and these are used as pixels P(x, y) of the output image 2.

As a specific example of this type of memory, the one shown in FIG. 2 is known. In the figure, 1 is, for example,
An image memory similar to that shown in Fig. 1 consists of 256 horizontal pixels x 256 vertical pixels, 4 is a parallel processing circuit, and 5 is a shift register that circulates with the number of pixels (256) obtained from one horizontal scanning line. A local memory is configured by stacking a predetermined number of stages in a spiral shape, and for example, when extracting a local area of 3×3 pixels, it is configured with three stages. Therefore, for example 6
When the image memory 1 is sequentially addressed using the MHz basic clock, the contents of the memory 1 (bits, 1 pattern)
are taken out in chronological order and sent to the local memory 5. As a result, images for three horizontal scans of the image memory 1 are sequentially shifted and imported into the local memory 5, and an observation area (window) with a size of 3 x 3 is created for this. By setting the parallel processing circuit 4
Desired local regions can be extracted in parallel via .

However, in such a system, the scanning direction must be fixed in one dimension (() and the bit pattern must be sent serially to the shift register, similar to the scanning of a television camera, and therefore the two-dimensional local memory 5 will be accessed serially, it is possible to instantly retrieve any local area of the screen memory l, that is,
This has the disadvantage that a desired area cannot be retrieved by random access.

[Purpose of the invention]

The present invention has been made in view of these points, and provides an image information extraction system that can freely extract a predetermined local area including a desired point by addressing the point, that is, in a random access method. The purpose is to

[Key points of the invention]

The key point is that multiple two-dimensional image memories that binarize and store images obtained through two-dimensional scanning imaging devices are installed in parallel, and the horizontal address for these memories is given in common to all memories. On the other hand, an address designation circuit that designates vertical addresses differently for each memory with a predetermined relationship, and a latch circuit that latches the contents read from each memory based on the designated address are provided. Embodiment of the Invention FIG. 3 is a conceptual diagram illustrating an embodiment of the invention. FIG. 4 is a schematic diagram for explaining the present invention; FIG.
Figures A to 40 are detailed configuration diagrams showing the details of each part of Figure 4, and Figure 5 is a waveform diagram of each part for explaining the read operation.

As schematically shown in FIG. It is composed of a vertical address (Y-ADDRESS) designation circuit 32, a parallel processing circuit 4, etc., and when the coordinates of the pixel of interest P5 in the memory 1 are designated by the X-X address from the address designation circuit 3t32, 3x3 pixel local plane @image data P1
-P9 are simultaneously processed in parallel via the parallel processing circuit 4.

Hereinafter, a detailed explanation will be given with reference to Nos. 4, 4A to 4C and FIG. 5.

In the stripe 4 diagram, 1 (11 to 13) is the 1st or 2nd diagram.
Image memory similar to the figure, 10 is a timing generation circuit, 1
1 (Ill~Ig) #13 (131~13
3) is an adder/subtractor, 12 is a selector, 14 (141 to 14
3) is a latch circuit. Note that X is the horizontal coordinate (
X address), Y is the vertical coordinate (X address), α
is an offset indicating the amount of deviation from the X address, and β is an offset indicating the amount of deviation from the X address. As shown in detail in FIG. 4A, the timing circuit 10 includes an oscillator 1 that generates a clock signal CKO of a predetermined frequency.
01, a counter 10 that divides the frequency of the clock signal CKo and outputs predetermined pulse signals CKI, CN3, CN3;
2 and various gates.

The X address generation circuit, as also shown in FIG. 4A, consists of an adder/subtractor 11 and two selectors 121 and 122 (in FIG. 4, these are shown together as one). receives the output from the counter 102 and selects one of the outputs of the adders/subtractors 111 to 113, and the selector 122 selects either the output from the selector 12 or the X address X1n (receiving the read signal , select the output of selector 121).

Note that the adder/subtractor 11 changes the X address designation n by the offset α. For example, if α=0, the horizontal addresses X1n-1, X1r1, and Xin+1 are changed to each adder/subtractor 11. , 112 and 113, respectively. Further, the Y address generation circuit includes an adder/subtractor 13 and a selector 15, as shown in FIG. 4B.
(151-153), selectors 151-15
3 is the Y address η. and each adder/subtractor 131 e 132
This selects either the output from g133,
When receiving the read signal RD, the output from the adder/subtractor 13 is selected. Note that the selector shown in FIG. 4B is
It is omitted in FIG. The readout circuits (bit pattern output circuits) of the image memories 11 to 13 receive latch pulses CK1 to CK3 as shown in FIG. 4C.
It consists of a latch circuit 14 that latches the bit output from lJ1, and a gate 16 that receives the read pulse RD and outputs the latched bit data.

The operation will be described below with reference to these drawings.

a) When writing image data to the image memory In this case, the image memory chip select signal C81 shown in FIG. 4A
Write mode signal WE and write signal (write pulse)
Since WT etc. are valid, the image data DATA is game)
G to each of the memories 11 to 13 in FIG. 4C. At this time, both the xgY addresses are addresses that are unrelated to the offset, and the data DATA is commonly given to each memory 11 to 13, so the predetermined Image data will be stored in the three memories 11-13 in exactly the same way. Note that the number N of memories 1 installed is determined by the number N of pixels to be read out at one time.
What is the purpose of reading out ×3 pixels? At this time, the offset α,
Both β are chosen to be zero.

b) When continuously outputting data from the image memory In this case, the fourth
When the image memory chip select signal C8, readout signal RD, etc. in the figure become valid, the oscillation circuit 101 shown in FIG. 4A generates a clock signal CKQ as shown in FIG. . The counter 102 receives this clock signal CKO as shown in FIG.
, (ho).

Since the frequency is divided as shown in (E) and (G), by performing the prescribed logic processing using AND gates AN1 to AN3 (see Fig. 4), (E), (S), and (TO) in Fig. The latch pulses CKI, CK2 and CN3 can be obtained as follows. Note that counter outputs QB and QC are selector 1.
21 as signals AO and AI (see FIG. 5(C)), thereby causing the horizontal addresses X-1, X and X+1 to be outputted sequentially in a time-division manner. On the other hand, as the Y address, the output from the adder/subtractor 13 is selected depending on the read signal (see Figure 4B).
, every time the X address is specified, yl(Y-1), Y
2 (Y) and Y3 (Y+1) are output, Yl is sent to memory 11, Y2 is sent to memory 12, and Y3 is sent to memory 1.
3 each. Therefore, the coordinates of the center pixel P5 (see FIG. 3) of the 3×3 two-dimensional local area are X.

If it is Y, first, the Y1 address of the memory 11, the Y2 address of the memory 12, and the Y3 address of the memory 13 are each specified simultaneously by the horizontal address X-1, and thereafter addresses are specified in the same manner. Here, horizontal addresses X-1, X, and X+1 are latch pulses CKI,
Since it is generated in synchronization with CR2 and CN3, address
-1, the contents latched by the latch circuit 14 are Pi
, P4. P7, and the address spaces are P2, P5,
P8, and at address X+1 P3, P6
, P9. Note that P1 to P9 correspond to each pixel shown in Figure 3. The pixel data P1 to P9 thus latched are taken out via the gate 16 opened by the read signal RD. In addition, some of these P1 to P3 are 5 figures (4).

υ), (6).

In the above, for convenience of explanation, the offsets α and β are α=β=0
However, this is because the local plane to be read out is limited to 3×3 pixels, and generally 1αl=lβl=2,3
......, the local area is 5X5
, 7X7, 9X9, and so on. Note that the number is not limited to an odd number, and can be set arbitrarily.

FIG. 6(A) is an explanatory diagram showing an example of expanding such a local area to 9×9M elements, and FIG. 6(B) is an explanatory diagram showing an example of setting values of offset addresses α and β at that time. be. Since there is no need to explain these, I will omit them.

〔Effect of the invention〕

As described above, according to the present invention, the image memory is made into a two-dimensional address format (random access format) and multiplexed according to the number of pixels to be read out at the same time, so high-speed access is possible. Become. For example, 3X3
In order to extract 3 pieces of image data of a local plane, 3 pieces of image data are required in the horizontal direction.
Therefore, the number of accesses can be reduced to 3/3'' = 1/3 compared to a device with only one image memory, and in general, nl data can be shortened to 1/n. This means that if the basic clock frequency shown in FIG.
) indicates that parallel reading is possible. Furthermore, since the present invention introduces the concept of an offset address, it has the advantage that it becomes easy to expand or reduce a local area.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram showing the general structure of an image parallel processing system, Figure 2 is a schematic diagram showing a specific example of Figure 1, and Figure 3 is a schematic diagram showing a specific example of Figure 1.
The figure is a schematic diagram for conceptually explaining this invention, FIG. 4 is a configuration diagram showing an embodiment of this invention, and FIGS. 4A to 4C are essential configuration diagrams showing each part of FIG. 4 in more detail. FIG. 5 is a timing waveform diagram particularly for explaining the memory read operation.
FIG. 6 is an explanatory diagram for explaining a method of enlarging a local area. Code explanation 1 (11-13)... Image memory, 2...
...Output image, 3...Scanning circuit, 31...
...Horizontal addressing circuit, 32... Vertical addressing circuit, 4... Parallel processing circuit, 5...
... Two-dimensional local memory, 10 ... Timing generation circuit, 11 (11, ~ 11a) t 13 (13
1 to 133)...Adder/subtractor, 12(121s1
22L15 (15, ~ 153)...Selector,
14 (14s~143)...Latch circuit, 1
6. G, ANI~AN3...Gate agent Patent attorney Akio Namiki Agent Patent attorney Kiyoshi Matsuzaki Gem 3 Figure 1 Figure 2 Figure 4 1 Figure 4A Figure 48 Figure 51A Figure 6 (A) (B)

Claims (1)

[Claims] A plurality of two-dimensional image memories each storing image information of a predetermined object obtained through a horizontal and vertical scanning type imaging device in the same manner, and a horizontal address of the memory is given in common to all the memories. On the other hand, the vertical address is specified by an address designation circuit that differs from each other in a predetermined relationship for each memory, and a latch circuit that latches the contents read from each memory based on the address specified by the designation circuit. 1. An image information extraction system characterized in that a plurality of pieces of image information are simultaneously extracted from a predetermined number of positions in the vicinity of the predetermined location including the predetermined location by addressing a predetermined location in a predetermined memory.