JPH0750504B2 - Pattern recognition device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern recognition device used for pattern defect inspection of printed wiring boards, IC mask patterns, lead frames and the like.

(Conventional technology and its problems) CC as a pattern recognition device that can recognize various patterns
Although a device combining an input system such as a D licensor and a computer has been developed, it is the current situation that it is difficult to increase the speed because there are many parts that depend on software. On the other hand, a pattern recognition device has been developed which is capable of recognizing various patterns at high speed by using hardware. However, in this type of device, a dedicated hardware that can detect each feature according to various patterns is developed. They have had the problem of requiring ware and, in addition, usually require a huge amount of processing circuits as the number of feature points to be recognized increases.

FIG. 21 is a circuit diagram of a conventional pattern recognition device. Here, for convenience of explanation, a pattern recognition circuit having a size of 5 × 5 pixels will be described, but theoretically any size is possible.

The inspection pattern corresponding to the inspection object 1 is a licensor,
Input with the input device 2 such as area sensor or TV camera,
It is assumed that the image data is binarized by the next binarization circuit 3. Here, for the sake of explanation, it is assumed that a 2048 pixel CCD licensor is used as the input device 2, and every time one line is scanned in the main scanning direction X by this CCD licensor.
The inspection object 1 is moved by one pixel in the sub-scanning direction Y,
Image data of the entire surface of the inspection object can be obtained.

In the binarized image data 3, the binarization circuit is sequentially latched in the flip-flop 214 (the highest column of the flip-flops 214) according to the pixel clock pulse sent from the pixel clock generator 4. On the other hand, a 2048-bit line shift register L
_The image data delayed by one scanning pixel (2048 pixels) by ₁₁ is latched in (the second column of) the flip-flop 214. Similarly, the image data delayed by 2 scans by the 2048-bit line shift register L ₁₂ is latched in the flip-flop 214 (the third column of the same), and is scanned by the 2048-bit line shift register L _{13 for} 3 scans. The image data delayed only by the flip-flop 214
The image data latched in (the fourth column of) and delayed by 4 scans by the 2048-bit line shift register L ₁₄ is latched in (the bottom column of) the flip-flop 214. In this way, the image data of 5 × 5 pixels appears in the flip-flop 214 in the main and sub-scanning directions sequentially for each pixel clock pulse.

The image data for this 5 × 5 pixels is processed by the exclusive OR circuit 215.
Is applied to one input terminal of each corresponding pixel.

The memory 205 stores the reference pattern 5 × 5 pixels to be recognized, and these data are given to the other input terminal of each corresponding pixel of the exclusive OR circuit 215.

The exclusive OR circuit 215 outputs a signal of "0" when the pixels are matched for each corresponding 5 × 5 pixel, or a signal of "1" when the pixels are not matched.

The memory 207 stores masking data for masking the inspection result of the area, if there is an unnecessary area in the area to be detected (here, 5 × 5 pixels). This masking data is given to one input terminal of each corresponding pixel of the AND circuit 216. AND circuit
Since the output signal of the exclusive OR circuit 215 is input to the corresponding input pixel of each pixel in the other input terminal of 216, when "0" is input to any of the AND circuits 216 as masking data. Even when the output signal of the corresponding exclusive OR circuit 215 is "1" (when they do not match), the output from the AND circuit is "0". This means that the pixel is masked.

Each output of the logical product circuit 216 is input to the logical sum circuit 208,
If the output is "0", it is recognized that the patterns match, and if the output is "1", it is recognized that the patterns do not match. (For example, Japanese Patent Publication 60-2718
FIG. 35 of Japanese Patent Laid-Open No. 5) Although the above-mentioned conventional example has been described with 5 × 5 pixels, in order to actually recognize the pattern, it is necessary to perform with, for example, about 256 × 256 pixels. However, the flip-flop 214 in FIG. 21,
In order to specifically realize the circuits of the exclusive OR circuit 215 and the AND circuit 216, a two-dimensional number is required, which is an enormous circuit.

(Object of the Invention) The present invention has been made to solve the above problems, and an object of the present invention is to provide a pattern recognition device that can recognize various patterns at high speed with a simple circuit configuration.

(Means for Achieving the Purpose) The present invention provides (a) a clock signal generating means for generating a clock signal, and (b) the object to be inspected transmitted in time series along the main scanning direction of the object to be inspected. Of the binary image data of the inspection object, the binary image data of m pixels (m is an integer of 2 or more) in the same column in the sub-scanning direction orthogonal to the main scanning direction,
A first latch circuit for latching in synchronization with the clock signal; and (c) a predetermined binary value of the m-pixel binary image data of the binary image data of the inspection object. Binary image data for k pixels preceding the binarized image data in time series in the main scanning direction (k is an integer of 1 or more)
A second latch circuit for latching in synchronization with the clock signal, and (d) m having m pixels in the sub-scanning direction and n pixels (n is an integer of 2 or more) in the main scanning direction.
The binary image data of the reference pattern of × n pixels is associated with each value of the first address data that specifies the storage location of each of the binary image data of m pixels in each sub-scanning direction. One reference data group is stored, and in the first reference data group, a binarized image for n pixels in the main scanning direction corresponding to a scanning line to which the binarized image data for k pixels belongs. The data is stored as the second reference data group in association with the value of the second address data that specifies the storage location of the binarized image data for the n pixels.
Further, the first and second address data are signals that also specify a storage location of data indicating which of the first and second latch circuits is specified corresponding to the binarized image data specified by each. A memory for storing, as selector switching data, data designating one of the first and second latch circuits in association with each value of the first and second address data. When a first reference data group of m pixels in the sub-scanning direction corresponding to the value of the first address data and the selector switching data are read in response to the input of one address data to the memory, and , Corresponding to the second address data according to the input of the second address data to the memory,
When the second reference data group and the selector switching data are read, the memory outputs the read first or second reference data group and the selector switching data in synchronization with the clock signal. And (e) a selector that outputs one of the binary image data for the m pixels and the k pixels output by the first and second latch circuits, respectively, according to the selector switching data output from the memory. And (f) comparing the first or second reference data group selectively called from the memory with the output of the selector for each corresponding pixel, and outputting a coincidence signal when all the pixels coincide with each other. On the other hand, a comparison circuit that outputs a non-coincidence signal when at least one set of pixels do not coincide with each other, and (g) a value corresponding to the second address data is preset data. When the coincidence signal is input from the comparison circuit, the count value is incremented in synchronization with the clock signal and the incremented count value is stored in the memory as the first address data. When the non-coincidence signal is output, the count value is preset in synchronization with the clock signal and the preset data is output as the second address data, while the count value is stepped continuously n times. In this case, a counter circuit for presetting the count value and outputting a pattern matching detection signal in synchronization with the next clock signal is further provided.

(Embodiment) FIG. 1 (a) is a circuit diagram of a pattern recognition apparatus according to an embodiment of the present invention. Here, for convenience of explanation, 5 × 5
Although described as a pixel size pattern recognition circuit, theoretically any size is possible.

The inspection pattern corresponding to the inspection object 1 is input by the input device 2 such as a line sensor, an area sensor, or a TV camera, and its image data is binarized by the following binarization circuit 3. . Here, for the sake of explanation, the input device 2 is 20
Assuming a 48-pixel CCD licensor, the inspected object 1 is moved in the sub-scanning direction Y by 1 pixel each time one line is scanned in the main scanning direction X by this CCD licensor, and the inspected object is inspected. Image data of the entire surface shall be obtained.

The image data binarized by the binarization circuit 3 is sequentially latched by the flip-flop P ₁ in accordance with the pixel clock pulse sent from the pixel clock generator 4.
On the other hand, the 2043-bit line shift register L ₁ and the flip-flops P _{6 to} P _{10 for} 5 pixels make one scan pixel (204
The image data delayed by 8 pixels) is latched by the flip-flop P ₂ . Similarly, 2043 bit line shift register L ₂ and 5 pixel flip-flop
Image data delayed by 2 scans by P _{11 to} P ₁₅ is latched in the flip-flop P ₃ , and image data delayed by 3 scans by the 2043-bit line shift register L ₃ and flip-flops P _{16 to} P _20. Is latched by the flip-flop P ₄ , and the image data delayed by 4 scans by the 2048-bit line shift register L ₄ is latched by the flip-flop P ₅ . Thus, the flip-flop P ₁ ~
In P ₅ , image data for 5 pixels in the same column in the sub-scanning direction sequentially appears for each pixel clock pulse. Further, in the flip-flops P _{6 to} P ₁₀ , the image data latched by the flip-flop P ₂ appears 1 to 5 pixels before in the time series direction (main scanning direction). Similarly, flip-flop P
Image data of 1 to 5 pixels before the image data latched by the flip-flop P ₃ in the time series direction appears in _{11 to} P ₁₅ , and in the flip-flop P ₄ in flip-flops P _{16 to} P _20. Image data of 1 to 5 pixels before the latched image data in the time series direction appears.

The memory 5 has a main scanning for preliminarily checking the matching of the first reference image data group of 5 pixels × 5 in the same column in the sub-scanning direction showing the reference pattern to be recognized and the pattern in the time series direction. A second reference image data group of 1-5 pixels before in the direction and selector switching data are stored. The memory 5 outputs the selector switching data from the output terminals D ₅ and D ₆ to the selector ₆ based on the address signal given to the input terminals A _{3 to} A ₀ , and outputs the selector switching data from the output terminals D _{4 to} D ₀ . The second reference image data group or the first reference image data group is output to one of the input terminals of the exclusive OR circuits XOR1 to XOR5. These outputs are performed at the rising edge of the pixel clock pulse (details of which will be described later).

The selector 6, based on the selector switching data output from the memory 5, flip-flops (P _{1 to} P ₅ ), (P ₆ to
Image data of 5 pixels of any one of P ₁₀ ), (P _{11 to} P ₁₅ ), and (P _{16 to} P ₂₀ ) is selectively input to the other input terminal of the exclusive OR circuits XOR1 to XOR5. In this way, in the exclusive OR circuits XOR1 to XOR5, the image data of corresponding pixels are compared with each other, and if they are different from each other, "1" is output.

In the memory 7, if there is an area that does not require inspection in the area to be detected (here, 5 pixels × 5 pixels), masking data for masking the inspection result of the area is stored. This masking data is stored in the input terminal A ₃ of the memory 7.
Based on the address signal given to ~ A ₀ , AND circuit
It is given to one input terminal of AND1 to AND5. AND circuit
Since the output signals of the exclusive OR circuits XOR1 to XOR5 are input to the other input terminals of AND1 to AND5, “0” is masked data as one of the AND circuits AND1 to AND5.
Input to the corresponding exclusive OR circuit XOR1 to XOR5
Even if the output signal of is "1" (in the case of non-coincidence), the output from the AND circuit becomes "0" (the details will be described later).

The outputs of the AND circuits AND1 to AND5 are input to the OR circuit 8, and the NOR circuit 9 outputs the borrow signal and NOR of the counter 10 from the output of the OR circuit 8 to the load terminal of the counter 10. Is entered. The counter 10 may be an addition counter or a subtraction counter, but here, for convenience of explanation, it is a subtraction counter, and the value "5" is set as the preset data.
Shall be loaded. Also, this counter 10
The counter is a synchronous type, and each function is executed at the falling edge of the pixel clock pulse. In addition, this counter
The data corresponding to the count value of 10 is input to the input terminals of the memories 5 and 7 as address data. Further, the borrow signal of the counter 10 is inverted by the inverter 11 and input to the monostable oscillator 12, and the monostable oscillator 12 outputs a pattern matching detection pulse when the borrow signal falls.

<Operation Example 1><Pattern Example 1> The operation of the pattern recognition apparatus will be described below with reference to the time chart shown in FIG. 5 by taking a specific pattern as an example. First, it is assumed that the memory 5 stores the memory data shown in FIG. in this case,
The data (D _{0 to} D ₄ ) corresponding to the addresses “0” to “4” (first address data) indicates the pattern data (that is, the first reference image data group) to be recognized, and the address “5” (the first reference image data group). Data (D ₀ ~) corresponding to 2 address data
D ₄ ) indicates a second reference image data group for precedingly checking the matching of the patterns in the time series direction, and the addresses "0" to
The data (D ₅ , D ₆ ) corresponding to “5” indicates the selector switching data. The second reference image data group is the first reference image data group.
Image data of the main scanning direction column (here, addresses “0” to “4”) corresponding to the flip-flops (here, flip-flops P _{11 to} P ₁₅ ) selected by the selector switching data among the reference image data group The image data is the same as the data D ₂ ). In the figure, the shaded area is "0".
, And the blank area represents “1”. Further, the table below shows a truth table of the selector 6.

Now, it is assumed that there is a pattern as shown in FIG. 3 on the surface 1 to be inspected. In addition, all “1” is stored in the memory 7.
Is written.

At time t _n-2 in FIG. 3, the flip-flop is
The pattern of FIG. 4A is input to P _{1 to} P ₅ . Further, the flip-flop P ₆ to P ₁₀ and P ₁₆ to P ₂₀ is input pattern of FIG. 4 (g), the flip-flop P ₁₁ to P ₁₅ are input pattern of FIG. 4 (h) There is. At this time, the counter 10, since it is preset to a value "5" by the load signal, from the memory 5 data of the address "5" is called, the selector 6 to select the flip-flop P ₁₁ to P _15. As a result, one input terminal of the exclusive OR circuit XOR1～XOR5, the input data of FIG. 4 which is latched by the flip-flop P ₁₁ ~P ₁₅ (h) is, to the other input terminal a 2, the reference image data group, that is, the data (D _{4 to} D ₀ ) at the address “5” shown in FIG. 2 is input, and “1” is output from the exclusive OR circuit XOR1. As a result, "1" is also output from the OR circuit 8, the counter 10 is loaded, and the counter value is continuously preset to "5" at the falling edge of the pixel clock pulse.

Then, when the time t _n-1 is reached, the flip-flops P _{1 to} P ₅
Is also pattern input of FIG. 4 (a), the pattern of the FIG. 4 (i) is input to the flip-flop P ₁₁ to P _15. At this time, since the counter 10 is preset to a value "5" as already mentioned, the selector 6 will continue to select the flip-flop P ₁₁ to P _15, the exclusive OR circuit XOR1～XOR5, flip-flop The data of FIG. 4 (i) latched by P _{11 to} P ₁₅ and the second reference image data group, that is, the data (D _{4 to} D ₀ ) of the address “5” shown in FIG. 2 are input. , The patterns match, so that all the exclusive OR circuits XOR1 to XOR5 output "0". As a result, the output of the OR circuit 8 becomes "0", the load of the counter 10 becomes "1", the counter 10 at the falling edge of the pixel clock pulses are subtracted, the address from the output terminal Q _a to Q _d " 4 ”is output.

After that, when the time t _n is reached, the next pattern, that is, the pattern of FIG. 4B is latched in the flip-flops P _{1 to} P ₅ at the rising edge of the pixel clock pulse. In addition, the data (D ₆ ...) of the address "4" shown in FIG.
D ₀ ) is called and the data D ₆ and D ₅ are “0” and “0”, the selector 6 switches from the flip-flops P _{11 to} P ₁₅ to the flip-flops P _{1 to} P ₅ , and the exclusive logic Sum circuit XO
The data of FIG. 4 (b) latched by the flip-flops P _{1 to} P ₅ and the data (D _{4 to} D ₀ ) of the address “4” shown in FIG. 2 are input to R1 to XOR5. . Again, since both patterns match, all exclusive OR circuits XO
"0" is output from R1 to XOR5, and the logical sum circuit 8 is "0".
The counter 10 is loaded with "1" and the counter 10 is decremented at the falling edge of the pixel clock pulse to output the address data "3".

Similarly, at the rising edge of the pixel clock pulse at time t _{n + 1} , the flip-flops P _{1 to} P ₅ latch the pattern shown in FIG. 4C, and the memory 5 stores the address “3” shown in FIG. Data (D _{6 to} D ₀ ) is called, the selector 6 continues to select the flip-flops P _{1 to} P ₅ , and the exclusive OR circuits XOR1 to XOR5 are shown in FIG. 4 (c).
Data and the data at address "3" (D ₄
To D ₀ ) are input, all of their outputs become “0”, the output of the logical sum circuit 8 is “0”, the load of the counter 10 is “1”, and the counter 10 has a falling edge of the pixel clock pulse. The subtraction is performed and the address data "2" is output.

At the next rising edge of the pixel clock pulse at time t _{n + 2} , the flip-flops P _{1 to} P ₅ latch the pattern of FIG. 4 (d), and the memory 5 stores the data of the address “2” shown in FIG. (D _{6 to} D ₀ ) is called, the selector 6 continues to select the flip-flops P _{1 to} P ₅ , and the exclusive OR circuits XOR ₁ to XOR ₅ store the data of FIG. 4 (d),
The data (D _{4 to} D ₀ ) at the address “2” shown in FIG. 2 is input, all the outputs become “0”, the output of the OR circuit 8 becomes “0”, and the load of the counter 10 becomes “0”. At "1", the counter 10 is decremented at the falling edge of the pixel clock pulse, and the address data "1" is output.

At the next rise time of the pixel clock pulse at time t _{n + 3,} the pattern of FIG. 4 (e) is latched in the flip-flops P _{1 to} P ₅ , and the memory 5 stores the address “1” shown in FIG. The data (D _{6 to} D ₀ ) is called, and the selector 6 continues to select the flip-flops P _{1 to} P ₅ ,
Data of FIG. 4 (e) to the exclusive OR circuit XOR1～XOR5, data at address "1" shown in FIG. 2 (D ₄ to D ₀₎ is input, all of their outputs "0" And the logical sum circuit 8 outputs "0". At this point, the load signal of the counter 10 is "1", but the counter 10 is decremented by the falling edge of the next pixel clock pulse, "0" is output as address data, and the borrow signal is "1". Then, the load signal becomes "0" by the NOR circuit 9.
Switch to.

At the next rising edge of the pixel clock pulse at time t _{n + 4} , the flip-flops P _{1 to} P ₅ latch the pattern of FIG. 4 (f), and the memory 5 stores the address “0” shown in FIG. Data (D _{6 to} D ₀ ) is called, the selector 6 continues to select the flip-flops P _{1 to} P ₅ , and the exclusive OR circuits XOR ₁ to XOR ₅ and the data of FIG. data at address "0" as shown in FIG. (D ₄ to D ₀₎
Are input, all the outputs become “0”, and the logical sum circuit 8 outputs “0”. At this point in time, the borrow signal of the counter 10 is "1", so that the NOR circuit 9 keeps the load signal at "0", but when the next pixel clock pulse falls, the counter 10 has the value "5". "is preset, from the output terminal Q _a to Q _d address data" 5 "is output. At the same time, the borrow signal switches from "1" to "0". This borrow signal is inverted by the inverter 11 and input to the clock terminal of the monostable oscillator 12. At this time, at the clock terminal of the monostable oscillator 12, the output signal “0” of the logical sum circuit 8 is fed to the inverter.
Since the "1" signal inverted by 13 is input,
Clearing of monostable oscillator 12 has been released, and output terminal Q
Outputs a pattern matching detection pulse.

At the next rise time of the pixel clock pulse at the time t _{n + 5} , the flip-flops P _{1 to} P ₅ latch the pattern of FIG.
Pattern of FIG. 4 (j) is latched in the ₁₁ to P _15. Further, the data (D _{6 to} D ₀ ) at the address “5” is called from the memory 5, the selector 6 switches from the flip-flops P _{1 to} P ₅ to the flip-flops P _{11 to} P ₁₅ , and the exclusive OR operation is performed. The data of FIG. 4 (j) latched by the flip-flops P _{11 to} P ₁₅ and the data (D _{4 to} D ₀ ) of the address “5” shown in FIG. 2 are input to the circuits XOR1 to XOR5. It Since these data do not match, the logical sum circuit 8 outputs "1". As a result, the load signal of the counter 10 is switched from "1" to "0", the value "5" is preset in the counter 10 at the falling edge of the pixel clock pulse, and the address data "5" is output.

In this way, when the image data latched in time series in the flip-flops P _{1 to} P ₅ and the first reference image data (5 × 5 pixels) stored in the memory 5 all match Since a pulse is generated from the monostable oscillator 12, the pulse can be used as a pattern detection signal.

<Operation Example 2> Next, in the pattern recognition apparatus, the operation when there is a mismatch between the pattern to be inspected and the reference pattern (first reference image data) will be described by taking the pattern to be inspected in FIG. 6 as an example. explain. Until the time t _n-2 ~t _n, but the same operation as the case of the test pattern shown in Figure 3 is carried out, at the time of the next time t _{n + 1,} the flip-flop P ₁ to P ₅ 7 (a) pattern is latched, and exclusive OR circuit XOR1
The data of Figure second. 7 (a) to ～XOR5, data of the address "3" shown in FIG. 2 (D ₄ ~D ₀₎ is input. Since there is a disagreement between both data, the exclusive OR circuit XOR2 corresponding to the disagreement outputs "1", the OR circuit 8 is "1", and the load signal of the counter 10 is "0". The value "5" is preset in the counter 10 at the falling edge of the pixel clock pulse, and the address data "5" is output.

Therefore, at the next rise time of the pixel clock pulse at time t _{n + 2} , the selector 6 causes the flip-flop P ₁
.. P ₅ to the flip-flops P _{11 to} P ₁₅ , and at this time, the flip-flops P _{11 to} P ₁₅ latch the pattern of FIG. 7B, so that the exclusive OR circuit XOR 1 to
The data shown in FIG. 7B and the data (D _{4 to} D ₀ ) at the address “5” shown in FIG. 2 are input to XOR5. Since there is also a disagreement between these data, the OR circuit 8 outputs "1", the load signal of the counter 10 becomes "0", and the counter falls at the next falling edge of the pixel clock pulse.
The value "5" is preset after 10 and the address data "5" is output.

Hereinafter, at times t _{n + 3} , t _{n + 4,} ... The same operation as above is performed. In this way, if there is a partial mismatch between the pattern to be inspected and the reference pattern, the detection pulse will not be output from the monostable oscillator 12, and in this example, the match will occur only after six consecutive matches. The detection pulse will be output.

<Modification (not included in the gist of the present invention)> When recognizing a pattern as shown in FIG. 3, the pattern matching in the time series direction shown in FIG. a flip-flop P ₆ to P ₂₀ for try, selector 6 of the flip-flop switching is not always necessary, as shown in Fig. 1 (b), it is also possible to omit these. In that case, the line shift register L ₁
Set the number of bits from ~ L ₃ to 20 as with line shift register L _4.
48 bits. Further, the preset value of the counter 10 is set to “4”, and the memory 5 stores the first reference image data group,
That is, the data (D ₄ at addresses “0” to “4” in FIG.
Store only ~ D ₀ ).

However, in the case of the configuration as shown in FIG. 1 (b), a recognition error may occur when a pattern corresponding to a line or a line width as shown in FIG. 8 is recognized. Next, the reason will be explained. Now, it is assumed that the memory 5 stores the reference pattern data shown in FIG. 8 and the surface to be inspected has a pattern as shown in FIG. In this case, the data of FIG. 10 (a) is latched in the flip-flops P _{1 to} P ₅ at time t _n , and this data and the eighth data are latched.
The data (D _{4 to} D ₀ ) at the address “4” shown in the figure are compared. Since these data match, counter 10
Is subtracted and the address data becomes "3". Next time
At time t _{n + 1} , the flip-flops P _{1 to} P ₅ are also in the 10th position.
The data shown in FIG. 9A is latched, and this data is compared with the data (D _{4 to} D ₀ ) at the address “3” shown in FIG. Again, since both data match, the counter
10 is subtracted and the address data becomes "2". However, at the next time t _{n + 2} , the flip-flops P _{1 to} P ₅
Again although the data of the 10 view (a) is latched, this data is data of the address "2" as shown in FIG. 8 (D ₄ ~
Since it does not match D ₀ ), the counter 10 is preset to the value “4” and the address data “4” is output by comparing the two data. At the next time t _{n + 3,} the data shown in FIG. 10 (b) is latched in the flip-flops P _{1 to} P _5, and the data (D _{4 to} D 4) of the address “4” shown in FIG. ₀ ), the counter 10 is continuously preset to the counter value "4". From this point of view, the pattern shown in FIG. 8 is not recognized for the surface to be inspected having the pattern shown in FIG. Therefore, the modified example of FIG. 1 (b) is excluded from the scope of the present invention.

<Pattern example 2> Therefore, as shown in FIG.
The above problem can be avoided if P _{6 to} P ₂₀ and the selector 6 are provided and the pattern matching in the time series direction is also checked in advance. The reason will be described below. Now, it is assumed that the pattern data shown in FIG. 11 is stored in the memory 5 and the pattern shown in FIG. 9 exists on the surface to be inspected. First, at time t _n−1 , the flip-flop P
To ₁₁ to P ₁₅ are data of FIG. 2 (a) is latched,
At this time, the counter 10 is because it is preset to the value "5", the selector 6 to select the flip-flop P ₁₁ to P _15. As a result, the exclusive OR circuit XOR1～XOR5, the data of Figure 12 (a), data of the address "5" as shown in FIG. 11 (D ₄ ~D ₀₎ are compared, these data one Since it has not been done, the value "5" is continuously preset in the counter 10.

At the next time t _n , flip-flops P _{11 to} P ₁₅
Since the data in FIG. 12B is latched and the selector 6 continues to select the flip-flops P _{11 to} P ₁₅ ,
The data shown in Fig. 12 (b) and the address "5" shown in Fig. 11
Data (D _{4 to} D ₀ ) are compared, and since these data match, the counter 10 is decremented and the data of address “4” is output.

If the data of the address “4” is output, the next time t _{n + 1}
In the selector 6, because it is switched from the flip-flop P ₁₁ to P ₁₅ to the flip-flop P ₁ to P ₅ side, thereafter, the sub-scanning direction of the inspection image data latched by the flip-flop P ₁ to P _5, Address "4" of memory 5 ~
The first reference image data stored in "0" is sequentially compared, and pattern recognition is performed. In this way, it is possible to accurately recognize a pattern corresponding to a line or line width as shown in FIG.

<Pattern Example 3> As shown in FIG. 1A, a plurality of flip-flop arrays (in this embodiment, the flip-flop array [P ₆ ~ P
_10], [P ₁₁ to P _15], by 3 columns) following reason provided in [P ₁₆ to P _20). For example, in the case of recognizing whether or not the pattern shown in FIG. 2 exists with respect to the pattern in which the central part is elongated in the time series direction as shown in FIG. 13 (a), the flip-flop string P _{11 in the} central part is recognized. which may cause recognition errors of the pattern be examined prior to match time-series direction of the pattern in to P _15, but provided a plurality of columns of flip-flop column as described above, the address stored in the memory 5 ' the selector switching data D _6, D ₅ 5 ", if Re selectively switched to the other one of the flip-flop column as shown in FIG. 13 (b), a pattern such as Fig. 13 (a) Even in the case of recognition, the selector 6 allows the flip-flop string P _{6 to} P ₁₀ or P
Accurate pattern recognition is possible by selecting any one of _{16 to} P ₂₀ and checking the pattern matching in the time series direction. In this case, the address "5" stored in the memory 5, in addition to the selector switching data (D _6, D _5),
As the reference image data (D _{4 to} D ₀ ), reference image data of the main scanning direction row corresponding to the flip-flop row selected by the selector 6 in the first reference screen data group is shown in FIG. It goes without saying that it is stored as shown.

<Pattern Example 4> Next, the function of the memory 7 will be described. Here, for convenience of explanation, a case where an L-shaped pattern is recognized as shown in the data (D _{4 to} D ₀ ) of addresses “0” to “4” in FIG. 14 will be described as an example. Now, it is assumed that another pattern exists near the L-shaped pattern on the surface to be inspected, as shown in FIGS. 15 and 16. In this case, as described in the previous example, if all the memory 7, "1" is written, the memory address "4" - "2" are sequentially output from the flip-flop P ₁ to P ₅ The data and the data (D _{4 to} D ₀ ) sequentially output from the memory 5 match, but the memory address “1”,
When it is "0", they do not match, and the L-shaped pattern is not recognized.

However, if the masking data as shown in FIG. 17 is stored in the memory 7, the above L-shaped pattern can be recognized. That is, when the data (D _{4 to} D ₀ ) of the address “1” of the memory 5 are compared, the output of the exclusive OR circuit XOR 1 is “1” for the patterns of FIGS. 15 and 16. And the outputs of the other exclusive OR circuits XOR2 to XOR5 are "0". However, the 17th output from the memory 7
Masking data of address "1" in the figure (D ₄ ~
D ₀ ), the output of the AND circuit AND1 becomes “0”, and as a result, the outputs of all the AND circuits AND1 to AND5 become “0”, and the OR circuit 8 outputs “0”, It means that the matching of the pattern in the necessary part was confirmed. Similarly, if the data of the address "0" in FIG. 14 of the memory 5 (D ₄ ~D ₀₎ is compared against the pattern of FIG. 15 the output of the exclusive OR circuit XOR1 is "1 , And the 16th
Exclusive OR circuits XOR1 and XO for the pattern in the figure
The output of R2 becomes "1". However, the masking data of the address "0" in FIG. 17 which is output from the memory 7 (D ₄ ~D _0), the output of the AND circuit AND1 and AND2 are both "0". In other words, it is confirmed that the matching of the pattern in the necessary part is confirmed here as well. In this way, a series of pattern recognition operations are performed, and as a result, the L-shaped pattern shown in FIG. 15 is recognized in the same time chart as in FIG.

<Pattern Example 5> Next, another function of the memory 7 will be described. In general,
When a specific pattern on the surface 1 to be inspected is input by the input device 2, there is a problem with the optical system or a problem with the scanning position,
Data uncertainties may occur at the boundaries and the like due to quantization errors, and image data slightly different from the actual pattern may be obtained. Even in such a case, if the masking data for masking the uncertain portion is stored in the memory 7, it becomes possible to perform the pattern recognition in the same state as the state in which there is no quantization error. The reason for this will be described below, but it is difficult to properly express with a 5 × 5 pixel size.
Here, the case of 20 × 20 pixel size will be described as an example. Now, it is attempted to recognize a pattern as shown in the range of addresses _{0 to 19} and data D _{0 to} D ₁₉ in FIG. Generally, when such an input pattern is input by the input device 2, for example, as shown by the diagonal lines in FIG. 19, (t ₁₄ −D ₁₆ ), (t ₉ −D ₁₁ ), (t ₅ −
Image data including a quantization error such as D ₈ ) is obtained. Therefore, as shown in FIG. 20, if masking data having data of “0” is stored in the memory 7 in the area corresponding to the boundary portion, the above-mentioned quantization error is ignored in the pattern recognition, and the pattern is ignored. Can recognize.

<Effects of Embodiment> As described above, according to the pattern recognition device, the pattern data to be recognized is provided in the memory 5,
Various pattern recognitions can be realized with the same circuit configuration, and the circuit configuration can be greatly simplified. Moreover, the pattern recognition can be speeded up by processing the two-dimensional pattern recognition in time series. Also, flip-flop P ₆ ~
Since the pattern matching in the time series direction is checked in advance by P ₂₀ , pattern recognition can be accurately performed even for a pattern corresponding to a line or a line width, for example. In addition, since a plurality of flip-flop arrays for checking the pattern matching in the time series direction are provided and can be switched depending on the data of the memory 5, by appropriately selecting the flip-flop arrays to be used according to the characteristics of various patterns. The types of patterns that can be recognized can be increased. Further, by providing the memory 7 with masking data, even if another pattern exists in the vicinity of the pattern to be recognized, that pattern can be correctly recognized. Moreover, if the memory 7 has masking data for masking the peripheral portion of the pattern to be recognized, the influence of the quantization error contained in the input image can be easily removed.

(Effects of the Invention) As described above, according to the pattern recognition device of the present invention,
By providing the memory with the pattern data to be recognized, various pattern recognition can be realized by the completely same circuit configuration, and the circuit configuration can be greatly simplified, and the two-dimensional pattern recognition is performed first in the pattern in the main scanning direction. After checking the match first, and then checking the pattern match in the sub-scanning direction in time series, it is possible to improve the accuracy of pattern recognition and achieve the speedup at the same time. To be

[Brief description of drawings]

FIG. 1 (a) is a circuit diagram of a pattern recognition apparatus according to an embodiment of the present invention, and FIG. 1 (b) is a modification other than the object shown to show the effectiveness of the apparatus of FIG. 1 (a). Example circuit diagram, Figure 2, Figure 8, Figure 11, Figure 13 (b), Figure 14 and Figure
FIG. 18 shows the memory data stored in the memory, and FIGS. 3, 6, 9, 13 (a), 15 and 16 show the patterns on the surface to be inspected. Figure showing,
4, FIG. 7, FIG. 10, and FIG. 12 are diagrams showing the data latched by the flip-flops, respectively. FIG. 5 is a time chart for explaining the operation of the pattern recognition device, FIG. 17 and FIG. FIG. 20 is a diagram showing masking data stored in a memory, FIG. 19 is a diagram showing image data including a quantization error input by an input device, and FIG. 21 is a circuit diagram of a conventional example. 1 ... inspection object, 2 ... input device, 3 ... binarization circuit, 5,7 ... memory 6 ... selector, 8 ... OR circuit, 10 ... counter, 12 ... monostable oscillator , L _{1 to} L ₄ …… Line shift register, P _{1 to} P ₂₀ …… Flip-flop, XOR _{1 to} XOR 5 …… Exclusive OR circuit, AND 1 to AND 5 …… AND circuit

Claims (3)

[Claims] 1. (a) Clock signal generating means for generating a clock signal, and (b) Binary image data of the inspection object transmitted in time series along the main scanning direction of the inspection object. Out of m pixels in the same column in the sub-scanning direction orthogonal to the main scanning direction (m
A first latch circuit for latching binarized image data of 2 or more) in synchronization with the clock signal, and (c) of the binarized image data of the object to be inspected for the m pixels. Among the binarized image data, the binarized image data (k is an integer of 1 or more) for k pixels that precedes the predetermined binarized image data in the main scanning direction in time series,
A second latch circuit for latching in synchronization with the clock signal; and (d) m × n pixels having m pixels in the sub-scanning direction and n pixels (n is an integer of 2 or more) in the main scanning direction. Minute reference pattern binary image data is associated with each value of the first address data that specifies the storage location of each m pixel binary image data in each sub-scanning direction. Stored as a group, and in the first reference data group, binarized image data for n pixels in the main scanning direction corresponding to the scanning line to which the binarized image data for k pixels belongs, 2 for the n pixels
The storage area of the binarized image data is stored as a second reference data group in association with the value of the second address data, and further, the first and second address data are binarized image data respectively identified. Corresponding to the first and second
It is a signal that also specifies a storage location of data indicating which of the latch circuits is to be designated, and is associated with each value of the first and second address data, and is used to identify one of the first and second latch circuits. A memory that stores designated data as selector switching data, and m in the sub-scanning direction corresponding to the value of the first address data in response to the input of the first address data to the memory. The second reference data corresponding to the second address data when the first reference data group for pixels and the selector switching data are read and when the second address data is input to the memory. When the group and the selector switching data are read, the memory sends the read first or second reference data group and the selector switching data to the clock signal. (E) One of the binarized image data for the m pixels and the k pixels output by the first and second latch circuits, respectively, is output from the memory. A selector that outputs according to the data, and (f) the first or second reference data group selectively called from the memory and the output of the selector are compared for each corresponding pixel, and all the pixels match. And a comparison circuit that outputs a non-coincidence signal when at least one set of pixels do not coincide with each other, and (g) a value corresponding to the second address data is set as preset data. When the coincidence signal is input from the circuit,
The count value is incremented in synchronization with the clock signal, the count value is output to the memory as the first address data after the increment, and when the mismatch signal is input, the count value is synchronized with the clock signal. While presetting a count value and outputting the preset data as the second address data, when the step of the count value continues n times, the count value is preset in synchronization with the next clock signal and a pattern A pattern recognition device further comprising: a counter circuit that outputs a coincidence detection signal. 2. The second latch circuit comprises 2 pixels for m pixels (here, m ≧ 3) latched by the first latch circuit.
For each of the scanning lines to which a plurality of the binarized image data belong, the binarized image data for the k pixels is included, and the selector switching data includes the first latch circuit. The second reference circuit and the data for designating the output of the k-pixel binary image data in the second latch circuit belonging to any one of the plurality of scanning lines. The pattern recognition device according to claim 1, wherein the scan line of the data group corresponds to the scan line designated by the selector switching data. 3. The comparison circuit includes specific pixel masking means for masking a comparison result between specific pixels in comparison of output data of the selector and output data of the memory for each pixel. The pattern recognition device according to the first or second range.