JPS6027120B2 - programmable memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to read-only memory circuits or programmable read-only memories (hereinafter abbreviated as P-ROMs) in which contents can be written electrically, and more particularly to programmable read-only memories (hereinafter abbreviated as P-ROMs). This relates to a method of testing a circuit in a "blank" state before writing to a ROM.

Recently, P-ROMs, particularly bipolar P-ROMs, have been widely used for a wide variety of information processing and control applications because of their flexibility in allowing the user to write freely stored contents on each P-ROM. As shown in FIG. 1A, such a P-ROM memory cell is of the so-called junction type, in which two diodes 1 are connected in series in opposite directions, and both ends of the diodes 1 are connected to the row and column of the memory. In this method, the cell exhibits a non-conductive state when not written, and is made conductive by shorting one of the diodes to perform writing as shown in FIG. 2a. In addition, in the so-called fuse method in which a diode is connected in series with a fuse 2 and connected between rows and columns as shown in FIG. This is done by blowing out the fuse 2 to make the rows and columns non-conductive.
However, there is a problem with writing logic information into such a cell, which is the problem of slow write speed. That is,
When the P-ROM is not written to, it is a "blank slate", meaning all outputs are 1 (or all 0) no matter which address is selected, so it is not possible to test whether the peripheral circuits are working normally. There's no pot. Therefore, a defect in the peripheral circuit becomes obvious only after a certain bit pattern is written, and at this stage the P-ROM becomes defective in writing. Therefore, in order to reduce these write defects and improve the write yield, it is necessary to test the peripheral circuits in advance by some means, and various means have been devised for this purpose. The most commonly used method is to add so-called dummy cells, i.e. rows or columns of cells in which appropriate logic information has been written in advance, in addition to the regular memory cell matrix, through which the corresponding peripheral circuits can be connected to column or row decoders. This is a way to test. However, in such a method, the logic information of the addressed dummy cell may coincide with an apparent erroneous readout due to a failure in a peripheral circuit or the like, and the detection rate cannot necessarily be said to be sufficient. FIG. 3 shows an example of a subordinate P-ROM in which dummy cells are arranged. The column decoder 20 decodes eight column lines 00 to ~111C by inputting three binary row addresses AC, ~AC3, and three binary column address inputs AR, ~AR.
3 is input, and the eight row lines 00 to 111R are decoded by the row decoder 0. At each intersection of the matrix, an unwritten memory cell (0 in this case) 25 is arranged.

Furthermore, in addition to the column lines, one end of each cell is commonly connected to the column line 35 by a column dummy cell 30, and the end of each cell is connected to the row line 00 to 1.
11R respectively, and the other row dummy cell 4
0 is connected to row line 45 at one end of each cell, and the other end of each cell is individually connected to column line 00 to 111C.
In the column dummy cells 30 and row dummy cells 40, information 0 is written alternately in row and column units, respectively.
A cell 15 is arranged. This test using row and column dummy cells shows that when using dummy cells, the column line 35 and the row line 00 pulse decoded by decoder 0
111R to sequentially read out the column dummy cells 30 and compare this read information with the stored contents of the actual dummy cells. If they match, there is no defect; if they do not match, there is a defect. It is assumed that The same process is performed when row dummy cells 40 are used. According to this method, short-circuit defects between row or column wirings and part of row or column decoder defects can be eliminated, but the remaining row or column decoder defects cannot be eliminated. FIG. 4 shows another example of a conventional P-ROM using dummy cells.

In this example, the column dummy cell 31 and the row dummy cell are arranged in the same machine as in the case of FIG. , and in the row dummy cell 41, the same machine writes 01101001 from columns 00 to 111C. This test using row and column dummy cells is carried out in exactly the same manner as in the case of FIG. However, testing using matrix dummy cells written in this way can eliminate most row or column decoder defects, but it still does not eliminate half of the two-address simultaneous selection defects, and short-circuit defects between adjacent row or column wirings. Also, the value of the dummy cell is 1
．． When the value is the same as 1 or 0,0, it cannot be excluded.
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of such secondary P-ROMs, improve the detection rate of defects in peripheral circuits, and therefore provide a P-ROM with high reliability.

The programmable read-only memory according to the present invention includes an array arranged in a matrix, N rows of these arrays,
a binary decoder (hereinafter each referred to as a "row decoder") for selecting each of the M columns;
Furthermore, 2 rows for N rows, 2 rows for M columns, and 2 rows for each
A row and column array of fixed memory cells in a column (hereinafter referred to as "dummy cells") is provided, and in these two rows of fixed memory cell arrays, cells in the same column are each written with different logic information, and The memory cell array is characterized in that cells in the same row have different logic information written therein.

Furthermore, in the fixed memory cell array of two rows and two columns according to the present invention, in one row of the two cell arrays, different logic information is written alternately along the column order (for example, 1, 0, 1,0,...) other 1
The row cells are set to be different from the above-mentioned one row in the same column, and logical information is written in the column order (for example, 0, 1, 0, 1, ...), that is, one row and Complementary logic information is written to cells located in the same column in the other row, so that the logic information of adjacent cells in the column order is different between the first row and the other row, and In fixed memory cell arrays, one of these
Cells in the same row of a column and another column can be provided with complementary logic information written in each row, and logic information in each adjacent row of the two columns in parentheses is different. preferable. Furthermore, in the present invention, it is preferable to arrange the addresses of the row and column decoders in such a way that parities of odd numbers and corner numbers are arranged alternately, paying attention to whether the parity is odd or even. .

Here, the odd number and even number of parity means that when selecting an address using multiple binary address information, for example, the number of binary code "1" is focused on, and the binary code "1" is selected.
1", the parity of the selected address is called odd parity, and the parity of the selected address is called even parity. According to the present invention, the dummy cells are arranged in the same row or column. P includes a peripheral circuit that can detect both oven mode and short mode because it can logically measure the input contents of cells in two adjacent rows of a column and two adjacent rows of the same row. One ROM can be tested.

Further, if the parity of the address in the decoder is set alternately at odd corners, it is possible to easily detect a defect in the decoder. Next, one embodiment of the present invention will be described with reference to FIG.

In this embodiment, a matrix of 〆×〆 will be explained for the sake of simplicity. The row decoder 10' inputs the 3-bit address information AR, -AR3 of each row and decodes eight sequential row addresses 000R-10 arranged from the top of the diagram.

Here, the row line 00 is the corner parity of "000" for "AR3, AR2, AR," and the row line 001R is "000".
01'' odd parity.Similarly, the row lines 011R,
0 plate R, 11 plate R, 111R, 101R, 10 mark R are corner parity "011", odd parity "01", corner parity "11", odd parity "11r corner parity "1", respectively.
01'', odd parity ''01''. In other words, the row address lines are arranged alternately in the order of odd parity and corner parity. The column decoder 20 inputs 3-bit column address information Ac, ~Ac3. Decoding the column addresses 000 to 10 arranged from left to right in the eight sequential diagrams.For the eight column addresses 00 to 10, "ratio 3, Ac2, Ac," is written in the same way as for the row addresses. Sequential even parity “00bi”, odd parity “00r”, corner parity “01”
r, odd parity "01", corner parity "11", odd parity "11r", corner parity "10r", odd parity "10"
It is considered a people.

The address order of these rows and columns is generally called a Baker code. At each of these eight row and column addresses, a memory cell 25 whose unreverberated state is a non-conductive logic "0" is arranged. On the other hand, the arrangement of the dummy cells is based on the dummy row addresses 143 and 144, with dummy cells placed at each intersection between the dummy row addresses 143 and 144 and column addresses 00 to 10. 1
41, and the dummy row address 144 is set as the second row dummy cell 142. First row dummy cell 1411'
From column address 00 to column address 10, sequentially "0", "
The cells are arranged so that the logical information is repeated as ``1'', ``0'', ``1''..., and the second row dummy cell 142
In the column address 00 to column address 10, logic information opposite to the first row address 141 for the same column address is written. That is, from column address 00 to column address 10
Sequentially "1", "0", "1", "0"...
・The roof is built in such a way that it looks like this. For the other column,
By providing a memory cell for each intersection between each column of dummy column addresses 133 and 134 and row addresses 00 to 10, the first column dummy cell 131
and second column dummy cells 132 are arranged. The first column dummy cells 131 are sequentially "0", "1", "0", "1", etc. for 10 pulses starting from row address 00.
Different logical information is penetrated alternately,
Logic information different from that of the first column dummy cell 131 is written in the second column dummy cell 132 at the same row address. That is, logical information is sequentially written as "1", "0", "1", "0", . . . from row address 00 to row 10. The dummy cells in the first and second rows and columns may be of the same type as the memory cell 25 and may be provided by selectively writing using a mask or the like, or they may be of a different type from the cell 25. may be used to make each intersection conductive or non-conductive. Next, a case in which a P-ROM having such a configuration is tested will be briefly described.

First, the test using row dummy cells is dummy row address 1.
43 and the column address selected by the column coder 20, the logical information of those points is read out and compared with the logical information written at the actual intersection.

Similarly, the dummy row address 144 is also tested. In this way, by using two row dummy cells, it is possible to detect a defective check of the column address and column decoder, and in this embodiment, the address parity is also arranged alternately, so that adjacent addresses It is easy to distinguish between the two, and it is possible to efficiently detect a defective decoder. Furthermore, by using two column dummy cells one at a time and reading out the intersection between these and the row address, it is possible to detect defects in the row address and row decoder in exactly the same way. Here, the dummy row address and dummy column address are determined by the row decoder 10 and column decoder 20.
It is preferable to select the row decoder 10 and
The column decoder 20 may be used for selection, and in this case, a dummy row or column address is selected when a potential level different from the potential level when selecting a general memory cell is applied. It is preferable to do so. It should be noted that the present invention is not limited to the above-described embodiments, and can of course be applied to matrices of any arrangement and memory cells of any configuration.

Figures 1a and b are circuit diagrams showing the configuration of fixed memory cells, and Figures 2a and b are circuit diagrams of the cells in Figure 1a and b, respectively. FIG. 3 is a diagram showing an equivalent circuit when

3 and 4 are general diagrams showing conventional P-ROMs, respectively, and FIG. 5 is a block diagram showing an embodiment of the present invention. Symbols in the diagram: 1...Diode, 2...
・Fuse, 10... Row decoder, 20... Column decoder, 30, 31, 131, 132... Column dummy cell, 40
．． 41, 141, 142...Row dummy cell, 35, 13
3,134...Dummy column address, 45,143,14
4...Dummy column address, 25, 15... Cell. Rare figure, 2 figures, bell, 31 blades, 4th figure, inferior 5th figure

Claims (1)

[Scope of Claims] 1. A memory array arranged in a matrix of N rows and M columns (N and M are positive integers), means for selecting each of the N rows and M columns, and means for selecting each of the N rows and M columns; 2 rows and 2 columns of fixed memory cell arrays provided for M columns, respectively, such that logical information of fixed memory cells located in the same column is different from each other in the two rows of fixed memory cell arrays. A programmable memory characterized in that in the two columns of fixed memory cells, fixed memory cells located in the same row have different logic information. 2. The programmable memory cell array according to claim 1, wherein rows and columns of the two-row and two-column fixed memory cell array are respectively selected by second selection means different from the selection means. memory.