JPS6063651A - Storage device - Google Patents

Abstract

PURPOSE:To prevent areas where error bits are unevenly distributed from overlapping with each other by making a storage cell in each array different in position for an address fed from the external. CONSTITUTION:A storage device consists of two storage cell arrays 21 and 22, row decoder circuits 23 and 24, column decoder circuits 25 and 26, and a logical circuit 27. The address sequence of word lines as outputs of the row decoder circuits 23 and 24 and the address sequence of bit lines as inputs to the column decoder circuits 25 and 26 are inverted between dual storage cell arrays 21 and 22. Consequently, the positions of storage cell at the same addresses of the storage cell arrays 21 and 22 are different for the decoders between the cell arrays.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory device that multiplexes memory cell arrays and compensates for errors occurring in the memory cell arrays.

[Prior art]

In the field of semiconductor integrated circuits, there has been remarkable progress in increasing the degree of integration through miniaturization. Semiconductor storage device is micro 1I
As the number of semiconductor devices increases, the probability of occurrence of micro defects that cause error pin 1- increases, and problems such as a decrease in device manufacturing yield and a decrease in device reliability become significant.

Conventionally, the following various methods have been known for compensating for error bits by multiplexing memory elements or memory cell arrays containing such defects (error bits).

(1) Effective use of defective elements is achieved by collecting multiple memory elements with different error bit addresses, writing the same information to each memory element, and extracting and outputting the correct data from the read data. How to measure.

(2) By storing the same information in multiple memory elements that operate normally, and taking advantage of the fact that the probability that the information stored at the same address in each memory element becomes an error bit at the same time is low, the reliability of the device described in 1α is improved. How to raise it.

(3) - The memory element has multiple memory cell arrays that store the same information, and a logic circuit that takes the output of each memory cell array as input and extracts only the correct information. A method of improving the yield of memory elements by taking advantage of the low probability that information stored at the same address will simultaneously become error bits.

FIG. 1 shows a storage device that uses conventional multiplexing to compensate for erroneous bits. The storage device in FIG.
An XN-bit memory cell array 1.2, an N-bit row decoder circuit (including a word driver) 3.4, which selects a memory cell in each memory cell array, and an M-bit column decoder circuit (including a sense amplifier). 5.6, and a logic circuit 7 which receives the output of the memory cell array 1.2 and outputs only correct information. An address from the outside is applied to an address input terminal 8, and a memory device output is output from an output terminal 9. Here, row decoder circuit 3.4
The order of the row addresses written inside and the order of the column addresses written inside the column decoder circuits 5 and 6 are the same between the duplicated memory cell arrays. When At I NO is applied to the address input terminal 8, the row decoder circuit 3.4 and the column decoder circuit 5.6 select memory cells at the same address, which is a position on two memory cell arrays. Decoder circuit 5.6
The data is read out to the logic circuit 7 via.

The logic circuit 7 outputs correct information from the information read from the two memory cell arrays. There are various methods for outputting correct information. For example, if a defective memory cell is known in advance, the address of the memory cell is registered in an associative memory or the like, and the output from the memory cell array of non-defective memory cells is selected and output. Furthermore, if the memory cell array has such characteristics that the defect is fixed at "o", correct information can be output by simply ORing the outputs of the two memory cell arrays.

On the other hand, when looking at defects that occur on memory cell arrays,
Most of the defects are local defects such as word line or bit line shorts or disconnections. These defects cause the word line,
A bit along the bit line becomes an error, but the probability of an error bit differing between a portion near the decoder circuit (near end) and a portion far away (far end). For example, in the case of a wire breakage, the pinot 1- at the far end from the breakage point will have an error, but the near end will operate normally. Even if the disconnection points exist randomly over the entire array, the bits at the far end from the disconnection point will be in error, so the probability that the far end will be an error bit increases. Furthermore, even in the case of a short circuit, if the wiring resistance is large, the near end often operates normally. Furthermore, even if there is no disconnection or short circuit, the signal waveform at the far end is likely to become dull due to the influence of the wiring time constant, and even slight noise or timing deviation can cause errors. As described above, depending on the connection positional relationship between the decoder circuit and the memory cell array, memory cells where error bits are likely to occur tend to be unevenly distributed at the far end.

Shaded areas 1o and 11 in FIG. 1 are simulated areas of memory cells where error bits are likely to occur along bit lines and word lines, respectively, and 12 is an equivalent memory cell array obtained as an output of a memory device. It is. As is clear from the figure, when duplication is performed using memory cell arrays and decoder circuits with the same configuration, areas where error bits are unevenly distributed will overlap, increasing the probability of errors in information stored at specific addresses. . Therefore, there is a problem in that the effects of increasing yield and improving reliability caused by duplication of the memory cell array are not fully exhibited.

[Purpose of the invention]

An object of the present invention is to further reduce the error probability in a memory device that compensates for error bits by multiplexing the memory cell array.

[Summary of the invention]

The present invention prevents areas where error bits are unevenly distributed from overlapping by making the selected storage cell positions on each storage cell array different for addresses given from the outside.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of the invention. The storage device in FIG. 2 is a storage device with a duplicated storage cell array,
Two NXN-bit memory cell arrays 2]-22, N-bit row decoder circuits (including word drivers) 23 and 24 that select the memory cells of each memory cell array, and M-pin column decoder circuits (sense amplifiers). 25 and 26, and a logic circuit 27 which inputs the outputs of the memory cell arrays 21 and 22 and outputs only correct information. An address from the outside is applied to an address input terminal 28, and a storage device output is outputted from an output terminal 29. 3
The shaded areas indicated by 0.31 are simulated areas where error pits are likely to occur along the pit 1-line and word line, respectively, and 32 is an equivalent memory cell array obtained as the output of the memory device. . Further, the numbers in the row decoder circuit and the column decoder circuit are a row address and a column address, respectively, and the matrix elements in the memory cell array represent the address of each memory cell.

The feature of this embodiment is that the address ordering of the word lines, which are the outputs of the row decoder circuits 23 and 24, and the address ordering of the p] to lines, which are the inputs of the column decoder circuits 25 and 26, are arranged in a duplicate memory cell array. 21.22
It is configured so that it is reversed between the two. As a result, the positions of memory cells with the same address in the memory cell arrays 21 and 22 relative to the decoder differ between each memory cell array.

As mentioned above, the error pits along the lines from pit 1 to the word line are unevenly distributed at the far end portions 30 and 31 when viewed from the decoder circuit, but the memory cells in the unevenly distributed area are generally different between the duplicated memory cell arrays. You will have more addresses. That is,
Addresses located in areas where errors are likely to occur in one memory cell array exist in areas where errors are unlikely to occur in the other memory cell array.

For example, if "LM" is given as the address,
In the conventional example shown in FIG. 1, the location of the memory cell with the address ``IM'' is in the same upper right area of the drawing with high error probability in both arrays 1O111, whereas according to the embodiment of the present invention shown in FIG. In the memory cell array 21, the memory cell with the address "IM" is located in an area with a high error probability in the upper right corner of the drawing, but in the memory cell array 22, the memory cell with the address "IM"' is located in an area with a low error probability in the lower left corner of the drawing. be.

By changing the address ordering between the two sets of decoders in this way, an equivalent memory cell array 3 after duplication can be created.
In No. 21, the area where error pits are likely to occur can be made much smaller than in the past.

Furthermore, by tripling the memory cell array, it is possible to completely eliminate the duplication of unevenly distributed error pit regions. Figure 3 is 3
This is an embodiment of a duplicated memory cell array, in which a third memory cell array 33, a row decoder circuit 34, and a column decoder circuit 35 are further added to the embodiment of FIG. Row decoder circuit 34 and column decoder circuit 3
5, the other row decoder circuit 23
．． 24 and other column decoder circuits 25 and 26 are configured to be different from each other in the address order (, J). Therefore, the addresses of the memory cells in the area where error pits are unevenly distributed are generally different addresses in the memory cell array stage. In the equivalent memory cell array 36'2 after conversion, areas where error pits are likely to occur can be prevented from overlapping.

The above is a case in which the locations of memory cells having the same address and storing the same information are changed for each memory cell array by changing the row decoder circuit and column decoder circuit.

FIG. 4 explains a method for transferring the same information to memory cells having different addresses. 41.42 is a duplicated storage cell array of NXM pins 1 and above; 43.44 is the same N-bit row decoder circuit; and 45.46 is the same N-bit column decoder circuit.

47 is a logic circuit which receives the outputs of the memory cell arrays 41 and 42 and outputs only correct information; 48 is an address input terminal; and 49 is an output terminal of the memory device. In this embodiment, each decoder circuit and the connection relationship between the memory cell array and the decoder circuit are exactly the same in both memory cell arrays. Therefore, the relative positions of the memory cells having the same address and the decoder circuit are also the same in the area memory cell array as in the conventional example shown in FIG. The feature of this embodiment is that the input address signal of one of the decoder circuits is changed using a conversion circuit 50. When an inversion circuit is used as a conversion circuit as shown in FIG. 4, the information stored at the address (x, y) of the memory cell array 41 will be converted to (xyy) in the memory cell array 42. The memory cell at address (X, Y) and the memory cell at address (Y, ■) are located far and close to the decoder circuit, respectively, so the probability that both memory cells are in the unevenly distributed area of error pits at the same time is becomes extremely small. Reference numeral 51 designates an isometric storage cell array after duplication, and as in the embodiment shown in FIG. 2, the overlapping of error pit maldistribution regions can be made much smaller than in the prior art. Note that it is easy to extend this paper or the above-mentioned triplexing.

In the above explanation, the address order within the memory cell array was continuous. On the other hand, the present invention works more effectively on a memory cell array in which the memory cell array is divided into several M sub-memory cell arrays and each sub-memory cell array is arranged in an fF pattern. FIG. 5 shows an embodiment in which the memory cell array is divided into 16 sub-memory cell arrays. Memory cell array 6
By changing the arrangement of the sub-memory cell arrays 0 and 61 as shown in the figure, the error maldistribution area shown in the shaded area becomes a single layer 11 on the equal nl1i storage cell array 62 after duplication.
t, no 31 can be done.

According to these embodiments, it is possible to significantly reduce the probability that the same information stored in each memory cell array will result in an error, and furthermore, the following effects can be obtained.

(]) A method of having memory cell arrays multiplexed on the same semiconductor chip and ensuring manufacturing yield by compensating for error pits caused by minute defects can further improve yield.

(2) In the case where a number of defective memory elements are used and the good parts of the memory cell array are combined to have the function of one memory element, and the defective elements are effectively utilized, one of the present inventions is particularly shown in FIG. This method allows for even more effective utilization.

(3) In a method of compensating for errors by multiplexing memory elements or memory cell arrays in order to improve the reliability of a storage device, the present invention lowers the rate of errors in the same information at the same time, further increasing reliability. can be achieved.

In the above description, it has been assumed that errors are unevenly distributed at the far end, but the present invention is not limited to this, and it is clear that a multiplexed storage device to which the present invention is applied can be constructed regardless of where the errors are unevenly distributed. Furthermore, if a plurality of memory cell arrays are provided, the effects of the present invention are the same whether they are on the same semi-chip or separated into individual memory elements.

〔Effect of the invention〕

According to the present invention, it is possible to prevent unevenly distributed error pits that frequently occur in each memory cell array from storing the same information in areas where error pits are likely to occur. The probability that the same stored information will result in an error can be greatly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIGS. 2 to 5 are block diagrams showing an embodiment of the present invention. 21.22, 33, 41, 42, 60.61...Storage cell array, 23,24,34,43°44...Row decoder circuit, 25,26,35°45.45.Column decoder circuit, 27° 47...Logic circuit. Figure 3 Figure 5 60

Claims (3)

[Claims] (1) A plurality of memory cell arrays each storing the same information, a decoder circuit provided corresponding to each memory cell array and selecting a memory cell within the memory cell array according to an address given from the outside, and the plurality of memory cell arrays described above. The memory cell array is characterized by comprising a logic circuit that outputs correct information from information read from the memory cell array, and making the selected memory cell position in each of the memory cell arrays different in response to an address given from the outside. Storage device. (2) The memory device according to claim 1, wherein each of the decoder circuits is configured to select a different memory cell in each memory cell array for a given address. (3) Addressing of each memory cell on the plurality of memory cell arrays is the same among each array, and selection on each array is made by converting the address given from the outside and giving it to each decoder circuit. 2. The storage device according to claim 1, wherein the storage cell locations are different.