JPS60254762A - Package for semiconductor element - Google Patents
Package for semiconductor elementInfo
- Publication number
- JPS60254762A JPS60254762A JP59111264A JP11126484A JPS60254762A JP S60254762 A JPS60254762 A JP S60254762A JP 59111264 A JP59111264 A JP 59111264A JP 11126484 A JP11126484 A JP 11126484A JP S60254762 A JPS60254762 A JP S60254762A
- Authority
- JP
- Japan
- Prior art keywords
- package
- packages
- terminal
- semiconductor elements
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（ａｌ 発明の技術分野
本発明はプリント基板に半導体素子を有する同一種類の
複数のパッケージが積載されて実装された半導体素子の
実装方法に係夛、〜に、所定のパッケージが選択できる
回路が形成されるようにした半導体素子のパッケージに
関する。DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a method for mounting a semiconductor device in which a plurality of packages of the same type having semiconductor devices are mounted on a printed circuit board. The present invention relates to a semiconductor device package in which a circuit can be formed with a selectable package.
（ｂＪ 従来技術と問題点
複数のメモリ素子などの半導体素子がプリント基板に実
装される場合は第１図に示すように構成されている。第
１図は従来の半導体素子のパッケージの積載を示す（”
）図は斜視図、（ｂ）図は説明図である。(bJ Prior Art and Problems When multiple semiconductor devices such as memory devices are mounted on a printed circuit board, the configuration is as shown in Figure 1. Figure 1 shows the stacking of conventional semiconductor element packages. (”
) is a perspective view, and (b) is an explanatory view.
（８１図に示すように半導体素子２−１〜２− ｎはリ
ード端子が設けられたパッケージに封止され、パターン
配線を有するプリント板基板１の実装面ＩＡＫパッケー
ジを配設することで実装されている。このパッケージの
それぞれのリード端子はプリント板基板１の所定のラン
ドに半田付され、パターン配４１ｉ１１Ｃ接続されるよ
うに構成されている。(As shown in Fig. 81, the semiconductor elements 2-1 to 2-n are sealed in a package provided with lead terminals, and mounted by placing an IAK package on the mounting surface of the printed circuit board 1 having pattern wiring. Each lead terminal of this package is configured to be soldered to a predetermined land of the printed circuit board 1 and connected to the pattern wiring 41i11C.
このような半導体素子２−１〜２−ｎは例えば装置の構
成上メモリ容量が増減する場合があり、半導体素子２−
１〜２− ｎの実装数を変える必要がある。したがって
、半導体素子２−１〜２− ｎの実装数が減少した場合
は当然プリント板基板１の大きさは小さくでき、例えは
／、の長さの大きさは点線のように！、の長さの小ルに
することができる。しかし、一般的にプリント板基板ｌ
の大きさは所定の大きさによって形成されているため、
大きさの異なった種種のプリント板基板１を製作すこと
はコストアップとなる。For example, the memory capacity of these semiconductor elements 2-1 to 2-n may increase or decrease depending on the structure of the device.
It is necessary to change the number of implementations from 1 to 2-n. Therefore, when the number of semiconductor elements 2-1 to 2-n mounted is reduced, the size of the printed circuit board 1 can naturally be reduced. For example, the length of / is reduced as shown by the dotted line! , can be made into a small length. However, generally the printed circuit board l
Since the size of is formed by a predetermined size,
Producing various types of printed circuit boards 1 with different sizes increases costs.
そこで、所定の大きさのプリント板基板ｌには必要な半
導体素子２−１〜２−ｎを配設し、メモリ容量の削減に
よって不要となった半導体製は除去し、半導体素子の未
実装箇所が有するように形成されている。したがって、
実装効率が悪い欠点を有していた。Therefore, the necessary semiconductor elements 2-1 to 2-n are arranged on a printed circuit board l of a predetermined size, semiconductors that are no longer needed due to the reduction in memory capacity are removed, and the areas where semiconductor elements are not mounted are It is formed so that it has. therefore,
It had the disadvantage of poor implementation efficiency.
また、このような構成では半導体素子２−１〜２− ｎ
は所定の半導体素子を選択してアクセスできるよう（ｂ
Ｊ図に示す回路が形成されている。Moreover, in such a configuration, semiconductor elements 2-1 to 2-n
allows you to select and access a predetermined semiconductor element (b
A circuit shown in figure J is formed.
半導体素子２−１〜２− ｎのそれぞれにはアドレス設
定部４−１〜４− ｎとゲートＧｌ−Ｇｎとが設けられ
、アドレス設定部４−１〜４−ｎＫ所定のアドレスを設
定することによシ、記憶部３−１〜３− ｎのアクセス
は所定のアドレス情報をそれぞれのゲートＧ１〜Ｑｎに
送出し所定の記憶部が選択されて行なわれるように形成
されている。したがって、それぞれのアドレス設定部４
−１〜４−ｎの一つ一つに対して所定のアドレスを設定
しなければなら表い問題を有していた。Each of the semiconductor elements 2-1 to 2-n is provided with address setting sections 4-1 to 4-n and gates Gl-Gn, and the address setting sections 4-1 to 4-nK are configured to set a predetermined address. Alternatively, the memory sections 3-1 to 3-n are accessed by sending predetermined address information to the respective gates G1 to Qn and selecting a predetermined memory section. Therefore, each address setting section 4
There is a problem in that a predetermined address must be set for each of -1 to 4-n.
（Ｃ） 発明の目的
本発明の目的はパッケージの上面には接触子を設け、複
数のパッケージが積載して実装できるよう圧しこの積載
によって半導体素子の選択すべきアドレス情報の設定が
行なはれ、かつ、半導体素子の実装の増減が容易に行な
えるようにしたもので、前述の問題点を除去したものを
提供するものである。(C) Purpose of the Invention The purpose of the present invention is to provide a contactor on the top surface of a package so that a plurality of packages can be stacked and mounted, and by this stacking, address information to be selected for a semiconductor element can be set. In addition, the mounting of semiconductor elements can be easily increased or decreased, and the above-mentioned problems are eliminated.
（ｄ） 発明の構成
本発明の目的は、かかる半導体素子の実装方法において
、−面にアドレス設定信号を入力するための第１端子、
該−面とは逆の面の該第１端子に対応する位置に第２端
子、該第１端子よシ入力された該アドレス設定信号を変
更して該第２端子より出力するアドレス変更手段を有す
ることを特徴とする半導体素子のパッケージにより達成
される。(d) Structure of the Invention An object of the present invention is to provide a semiconductor device mounting method including: a first terminal for inputting an address setting signal to the negative side;
a second terminal at a position corresponding to the first terminal on the opposite side to the - side, address changing means for changing the address setting signal inputted from the first terminal and outputting it from the second terminal; This is achieved by a semiconductor device package characterized by having the following characteristics.
（ｅ） 発明の実施例
以下本発明を第２図および第３図を参考に詳細に説明す
る。第２図は本発明による半導体素子のパッケージの一
実施例を示す、第２図の（ａ）、 （ｂ）。(e) Examples of the Invention The present invention will be explained in detail below with reference to FIGS. 2 and 3. FIGS. 2(a) and 2(b) show an embodiment of a package for a semiconductor device according to the present invention.
（Ｃ１図は説明図、第３図は構成図である。(Figure C1 is an explanatory diagram, and Figure 3 is a configuration diagram.
プリント板基板１の実装面ＩＡＫはパッケージ５−１の
端子６が半田付されることでパッケージ５−１が固着さ
れ、このパッケージ５−１には更にパッケージ５−２が
、パッケージ５−２はパッケージ５−３が、それぞれの
端子６が挿入されることで積載するように実装されるよ
うにし友ものである。The package 5-1 is fixed to the mounting surface IAK of the printed circuit board 1 by soldering the terminal 6 of the package 5-1, and the package 5-2 is further attached to the package 5-1. The package 5-3 is mounted so as to be loaded by inserting each terminal 6.
このような積載は（ｂＪ図に示すようにパッケージ５を
形成することで行なえる。セラミック材などによって形
成された部材９の一方には端子６を設け、他方には接触
片７を設け、接触片７の挿入孔７Ａは端子６の先端部６
Ａが挿脱できるように形成さね、それぞれの端子６およ
び接触片７にはパターン配線８Ａ、８Ｂ、８Ｃを介して
内設され九半導体素子に接続されるように形成されてい
る。Such loading can be carried out by forming a package 5 as shown in figure bJ.A terminal 6 is provided on one side of a member 9 made of a ceramic material or the like, and a contact piece 7 is provided on the other side. The insertion hole 7A of the piece 7 is inserted into the tip 6 of the terminal 6.
A is formed so that it can be inserted and removed, and is formed so that it is connected to nine semiconductor elements by being internally installed in each terminal 6 and contact piece 7 via pattern wiring 8A, 8B, and 8C.
したがって、メモリ容量の増減によって半導体素子の実
装数を変える場合は積°載されたパッケージ５の積載段
数を変えることで行なえ、増減は容易に行なえる。尚、
パッケージ５−１．５−２゜５−３．５−４の積載には
冷却を前片して間隙Ｓを設けると良い。また、（Ｃ）図
に示す所定のパッケージを選択する番地認識回路を形成
することもできる。Therefore, when changing the number of semiconductor elements mounted due to an increase or decrease in memory capacity, this can be done by changing the number of stacked packages 5, and the increase or decrease can be easily done. still,
When loading packages 5-1.5-2 and 5-3.5-4, it is preferable to provide a gap S by using a cooling front piece. It is also possible to form an address recognition circuit that selects a predetermined package as shown in FIG.
それぞれのパッケージ５−１〜５−４には端子６−１と
接触片７−１との間にインバータエを、端子６−２と接
触片７−２との間に排他オアゲートＧを形成すると、積
載されることにより、パッケージ５−１と５−２．５−
２と５−３．５−３と５−４とはそれぞれの端子６−１
が接触片７−１に、端子６−２が接触片７−２に接続さ
れる。In each package 5-1 to 5-4, an inverter is formed between the terminal 6-1 and the contact piece 7-1, and an exclusive OR gate G is formed between the terminal 6-2 and the contact piece 7-2. , by loading packages 5-1 and 5-2.5-
2 and 5-3.5-3 and 5-4 are the respective terminals 6-1
is connected to the contact piece 7-1, and the terminal 6-2 is connected to the contact piece 7-2.
そこで、パッケージ５−１の端子６−１と端子６−２と
を０”にすると、パッケージ５−２の端子６−１と６−
２は１”とｌｌ０１′、パッケージ５−３の端子６−１
と６−２は′０”と１”、パッケージ５−４の端子６−
１と６−２は”ｌ”と１”が出力される。したがってパ
ッケージの積載順序によりてアドレス情報の設定が行な
われる。Therefore, if the terminals 6-1 and 6-2 of the package 5-1 are set to 0", the terminals 6-1 and 6-2 of the package 5-2 are set to 0".
2 is 1" and ll01', terminal 6-1 of package 5-3
and 6-2 are '0'' and 1'', terminal 6- of package 5-4.
1 and 6-2 output "1" and "1". Therefore, the address information is set according to the loading order of the packages.
また、例えば、第３図に示す回路構成が可能である。互
いの端子片６と接触子７とが接続されて積載されたパッ
ケージ５−１．５−２．５−３．５−４のそれぞれには
グー）Ｇｌ−Ｇ４とインバータＩとが設けられている。Further, for example, the circuit configuration shown in FIG. 3 is possible. Each of the stacked packages 5-1.5-2.5-3.5-4 in which the terminal pieces 6 and contacts 7 are connected to each other is provided with a Gl-G4 and an inverter I. There is.
ゲートＧ１とインバータエでは前述のようにアドレス情
報の設定が行なわれる。Address information is set in the gate G1 and inverter E as described above.
例えば、アドレス情報Ｓ１．３２を０”に設定し、アド
レス選択信号Ｓ３と８４とが０”の時はパッケージ５−
１の排他ノアゲートＧ２と０３の出力は１”となり、又
、選択指示信号Ｓ５が′１”になるので、アンドゲート
Ｇ４はオープンなる。しかし、パッケージ５−２では排
他ノアグー）Ｇ２の出力が０”、排他ノアグー１−Ｇ３
の出力が１”となり、パッケージ５−３では排他ノアグ
ー）Ｇ２の出力がｌ”、排他ノアグー）Ｇ３の出力が０
″となり、パッケージ５−４では排他ノアゲー田２とＧ
３とＱ出力がＮｏｎとなシ、いづれのアンドゲートＧ４
もクローズとなる。したがって、チップセレクト信号Ｓ
５はパッケージ５−１の記憶素子Ｍをアクセスするが、
パッケージ５−２．５−３゜５−４の記憶素子Ｍはアク
セスされない。又、アドレス情報８１．８２を０”に設
定しパッケージ５−２を選択する場合はＳ３をｌ”、８
４を６０”、パッケージ５−３を選択する場合に８３″
０”、８４を′１”、バンケン５−４を選択する場合は
Ｓ３を１”。For example, when address information S1.32 is set to 0'' and address selection signals S3 and 84 are 0'', package 5-
The outputs of the exclusive NOR gates G2 and 03 become 1'', and the selection instruction signal S5 becomes 1, so the AND gate G4 becomes open. However, in package 5-2, the output of exclusive no-goo) G2 is 0'', and the output of exclusive no-goo 1-G3 is
In package 5-3, the output of G2 (exclusive no go) is l'', and the output of exclusive no go (exclusive no go) G3 is 0.
'', and in package 5-4 exclusive Noageta 2 and G
3 and Q output are Non, which AND gate G4
will also be closed. Therefore, the chip select signal S
5 accesses the memory element M of the package 5-1, but
Memory element M of package 5-2.5-3°5-4 is not accessed. Also, when setting address information 81.82 to 0" and selecting package 5-2, set S3 to l", 8
60" for 4, 83" when selecting package 5-3
0'', 84 as '1'', and S3 as 1'' when selecting Banken 5-4.
Ｓ４を”１″にすればよい。It is sufficient to set S4 to "1".
このように構成すると、アドレス選択信号Ｓ３と８４の
所定のアドレス情報によって、ノアグー）Ｇ２．Ｇ３出
力を受けるゲートＧ４を介して所定のパッケージが選択
され、所定の記憶素子Ｍをアクセスすることができる。With this configuration, according to the predetermined address information of the address selection signals S3 and 84, the No.G2. A predetermined package is selected via the gate G4 receiving the G3 output, and a predetermined memory element M can be accessed.
（ｆ） 発明の詳細
な説明したように本発明はパッケージ５は積載されて実
装されるようにし、バッケジ５は積載されることで、パ
ッケージ５に形成されたゲート回路によって所定のアド
レスが設定されるようにしたものである。(f) Detailed Description of the Invention As described in the present invention, the package 5 is loaded and mounted, and when the package 5 is loaded, a predetermined address is set by the gate circuit formed in the package 5. It was designed so that
これによシ、パッケージ５の実装は積載されて行なわれ
ているため、パッケージ５の着脱による半導体素子の実
装数の増減が容易となシ、かつ、実装効率の向上を図る
ことができ、更に、 従来ノヨウなアドレス設定部およ
び設定部のアドレス設定は工費となシ、実用効果は大で
ある。As a result, since the packages 5 are mounted while being stacked, it is easy to increase or decrease the number of semiconductor elements mounted by attaching and detaching the packages 5, and it is possible to improve the mounting efficiency. However, the conventional address setting section and the address setting in the setting section require no labor costs, and the practical effects are great.
第１図は従来の半導体素子のパッケージを示す（８１図
は斜視図、（ｂ）図は説明図、第２図の（ａ）（ｂ）（
Ｃ）図は本発明による半導体素子のパッケージの一実施
例を示す説明図、第３図は回路構成図を示す。
図中において、
ｌはプリント板基板、２−１〜２− ｎは半導体素子、
３−１〜３− ｎは記憶部、４−１〜４− ｎはアドレ
ス設定部、５−１． ５−２． ５−３． ５−４はパ
ッケージ、６−１． ６−２． ６は端子、７−１．７
−２．７は接触片を示す。
Ｖ １ 区 （ρ）Fig. 1 shows a conventional semiconductor device package (Fig. 81 is a perspective view, Fig. 81 (b) is an explanatory drawing, Fig. 2 (a), (b)
C) is an explanatory diagram showing one embodiment of a package for a semiconductor element according to the present invention, and FIG. 3 is a circuit configuration diagram. In the figure, l is a printed circuit board, 2-1 to 2-n are semiconductor elements,
3-1 to 3-n are storage units, 4-1 to 4-n are address setting units, and 5-1. 5-2. 5-3. 5-4 is a package, 6-1. 6-2. 6 is a terminal, 7-1.7
-2.7 indicates a contact piece. V 1 Ward (ρ)
Claims (1)
ス設定信号を入力するための第１端子、該−面とは逆の
面の該第１端子に対応する位置に第２端子、該第１端子
よシ入力された該アドレス設定信号を変更して該第２端
子よシ出力するアドレス変更手段を有することを特徴と
する半導体素子のパッケージ。A package having a semiconductor element, a first terminal for inputting an address setting signal on the - side, a second terminal at a position corresponding to the first terminal on the opposite side to the - side, and the first terminal. A package for a semiconductor device, comprising address changing means for changing the input address setting signal and outputting it from the second terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59111264A JPS60254762A (en) | 1984-05-31 | 1984-05-31 | Package for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59111264A JPS60254762A (en) | 1984-05-31 | 1984-05-31 | Package for semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60254762A true JPS60254762A (en) | 1985-12-16 |
Family
ID=14556788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59111264A Pending JPS60254762A (en) | 1984-05-31 | 1984-05-31 | Package for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60254762A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4953005A (en) * | 1987-04-17 | 1990-08-28 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
| WO1991000619A1 (en) * | 1989-06-30 | 1991-01-10 | Raychem Corporation | Flying leads for integrated circuits |
| US5028986A (en) * | 1987-12-28 | 1991-07-02 | Hitachi, Ltd. | Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices |
| US5198888A (en) * | 1987-12-28 | 1993-03-30 | Hitachi, Ltd. | Semiconductor stacked device |
| JPH07130949A (en) * | 1993-11-01 | 1995-05-19 | Nec Corp | Semiconductor device |
| US5514907A (en) * | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| US5648683A (en) * | 1993-08-13 | 1997-07-15 | Kabushiki Kaisha Toshiba | Semiconductor device in which a first resin-encapsulated package is mounted on a second resin-encapsulated package |
| US6340845B1 (en) | 1999-01-22 | 2002-01-22 | Nec Corporation | Memory package implementing two-fold memory capacity and two different memory functions |
| US6576992B1 (en) | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
| US6806120B2 (en) | 2001-03-27 | 2004-10-19 | Staktek Group, L.P. | Contact member stacking system and method |
| KR101078744B1 (en) | 2010-05-06 | 2011-11-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
-
1984
- 1984-05-31 JP JP59111264A patent/JPS60254762A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4953005A (en) * | 1987-04-17 | 1990-08-28 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
| US5028986A (en) * | 1987-12-28 | 1991-07-02 | Hitachi, Ltd. | Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices |
| US5198888A (en) * | 1987-12-28 | 1993-03-30 | Hitachi, Ltd. | Semiconductor stacked device |
| WO1991000619A1 (en) * | 1989-06-30 | 1991-01-10 | Raychem Corporation | Flying leads for integrated circuits |
| US5648683A (en) * | 1993-08-13 | 1997-07-15 | Kabushiki Kaisha Toshiba | Semiconductor device in which a first resin-encapsulated package is mounted on a second resin-encapsulated package |
| JPH07130949A (en) * | 1993-11-01 | 1995-05-19 | Nec Corp | Semiconductor device |
| US5514907A (en) * | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| USRE36916E (en) * | 1995-03-21 | 2000-10-17 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| US6340845B1 (en) | 1999-01-22 | 2002-01-22 | Nec Corporation | Memory package implementing two-fold memory capacity and two different memory functions |
| US6806120B2 (en) | 2001-03-27 | 2004-10-19 | Staktek Group, L.P. | Contact member stacking system and method |
| US6576992B1 (en) | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
| KR101078744B1 (en) | 2010-05-06 | 2011-11-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
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