JPS60251431A - Memory display device - Google Patents

Abstract

PURPOSE:To obtain a display device having an effective window function by forming the 3rd memory for storing display switching data in addition to the 1st and 2nd memories and writing switching information indicating a window shape in the 3rd memory. CONSTITUTION:A display control circuit 14 outputs horizontal and vertical synchronizing signals to a CRT26 and simultaneously outputs a display address to memories 16-18 through an address selector 15. Sinchronously with the synchronizing signals, the contents of the three memories 16-18 are simultaneously read out. The read-out signals of respective memories 16-18 are inputted to shift registers 22-24 respectively, converted into serial signals and then inputted to a switching circuit 25. The CRT26 displays the contents of the memory 16 on the while screen when a switching enable signal EN is in the low level, displays the contents of the memory 17 only in the area where the display switching data stored in the memory 18 are in the high level when the EN is in the high level and displays the contents of the memory 18 in an area where the display switching data are in the low level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device having a function of displaying the contents of a memory on a display device such as a CRT or liquid crystal.

Conventional configurations and their problems In recent years, personal computers, etc., have improved image quality and various functions such as high resolution, multicolor display, scrolling, and screen splitting, as memory elements have become cheaper and display control has become more sophisticated. It is being realized. Furthermore, as these devices become more widespread, it becomes necessary to provide devices that are easier to see and use at lower prices. For example, a window effect that inserts another screen into the display screen is one of the effective display functions. When processing a large number of text and graphic information, only a portion of this information can be displayed on one screen, so if you want to temporarily see some of the hidden information, close the window. It is convenient to set it inside and display it. This allows the operator to view two pieces of information at the same time without switching the entire screen.

A conventional memory display device having a window function will be described below. Generally, there are two ways to accomplish this: software and hardware.

FIG. 1 shows the configuration of a conventional memory display device. 1 is the CPU, 2 is the main memory, 3 is the system bus, 4
5 is a display control circuit, and 5 is a selector. Reference numeral 6 denotes a display memory, and the stored display data is sequentially read out by the display control circuit 4 via the selector 6, converted into a serial signal by the shift register 7, and displayed on the CBr4. The display memory 6 and the main memory 2 are connected to the C'PU 1 of the system via a system bus 3, and data can be read and written by the CPU. A case where a window is realized by software with this configuration will be explained using FIG. 2.

Now, taking as an example a case where the display data stored in the area 2a of the main storage device 2 is to be displayed in the arbitrarily set window area 6a, first, the window area 6 of the display memory 6 is displayed.
The data in a is transferred and saved to the save area 2b of the main memory 2. Next, the display data stored in the area 2a is transferred to the window area 6a. As a result, a screen with a window is displayed on the CRTa. The transfer operation is performed by the system CPU1. To close the window,
By transferring the data saved in the save area 2b to the window area 6a, the contents of the display memory 6 are restored to their original data. In this way, a window is formed and restored on the display screen.

In this method, the data in the window is written directly onto the display memory 6 using software, so no extra hardware is required and the configuration is simple. However, the CPU 1 was used three times to save data, transfer data within the window, and restore
It has the disadvantage that it requires data transfer, which takes time. Especially when the window area becomes large, the low-speed CPU1 causes trouble to the operator.
This leads to defects in operability.

FIG. 3 is a diagram showing another conventional memory display device. In this device, the display data to be displayed in the window must be stored in the display memory. 09 is a window circuit, and the CPU 1 sends area information of the window area 6b and the display data storage area 6c to be displayed in the window. When given, a read address for the window portion is generated based on this. That is, the read address outputted by the display control circuit 4 is determined by the window circuit 9 and the selector 6.
is applied to the display memory 6 via the.

However, the window circuit 9 detects that the address signal of the display control circuit 4 is an address within the window area 6b, and only for this part, the read address converted into the address of the display data storage area 6c is sent to the selector. Output to 5.

In this way, a window is formed on the screen.

This method does not require direct rewriting of the contents of the display memory 6 and has a fast response, but on the other hand, the hardware configuration is complicated, especially when the window area is specified in bits in the horizontal direction, or when the window area is not rectangular. It is difficult and expensive to realize this shape.

As described above, conventional devices have drawbacks such as reduced processing speed and increased complexity of hardware.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a memory display device having a simple configuration and an effective window function.

Structure of the Invention The present invention comprises at least a first memory that stores display data, a second memory that stores another display data, a third memory that stores display switching data, and the first memory that stores display data. ．． Second. a display control circuit that simultaneously reads the third memory and displays it on the display screen; a display switching data writing circuit that generates display switching data and writes it to the third memory; A memory display device comprising: a switching circuit that switches between two output signals read from the memory based on an output signal read from the third memory; By directly writing switching information representing the shape of the window in the form of a bit pattern, a window of any shape can be formed at any position on the display screen.

DESCRIPTION OF EMBODIMENTS FIG. 6 is a circuit diagram of a main part of a memory display device according to an embodiment of the present invention. 10 is the system FyCPU.

11 is a main storage device, 12 is a system bus, 13 is a display switching data writing circuit, 14 is a display control circuit, 16 is an address selector for switching between a display address and a write/read address, and 16 is an address selector for storing display data. A memory 17 stores another display data and constitutes a second memory. A memory 18 stores display switching data and constitutes a third memory. 19 to 21 are data buffers, and each of these buffers 1
Reading and writing data to and from each of the memories 16 to 18 is exchanged via the memory cells 9 to 21. 22 to 23 are shift registers, respectively, which convert the output data of each of the memories 16 to 18 from parallel to serial, input it to the switching circuit 25, and display the display data on the CRT 26.

Note that the display switching data writing circuit 13 may be configured to have a graphic generation function by itself, for example, by an LSI having a drawing function, but in this embodiment, the drawing function is provided by a CP.
The description will be made assuming that U10 performs the processing, and the CPU 10 is included as a part of the display switching data writing circuit 13.

The operation of the embodiment configured as above will be described below.

The display control circuit 14 outputs horizontal and vertical synchronization signals to the CRT 26, and at the same time outputs display addresses to the memories 16-18 via the address selector 15, and these three memories 16-18 are simultaneously operated in synchronization with the synchronization signals. Read out. The read output signals of the memories 16 to 18 are input to shift registers 22 to 24, respectively, and after being converted into serial signals, the signals are input to the switching circuit 25.

FIG. 5 shows a specific configuration of the switching circuit 25.
When the switching enable signal (EN) output from the display switching data writing circuit 13 is at low level, the output (ml) of the shift register 22 is output (or game)27. Output from d,
In the case of high level, the output m of the shift register 24
When m3 is at a low level, the output n2 of the shift register 23 is sent to the bow 1, and when m3 is at a high level, it is sent to the OR gate 2.
Output from 7d. In addition, 27a, 27b, 27, C
is and gate, 27e is or gate, 27 f, 2
7q is an inverter. Therefore, the CRT26 has EN
When is at a low level, the contents of the memory 16 are displayed over the entire screen, and when it is at a high level, only the area where the display switching data stored in the memory 18 is at a high level (area where a bit pattern of 1 is stored) is displayed in the memory. The contents of memory 16 are displayed in the display switching data color level area (area where the 0 pit pattern is stored).

Next, the procedure for writing data into each of the memories 16 to 18 will be explained using FIG. Figure 7 shows the write data of each memory and C
This is an example of the use of a window showing the display screen of an RT. In the figure, A11B and C show the contents of the memories 16, 17, and 18, respectively, and 2 shows the CRT display screen.

First, the CPU 10 sends an E to the display switching data writing circuit 13.
In this state, the memory 16 is selected by the bank select signal via the display switching data write circuit 13, and the desired data is written to the memory 16 via the address selector 15 and data buffer 19. The display data 28 to be displayed is written. This operation is a normal operation when the window is not used, and the display data 28 is displayed over the entire surface of the display screen. When displaying a window, the CPU 10 first selects the memory 17 using a bank select signal, and writes desired in-window display data 29 into the memory 17 at the window display position. In this state, the window is not displayed yet.
selects the memory 18 by a bank select signal, and writes display switching data 30 in the memory 18 in a desired shape at a desired window display position. In this example, a diamond-shaped window area 30a is formed at the center of the screen. The display switching data is written so that a bit pattern of all O's is written outside the window area, and a bit pattern of 1 is written inside the window area. In this state, when the CPU 10 instructs the display switching data writing circuit 13 to set EN to the no-y level,
As mentioned above, based on the output signal of the memory 18, the memory 1
6 and memory 17 are selected and CR
Since it is output at T26, the display screen shown in Figure 7 is projected and a window is formed. To end the window, set EN to low level and immediately return to the original screen memory 16.
The data is restored to the display data 28 within.

As described above, the formation and restoration of the window can be easily performed. Further, as long as the display contents of the window are not changed, subsequent formation and restoration of the window can be performed at high speed simply by switching the EN signal.

Note that the memory 18 can have a reduced number of pixels compared to the memory 16 and the memo 17 within the range permitted by the display setting position of the window and the roughness of the shape, and can be realized with a small memory capacity. In addition, the memory 18 is used exclusively for storing display switching data in the embodiment, but by changing the switching circuit 26, it can also be used as a normal display data storage memory in the same way as the memory 16 and the memory 17 when it is desired to use a window. can. Furthermore, although the shape of the window is rhombic in this embodiment, any arbitrary shape such as a circle or a rectangle is possible, and the position of the window can be set in bits. By rewriting the memory 18 from, for example, small rectangular data to gradually larger rectangular data, a corresponding dynamic window can be expressed on the display screen. In addition, while the CPU 1 o is rewriting the window display data or window display switching data in the memory 17 or memory 18, EN is set to low level, and after the rewriting is completed, it is set to high level, so that the operator does not have to worry about the inconvenience during rewriting. It is possible to instantly give the impression that a window has been formed without giving any impression.

Effects of the Invention As is clear from the above embodiments, the memory display device according to the present invention includes a first memory and a second memory, as well as a third memory that stores display switching data, and a switching function obtained from the output of the same memory. By providing a switching circuit that switches display data based on information, it is possible to form an effective window in any shape at any position on the screen using simple hardware and at relatively high speed. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional memory display device, FIG. 2 is a diagram for explaining its window operation, FIG. 3 is a block diagram of another conventional memory display device, and FIG. 4 is a diagram explaining its window operation. FIG. 5 is a block diagram of a main part of a memory display device according to an embodiment of the present invention, FIG. 6 is a circuit diagram showing a specific configuration of the switching circuit, and FIG. 7 is a diagram of the window. It is a diagram for explaining the operation. 10...CPU, 13...Display switching data writing circuit, 14...Display control circuit, 16~
18. Mountain... Memory, 25... Switching circuit. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 3 Figure 14 Figure 4 7 b Figure 5 Figure 6 Figure 7 □ □ □ One? 8 2Q 30 -30a. , 31

Claims (1)

[Claims] A first memory that stores display data, a second memory that stores other display data, a third memory that stores display switching data, and a first memory that stores display switching data. a display control circuit that simultaneously reads out the second and third memories and displays them on a display screen; a display switching data writing circuit that generates display switching data and writes it into the third memory; A switching circuit is provided for switching the two output signals read from the second memory based on the output signal read from the third memory. A memory display device characterized by: