JP2922519B2 - Video synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a video synthesizing apparatus that synthesizes and displays a plurality of types of image information.

(Prior Art) In recent years, the spread of personal computers and workstations has been remarkable. For example, when performing image processing and the like, a plurality of types of computers and workstations may be used at the same time. In such a case,
Dedicated display devices are connected to each computer, and the corresponding computers are operated while confirming the display contents of these display devices. Therefore, it is necessary to check the display contents of many display devices at once, which is inconvenient.

Therefore, it has been considered that image information from a plurality of computers is combined and displayed on a single display device.

(Problems to be Solved by the Invention) However, when, for example, a CRT display device is used as a display device for displaying image information, it is necessary to continuously write image information repeatedly on a screen. The refresh timing for writing may differ depending on the display device. Therefore, a computer system has refresh timing according to the specifications of the system, and image information handled by such a computer system has a video frequency according to the specifications of the system. It has been difficult for a conventional apparatus to synthesize a plurality of types of image information having different video frequencies and refresh timings.

The present invention has been made in view of the above problems, and has as its object to provide a video synthesizing apparatus that can easily synthesize a plurality of types of image information having different video frequencies and refresh timings.

[Means for Solving the Problems] To achieve the above object, a video synthesizing apparatus provided by the present invention comprises a display memory for storing first image information having a predetermined video frequency, and a display memory for storing the first image information. A first method of reading the first image information from a memory at a predetermined refresh timing;
Reading means, a FIFO memory for storing second image information having a video frequency different from the first image information, and a timing different from the predetermined refresh timing from the FIFO memory. , And selectively selects the second image information read by the second reading unit, and the third image information having a video frequency different from the second image information. A frame memory for storing the second image information or the third image information output by the selection means, and a second image information or the second image information stored in the frame memory. A third image information to be read at the predetermined refresh timing;
And the first image information read by the first reading means and the second image information or the third image information read by the third reading means. The image processing apparatus includes a synthesizing means for synthesizing, and a display means for displaying image information synthesized by the synthesizing means.

(Operation) In the present invention, the display memory may include a first video signal having a predetermined video frequency.
And the first readout means reads out the first image information stored in the display memory at a predetermined refresh timing. In addition, the second image information having a video frequency different from that of the first image information and input at a timing different from the refresh timing is stored in the input order, and the output order is stored when the second image information is output. FIFO memory for outputting to The image processing apparatus further includes a selection unit for selectively outputting the second image information output from the FIFO memory and the third image information different from the second image information to the frame memory. A memory stores the second image information or the third image information output from the selection unit. The second image information or the third image information stored in the frame memory is read by the third reading means at the predetermined refresh timing. The combining means combines the first image information and the second image information or the third image information read at the same refresh timing by the first and third reading means in this way, and the combined The display unit displays the image information.

Embodiment An embodiment according to the present invention will be described below in detail with reference to the drawings.

First, the configuration of a video synthesizing apparatus according to the present invention will be described with reference to FIG.

The storage unit 1 is connected to an image processing apparatus having a CPU and the like (not shown),
17 and address information 18 are input. This first image information 17 is formed by a first video frequency. The storage unit 1 is connected to a FIFO (First In First Out) memory unit 3 and receives a video signal 20 from the FIFO memory unit 3. This video signal 20 is formed by a second video frequency different from the first video frequency. The storage unit 1 is connected to the write control unit 4 and receives a control signal 19 and write address information 21 from the write control unit 4. The storage unit 1 stores the first image information 17
And this image information 17 is a first storage means for storing a video signal as second image information having a different video frequency. Further, the storage unit 1 is connected to the display unit 2, and the image information read at the first refresh timing is provided to the display unit 2. The display unit 2 is, for example, a CRT
The image information 13 includes a display device and the like, and is read from the storage unit 1 at the first refresh timing.
Display a.

The FIFO memory unit 3 is connected to an external device, and inputs each of a video signal 3a, a video clock signal 3b, and a clock signal 3c composed of serial data from the external device. The video signal 3a as the second image information is raster-scanned by the external device at a second refresh timing different from the first refresh timing, and is sent as serial data. Also FIFO
When the memory unit 3 stores the data of the video signal 3a,
In accordance with the storage order, the data is sequentially output from the data stored earlier.

The write control unit 4 is connected to an external device (not shown), and receives a video control signal 4a from the external device.
The write control unit 4 is connected to the FIFO memory unit 3,
The control for writing the video signal 3a to the FIFO memory unit 3 is executed.

Next, the internal configuration of the storage unit 1 will be described with reference to FIG.

The memory control unit 12 inputs a control signal 16 for writing or reading the first image information and also inputs a control 19 relating to a video signal writing request from the writing control unit 4. The memory controller 12 is connected to a control port of the display memory 10 and outputs a control signal 24 related to writing or reading of first image information or writing of second image information. That is, the memory control unit 12 controls writing or reading of image information to or from the display memory 10 based on the control signal 16 or 19. The memory control unit 12 is provided with selectors 11 and 15
And controls these selectors 11 and 15 based on the control signal 16 or 19 described above. The memory control unit 12 is connected to a CRT controller 14, and receives a control signal 2 from the CRT controller 14.
Enter 2. The memory control unit 12 controls the selector 15 based on the control signal 22.

That is, the memory control unit 12 functions as a reading unit for reading out the image information stored in the storage unit 1 as the first storage unit at the first refresh timing.

The selector 11 inputs each of the image information 17 and the video signal 20. Further, the selector 11 is connected to the display memory 10 and selects either the image information 17 or the video signal 20 based on a control command from the memory control unit 12 and sends the selected information to the input port of the display memory 10. Output. The selector 15 is connected to the CRT controller 14, and inputs address information 23 from the CRT controller 14. The selector 15 receives the address information 18 from the image processing apparatus (not shown) and the write address information 21 from the write controller 4. Also selector
15 is connected to the address port of the display memory 10,
The selector 15 outputs the address information selected based on the control command from the memory control unit 12 to the address port of the display memory 10.

The parallel-serial conversion unit 13 is connected to the output port of the display memory 10 and is connected to the display unit 2. The parallel-serial conversion unit 13 converts the parallel data input from the display memory 10 into serial data, and converts the converted serial data The information 13a is output to the display unit 2.

Next, the internal configuration of the FIFO memory unit 3 will be described with reference to FIG.

The serial-parallel conversion unit 30 includes a shift register unit 32 and a flip-flop circuit unit 33. The shift register section 32 inputs a video signal 3a consisting of serial data for each predetermined bit. The shift register section 32 has, for example, a number of shift register sections corresponding to the number of bits of the video signal 3a, and each shift register section inputs a video clock signal 3b having a predetermined period. Similarly, the flip-flop circuit unit 33 has a number of flip-flops corresponding to the number of bits of the video signal 3a, and each flip-flop operates in synchronization with the clock signal 3c having a predetermined cycle. The serial-parallel conversion unit 30 formed by the shift register unit 32 and the flip-flop circuit unit 33 receives the video signal 3a composed of serial data, converts the video signal 3a into parallel data, and converts the converted parallel data into a FIFO memory. Output to 31. The storage capacity of the FIFO memory 31 is set to, for example, the same storage capacity as that of the display memory 10 or an appropriate storage capacity that is equal to or larger than that. The fast memory 31 is connected to each of the write control unit 4 and the storage unit 1, and has a serial-parallel conversion unit.
When the video signal 3a input through the memory 30 is stored, the video signal stored based on the control command from the writing control unit 4 is output to the storage unit 1 in the storage order.

 Next, the operation of the embodiment shown in FIG. 1 will be described.

First, the operation when writing the image information 17 into the display memory 10 will be described. When the memory control unit 12 inputs a control signal 16 for writing image information 17, the memory control unit 12 controls the selectors 11 and 15 based on the control signal 16. As a result, the selector 11 selects the image information 17 and
The selected image information 17 is output to the input port of. Also,
The selector 15 selects the address information 18 and outputs the selected address information 18 to the address port of the display memory 10. The memory control unit 12 is a control signal for controlling the writing of the image information 17 based on the control signal 16.
24 is output to the display memory 10. This allows the display memory 10
Then, the image information is transferred to the address area corresponding to the address information 18.
17 is written.

Next, the operation when the image information 17 is read from the display memory 10 will be described.

When the memory control unit 12 receives a control signal 16 for reading out image information 17, the selectors 11 and 15 are controlled based on the control signal 16. As a result, the selector 15 selects the address information 18 for reading the image information 17 and outputs the selected address information 18 to the address port of the display memory 10. Further, the memory control unit 12 outputs a control signal 24 for reading out the image information 17 to the display memory 10.
Output to the control port. As a result, in the display memory 10, the image information at the address corresponding to the address information 18 is read out via the selector 11.

Next, the operation when the video signal 20, that is, the second image information formed by the second video frequency different from the first video frequency of the image information 17 is written to the display memory 10 will be described.

Upon receiving a control signal 19 for requesting writing of the video signal 20, the memory control unit 12 controls the selector 11 and the selector 15 based on the control signal 19. Thus, the selector 11 selects the video signal 20 and the selector 15 selects the write address information 21. Here, for example, a combining area for combining a plurality of types of image information is set in the display memory 10, and an address corresponding to the combining area is given as write address information 21. The memory control unit 12 outputs a control signal 24 for writing the video signal 20 to the display memory 10.
As a result, the video signal 20 is written into the address area corresponding to the write address information 21 in the display memory 10.

Next, an operation when the image information written in the display memory 10 is displayed on the display unit 2 will be described.

The CRT controller 14 outputs a control signal 22 relating to the display of image information to the memory control unit 12. Further, the CRT controller 14 outputs to the selector 15 the address information 23 of the area where the image information to be displayed is stored. The selector 15 is a CRT controller 14 based on a control command from the memory control unit 12.
Is output to the address port of the display memory 10. Further, the memory control unit 12 outputs a control signal 24 relating to display of image information to a control port of the display memory 10. As a result, in the display memory 10, the image information at the address corresponding to the address information 23 is read through the output port. The timing at which the image information is read at this time is set to the same timing as the first refresh timing of the display unit 2. The image information 10 a composed of parallel data read from the display memory 10 is provided to the display unit 2 after being converted into serial data by the parallel-serial conversion unit 13. The display unit 2 displays the input serial data at the first refresh timing.

If the address specified by the address information 23 is the area of the first image information, the first image information is displayed as shown in FIG. Also, address information
If the address specified by 23 is the area of the second image information, the second image information is displayed as shown in FIG. Accordingly, by alternately designating the first image information area and the second image information area by the address information 23, the first image information and the second image information as shown in FIG. A composite image is obtained.

Next, a description will be given of an operation when a request for reading image information from the display memory 10 and a request for writing the video signal 20 to the display memory 10 occur simultaneously.

First, when a video signal 3a composed of serial data of a predetermined number of bits is sequentially input to the FIFO memory unit 3, the FIFO memory 3
At 31, data D ₁ , D ₂ , D ₃ , D ₄ ,... For each predetermined number of bits are sequentially stored as shown in FIG. in this way
When data is written to the FIFO memory 31, the write control unit 4 outputs a control signal 19 for requesting writing of a video signal to the memory control unit 12. When other control signals related to reading of image information are not input to the memory control unit 12, that is, when only the control signal 19 described above is input, the memory control unit 12 selects a selector based on the control signal 19.
11 and the selector 15 are controlled. This allows the selector 11
Selects the video signal 20. As a result, the data D ₁ and D ₂ are transferred from the FIFO memory 31 to the selector 11 as shown in FIG.
To the input port of the display memory 10. As a result, the data D ₁ and D ₂ of the video signal 20 are sequentially written in the display memory 10 as shown in FIG. Next, when the control signal 22 related to the display of the image information from the CRT controller 14 at time t ₃ as shown in FIG. 7 is output, the image information memory control unit 12 based on a control signal 22 input at time t ₃ Priority is given to the control operation relating to the display of. That along with interrupting the writing operation of the video signal 20 to the display memory 10 at time t _3, reads out image information based on the control signal 22. Thus, FIG. 7 (C)
Image data for display from the display memory 10 is read out at time t ₃ as shown in.

Then Along with the reading operation of the image information based on the control signal 22 is terminated at time t _5, it resumes the writing operation of the video signal 20 to the display memory 10. Namely the data D ₃ of the continuous video signal 20 is output from the FIFO memory 31 from time t ₃ as shown in FIG. 7 (B), writing the data D ₃ to the display memory 10. Similarly, FIFO memory 31
Are sequentially written into the display memory 10.

As described above, the video signal 3a is temporarily stored in the FIFO memory unit 3 and is output to the display memory according to the stored order. Even when the image information readout request is made at the same time or before or after the image data readout request, the control process regarding the display of the image data is preferentially performed, and the display image on the display unit 2 can be prevented from being omitted. In addition, the video signal can be reliably written to the display memory after the display control processing is completed.

Next, another embodiment according to the present invention will be described with reference to FIGS.

In the present embodiment, a frame memory unit 5 for storing a video signal 7 as second image information from the FIFO memory unit 3 is provided, and the video signal 7 is stored in the same frame as the first refresh timing of the display unit 2. It is characterized in that reading is performed at a timing.

More specifically, the frame memory unit 5 is connected to the FIFO memory unit 3 and also connected to the write control unit 4, and receives a video input from the FIFO memory unit 3 based on control from the write control unit 4. The signal 7 is stored. The video signal stored in the frame memory unit 5 is read out in synchronization with the first refresh timing of the display unit 2 under the control of the writing control unit 4 as the second reading unit.

The synthesizing unit 6 is connected to each of the storage unit 101 and the frame memory unit 5, and reads the image information 10a read from the storage unit 101 at the first refresh timing and the image information 10a read from the frame memory unit 5 at the first refresh timing. The input video information 9 is input, the input image information is combined by, for example, an OR operation, and output to the display unit 2. The synthesizing unit 6 may be configured to synthesize images not only by the OR operation but also by other operations such as an AND operation and an OXR (exclusive OR) operation.

 Next, the storage unit 101 will be described with reference to FIG.

When receiving the control signal 16 requesting the writing of the first image information, the memory control unit 12 outputs a control signal 24 instructing the writing to the display memory 10,
Controls the secector 15. Thus, the selector 15 selects the address information 18 for writing the first image information, and outputs the selected address information 18 to the display memory 10. In the display memory 10, the first image information input to the input port
17 is stored in the address specified by the address information 18.

When the memory control unit 12 receives a control signal 16 requesting reading of the first image information, the memory control unit 12 issues a control signal for instructing reading based on the control signal 16.
24 is output to the display memory 10 and the selector 15 is controlled. The selector 15 selects the address information 18 for reading the first image information based on the control of the memory control unit 12, and outputs the address information 18 to the display memory 10. Accordingly, the first image information at the address specified by the address information 18 is read from the display memory 10.

Further, when a control signal 22 is input from the CRT controller 14, the memory control unit 12 as a first reading unit executes control relating to reading of image information for display based on the control signal. That is, the memory control unit 12 outputs a control signal 24 for instructing reading to the display memory 10 and controls the selector 15 to send the address information 23 from the CRT controller 14 to the display memory 10. Thereby, the first image information at the address specified by the address information 23 is read from the display memory 10 from the output port. At this time, the first image information is read out in synchronization with the first refresh timing of the display unit 2.

Next, the frame memory unit 5 will be described with reference to FIG.

The frame memory unit 5 includes a frame memory 50 and a selector.
51 and a frame memory control unit 52. The storage capacity of the frame memory 50 is set to the same storage capacity as that of the display memory 10, or to a larger or smaller appropriate storage capacity. The input port of the frame memory 50 is the FIFO memory 3
And a video signal 7 as second image information.
Enter

The frame memory control unit 52 is connected to each of the CRT controller 14 and the write control unit 4 and controls the control signal
Enter 61,54. The frame memory controller 52 is connected to the frame memory 50 and the selector 51, and controls the frame memory 50 and the selector 51 based on the control signal 61 or 54. The selector 51 receives the address information 53 from the write control unit 4 and the address information 63 from the CRT controller 14, and selects one of the address information based on a control command from the frame memory control unit 52,
The selected address information is output to the address port of the frame memory 50.

Next, writing of a video signal to the frame memory 50,
The operation related to reading will be specifically described.

Upon receiving a control signal 54 requesting writing of a video signal, the frame memory control unit 52 outputs a control signal 55 instructing writing to the frame memory 50 based on the control signal 54, and controls the selector 51. The write address information 53 is sent to the frame memory 50. Thus, the video signal 7 is written to the address specified by the address information 53 in the frame memory 50.

When the frame memory control unit 52 receives a control signal 61 requesting reading of a video signal, the frame memory control unit 52 outputs a control signal 55 for instructing reading to the frame memory 50 based on the control signal 61,
51 is controlled to store address information 63 for display in the frame memory.
Send to 50. As a result, in the frame memory 50, the video signal at the address specified by the address information 63 is read from the output port. At this time, the video signal 9 read out is read out in synchronization with the refresh timing of the display unit 2.

The internal configuration of the FIFO memory unit 3 is the same as that shown in FIG. 3, and a detailed description is omitted.

When a specific combining area corresponding to a particular display area of the display unit 2 is set in the frame memory 50 and the video signals stored in this combining area are combined only in the corresponding display area, The display position of the video signal combined with the first image information can be easily controlled.

Next, another embodiment of the frame memory unit 5 will be described with reference to FIG.

In the present embodiment, a selection unit 70 for selecting the video signal 7 and the third image information 73 and outputting the selected signal to the frame memory 50 is provided, so that the video signal 7 and the third image information 73 can be selectively selected. It is characterized in that it is stored in the frame memory 50. Here, the third image information has a different video frequency component from the first and second image information.

Upon receiving a control signal 71 requesting writing of the third image information, the frame memory control unit 52 receives a control signal instructing writing based on the control signal 71.
55 to the frame memory 50 and the selector 51
To control the writing address information 75 to the frame memory 50.
To send to. As a result, the third image information is written to the address specified by the address information 75 in the frame memory 50.

With the above configuration, it is possible to easily synthesize three types of image information having different video frequency components.

Further, the first image information may be used as the third image information. In this case, a selector may be provided between the display memory 10 and the selection unit 70 so as to selectively transmit the first image information to the display memory 10 or the frame memory 50.

With the above configuration, the frame memory 50 can be handled as the auxiliary storage unit of the display memory 10, and a so-called hardware multi-window function can be easily realized.

[Effects of the Invention] As described above, according to the present invention, First In
The second image information input via the First Out memory unit and the first image information different from the second image information are stored in a storage means, and both image information are stored at the same timing from this storage means. Is read, a plurality of different types of image information can be easily synthesized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a video synthesizing apparatus according to the present invention, FIG. 2 is a block diagram showing an internal configuration of a storage unit in FIG. 1, and FIG. 3 is a FIFO in FIG. FIG. 4 is a block diagram showing an internal configuration of the memory unit, FIG. 4 is an explanatory diagram showing a display example of first image information, FIG. 5 is an explanatory diagram showing a display example of second image information, and FIG. Is an explanatory diagram showing a case where the first image information and the second image information are combined, FIG. 7 is an explanatory diagram showing the operation of the embodiment shown in FIG. 1, and FIG. FIG. 9 is a block diagram showing the internal configuration of the storage unit in FIG. 8, and FIG. 10 is a block diagram showing the internal configuration of the frame memory unit in FIG. FIG. 11 is a block diagram showing another example of the configuration of the frame memory unit shown in FIG. 10 Display memory 12 Memory controller 31 FIFO memory

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁶ Identification code FI G09G 5/18 G09G 5/18 5/36 530 5/36 530M (56) References JP-A-2-73293 (JP, A) JP-A-62-235686 (JP, A) JP-A-61-25186 (JP, A) JP-A-63-153583 (JP, A) JP-A-60-198588 (JP, A) (58) (Int.Cl. ⁶ , DB name) G09G 5/00 G09G 5/36 G09G 5/18

Claims (1)

(57) [Claims] A display memory for storing first image information having a predetermined video frequency; first reading means for reading the first image information from the display memory at a predetermined refresh timing; A FIFO memory for storing second image information having a video frequency different from that of the first image information, and a second reading means for reading the second image information from the FIFO memory at a timing different from the predetermined refresh timing. Selecting means for selectively outputting the second image information read by the second reading means and third image information having a video frequency different from the second image information; A frame memory for storing the second image information or the third image information output by the selection means; A third reading unit that reads out the second image information or the third image information at the predetermined refresh timing, the first image information that is read by the first reading unit, Combining means for combining the second image information or the third image information read by the reading means, and display means for displaying the image information combined by the combining means. Video synthesis device.