JPS60246110A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60246110A
JPS60246110A JP10287684A JP10287684A JPS60246110A JP S60246110 A JPS60246110 A JP S60246110A JP 10287684 A JP10287684 A JP 10287684A JP 10287684 A JP10287684 A JP 10287684A JP S60246110 A JPS60246110 A JP S60246110A
Authority
JP
Japan
Prior art keywords
terminal
collector
transistor
region
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10287684A
Other languages
Japanese (ja)
Inventor
Osamu Shiozaki
修 塩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10287684A priority Critical patent/JPS60246110A/en
Publication of JPS60246110A publication Critical patent/JPS60246110A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To realize a new high frequency high output semiconductor device having a two-way signal amplifier function by providing the 1st terminal connected to a collector of the 1st transistor (TR), the 2nd terminal connected to a collector of the 2nd TR and the 3rd terminal connected to a common base of the 1st and 2nd TRs. CONSTITUTION:An N-channel epitaxial layer used as a collector region is formed on a P<->-channel silicon substrate, said epitaxial layer is separated electrically into two regions 10', 10'' by a P insulation separating region 15, P-channel base regions 1', 1'' and N<+> emitter regions 2', 2'' are formed on each region, contact windows 4', 4'', 5', 5'', 6', 6'', are formed to surface insulation films 3', 3'', 3''', and base electrode 7', 7'' are connected electrically by an electrode pattern 11. Suppose that most of signals enters a TRT2 when a signal comes from a terminal A1, the signal is amplified by a TRT2 and the result is outputted to an external circuit through a terminal A2. When the signal comes from the terminal A2 conversely, most of the signals enters the TRT1 and is outputted to the external circuit through the terminal A1.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置、特に入・出力が双方向で動作する
高周波高出力半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a high frequency, high power semiconductor device whose input and output operate bidirectionally.

(従来技術) 最近の通信分野の進歩は著しいものがあり、たとえば衛
星放送通信(DBS )及び有線テレビ通信(CATV
υといった新らしい通信分野が今後伸びてゆくものと考
えられる。またその通信方式についても従来の単一方向
から双方向通信が主流になると思われます。このような
通信分野の進歩革新に対処する為には、通信機器に使用
される電子デバイス特に能動デバイスについても新しい
機能を持ったものが必要となる。
(Prior Art) Recent advances in the field of communications have been remarkable, such as satellite broadcast communications (DBS) and cable television communications (CATV).
It is thought that new communication fields such as υ will continue to grow in the future. It is also likely that bidirectional communication will become mainstream instead of the conventional unidirectional communication method. In order to cope with such advances and innovations in the communication field, electronic devices, especially active devices, used in communication equipment are required to have new functions.

しかるに、従来の能動デバイス即ち高周波高出力トラン
ジスタは、接地形式全決定すれば増幅方向は一方向のみ
に限られておp、入力端全出力端としても利用できる双
方向増幅全可能にする為にはと9しても2つの系列の高
周波高出力トランジスタ群を別々に用意し、これら全並
列に接続しなければならずシステム自体が大きくなり、
複雑になるとともにコストの上昇全まねき、双方向通信
方式の普及に対する重大なる障害となっている。
However, with conventional active devices, that is, high-frequency, high-output transistors, if the grounding type is determined, the amplification direction is limited to only one direction. However, two series of high-frequency, high-output transistor groups must be prepared separately, and all of them must be connected in parallel, making the system itself large.
As the complexity increases, so does the cost, creating a serious obstacle to the widespread use of two-way communication systems.

(発明が解決しようとする問題点) そこで、本発明の目的は、双方向通信方式に対処できる
双方向信号増幅機能を持つ新しい高周波高出力半導体装
置を提供することにある。かかる双方向信号増幅機能を
持った半導体装置全使用すれば、双方向通信システムが
コストの上昇なしで容易に実現できるとともにデバイス
の数が少なくなることにより機器の信頼性の向上も期待
できますO (問題点全解決するための手段) 本発明によれば、ベースが共通に接続された第1および
第2のトランジスタの一方のコレクタと他方のベースが
コンデンサを介して接続され、そレソレのトランジスタ
のコレクタに入・出力端子を接続した半導体装置を得る
。かかる半導体装置は容器内に電気的に分離して形成さ
れた第1および第2のトランジスタチップを有し、これ
らトランジスタチップのベース電極同志全接続し、一方
のトランジスタチップのコレクタと他方のトランジスタ
チップのエミッタと全コンデンサ全介して接続し、それ
ぞれのトランジスタのコレクタ全容器の外部リードに接
続して得られる。
(Problems to be Solved by the Invention) Therefore, an object of the present invention is to provide a new high-frequency, high-output semiconductor device having a bidirectional signal amplification function that can handle bidirectional communication systems. If all semiconductor devices with such bidirectional signal amplification functions are used, a bidirectional communication system can be easily realized without increasing costs, and the reliability of equipment can be expected to improve by reducing the number of devices. (Means for Solving All Problems) According to the present invention, the collector of one of the first and second transistors whose bases are connected in common and the base of the other transistor are connected via a capacitor, A semiconductor device is obtained in which input and output terminals are connected to the collector of the semiconductor device. Such a semiconductor device has first and second transistor chips electrically separated from each other in a container, the base electrodes of these transistor chips are all connected, and the collector of one transistor chip is connected to the collector of the other transistor chip. The emitter of each transistor is connected through all the capacitors, and the collector of each transistor is connected to the external lead of the entire container.

(実施例) 次に1図面全参照して本発明をより詳細に説明する0 まず第1図と第2図はそれぞれ公知の拡散、リソグラフ
ィ、メタリゼーシ画ン等の技術金利用して完成された従
来のトランジスタチップと本発明の一実施例によるトラ
ンジスタチップと會示している。ここでNPN型シリコ
ントランジスタに限定して説明すると、従来のトランジ
スタチップは、まず、N型のシリコン基板上に酸化、拡
散、リングラフイー技術全駆使することによt)P型の
ベース領域1がまたP型のベース領域1内にt型のエミ
ッタ領域2が形成される。さらにリソグラフィー技術に
よって、開けられたシリコン基板上の酸化膜(8i02
 )または窒化膜(8jllN4)等の絶縁膜3上のコ
ンタクト窓4. 5. 6i介して表面にろるベース電
極7とエミッタ電極8とコレクタ電極9がそれぞれベー
ス領域及びエミッタ領域2及びコレクタ領域10と接続
されている。
(Example) Next, the present invention will be explained in more detail with reference to one drawing. First, Fig. 1 and Fig. 2 were completed using known techniques such as diffusion, lithography, and metallization, respectively. A conventional transistor chip and a transistor chip according to an embodiment of the present invention are shown together. If we limit the explanation to NPN type silicon transistors here, conventional transistor chips are manufactured by first making full use of oxidation, diffusion, and phosphorography techniques on an N-type silicon substrate.t) A P-type base region 1 A T-type emitter region 2 is also formed within the P-type base region 1 . Furthermore, an oxide film (8i02) was opened on the silicon substrate using lithography technology.
) or a contact window 4 on the insulating film 3 such as a nitride film (8jllN4). 5. A base electrode 7, an emitter electrode 8, and a collector electrode 9 extending on the surface are connected to the base region, the emitter region 2, and the collector region 10, respectively, via the base electrode 6i.

かかるトランジスタ全ベース接地で使用しようとすると
、必然的に入力信号はエミッタに加え出力信号はコレク
タから取り出さねばならず、この逆の使い方はできない
ので、双方向通信にはこのままでは適用できないという
欠点がある。
If such a transistor is to be used with all bases grounded, the input signal must be taken out from the emitter and the output signal must be taken out from the collector, and the reverse operation is not possible, so it has the disadvantage that it cannot be used as is for bidirectional communication. be.

そこで本発明の場合は、第2図に示す一実施例の如<、
p−mシリコン基板上にコレクタ領域として使用するN
型エピタキシャル層を形成し、このエピタキシャル層i
P型絶縁分離領域15で2つの領域10′と10“とに
電気的に分離し、それぞれの領域にP型ベース領域1′
、1“とN−■エミッタ領域2′、2“とを形成し、表
面の絶縁膜3’、 3″、 3“′にコンタクト窓4/
、 4//、 5/、 5/; 6Z 6“を形成し1
、ベース電極7′、7“同志全電極パターン11によっ
て電気的に接続する。コレクタ電極9′とエミッタ電極
8“とが容量素子12“全弁して電極パターン13にて
電気的に接続されておフ、さらにコレクタ電極9“とエ
ミッタ電極8′とが容量素子12′ヲ介して電極ハター
ン14にて電気的に接続されていま丁。
Therefore, in the case of the present invention, as shown in one embodiment shown in FIG.
N used as collector region on p-m silicon substrate
type epitaxial layer is formed, and this epitaxial layer i
Two regions 10' and 10'' are electrically isolated by a P-type insulating isolation region 15, and a P-type base region 1' is provided in each region.
, 1" and N-■ emitter regions 2', 2" are formed, and contact windows 4/2 are formed on the surface insulating films 3', 3", 3"'.
, 4//, 5/, 5/; 6Z 6" is formed and 1
, the base electrodes 7', 7'' are electrically connected through the electrode pattern 11. The collector electrode 9' and the emitter electrode 8'' are electrically connected through the electrode pattern 13 through the capacitive element 12''. Further, the collector electrode 9'' and the emitter electrode 8' are electrically connected at the electrode terminal 14 via the capacitive element 12'.

結局、3つの電極パターン11,13.14により外部
取り出し用電極パッドも形成され、3端子素子が形成さ
れることになります。この場合1つの端子11は接地端
子となジ、残り2つの端子13゜14はそれぞれ信号の
方向により入力・出力端子となる可能性を持っています
。さらに第2図におけるP型絶縁分離領域15は厚い絶
縁膜でコレクタ領域10′と10“と全電気的に絶縁し
ても良い。
In the end, the three electrode patterns 11, 13, and 14 form electrode pads for external extraction, forming a three-terminal element. In this case, one terminal 11 is used as a ground terminal, and the remaining two terminals 13 and 14 have the possibility of becoming input/output terminals depending on the direction of the signal. Further, the P-type isolation region 15 in FIG. 2 may be completely electrically insulated from the collector regions 10' and 10'' by a thick insulating film.

また、容量素子12’、12“は2つの電極パターン金
絶縁膜を介して重ね合わせることによって形成される。
Further, the capacitive elements 12', 12'' are formed by overlapping two electrode patterns with a gold insulating film interposed therebetween.

第3図にかかる半導体装置の電気的等価回路を示す。こ
こで、2つのトランジスタ素子T。
An electrical equivalent circuit of the semiconductor device according to FIG. 3 is shown. Here, two transistor elements T.

T2はともにベース接地形式で接続されている。トラン
ジスタ素子Tlのコレクタとトランジスタ素子T2のエ
ミッタとが容量C2ヲ介して電気的に接続されて端子A
sk通じて外部回路と接続され1−jo同じようにトラ
ンジスタ素子T2のコレクタとトランジスタ素子T1の
エミッタとが容量C1?介して電気的に接続されて、端
子Aztl”通じて外部回路と接続されます。コレクタ
供給電圧VOOは接地に対し、て2つの端子A、、A2
に同じ極性に印加され、容量C1゜C2はコレクタ供給
電圧が2つのトランジスタ素子Tl、T2のエミッタベ
ース接合に直接印加されるのを防ぐ為に必要となります
Both T2 are connected in a base-grounded manner. The collector of the transistor element Tl and the emitter of the transistor element T2 are electrically connected via the capacitor C2 to the terminal A.
Similarly, the collector of the transistor element T2 and the emitter of the transistor element T1 are connected to the external circuit through the capacitor C1? The collector supply voltage VOO is connected to ground by the two terminals A, , A2.
are applied with the same polarity, and the capacitance C1°C2 is required to prevent the collector supply voltage from being applied directly to the emitter-base junction of the two transistor elements Tl, T2.

この状態において、今仮シに、信号が端子A、から入っ
てくるとベース接地形式のトランジスタの出力インピー
ダンスがそれの入力インピーダンスに対してかなり大き
い為その信号の大部分がトランジスタ素子T2に入り、
トランジスタ素子T2にて増幅され端子Azk通して外
部回路へ出力されます。
In this state, if a signal is input from terminal A, most of the signal will enter transistor element T2 because the output impedance of the common base type transistor is considerably larger than its input impedance.
It is amplified by transistor element T2 and output to the external circuit through terminal Azk.

また逆に信号が端子A2から入ってくると上記と同じ原
理に基づいてその信号の大部分がトランジスタ素子T、
に入り、トランジスタ素子T1にて増幅され端子A+に
通じて外部回路へ出力されることになります。すなわち
、双方向信号増幅が可能となp、双方向通信が低コスト
で容易に行えるようになり、トランジスタ素子T1.T
2の大きさ全任意に組み合せることにより双方向の増幅
度も自由に変えられる可能性?持ちます。
Conversely, when a signal comes in from terminal A2, most of the signal is transferred to transistor element T, based on the same principle as above.
The signal enters the circuit, is amplified by transistor element T1, and is output to the external circuit through terminal A+. That is, bidirectional signal amplification becomes possible, bidirectional communication can be performed easily at low cost, and transistor elements T1. T
Is it possible to freely change the degree of amplification in both directions by combining the two sizes arbitrarily? hold.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の単方向増幅機能金持つ半導体装置の平面
図、第2図は本発明の一実施例により実現される双方向
増幅機能?持つ半導体装置の一例を示す平面図で、第3
図は本発明により提案されている半導体装置の動作原理
全説明する為の電気的等価回路図でありま丁0 1 、1’、 1“・・・ベース領域、2.2’、2“
・・・エミッタ領域、3 、3’、 3“、、、絶縁f
l、4.4′、4ζ5,5′、516.6′、6“・・
・コンタクト窓、7 、7’、 7“・・・ベース電極
、8.8’。 8′′−・・エミッタ電極、9 、9’、 9“・・・
コレクタ電極、10゜10’、 10“・・・コレクタ
領域、11,13.14・・・外部引き出し用電極、1
2’、12“・・容量素子xt/”ら′;′rTゝ 代理人 弁理士 内 KA □+ ’j・\−7・′
Fig. 1 is a plan view of a conventional semiconductor device having a unidirectional amplification function, and Fig. 2 shows a bidirectional amplification function realized by an embodiment of the present invention. 3 is a plan view showing an example of a semiconductor device having a third
The figure is an electrical equivalent circuit diagram for fully explaining the operating principle of the semiconductor device proposed by the present invention.
...Emitter region, 3, 3', 3",, insulation f
l, 4.4', 4ζ5,5', 516.6', 6"...
・Contact window, 7, 7', 7"...Base electrode, 8.8'. 8''-...Emitter electrode, 9, 9', 9"...
Collector electrode, 10°10', 10"... Collector area, 11, 13.14... External extraction electrode, 1
2', 12"...capacitive element

Claims (1)

【特許請求の範囲】[Claims] 互いにベースが接続された第1および第2のトランジス
タと、第1のトランジスタのコレクタと第2のトランジ
スタのエミッタとを接続する第1の容量素子と、第1の
トランジスタのエミッタと第2のトランジスタのコレク
タと全接続する第2の容量素子と、第1のトランジスタ
のコレクタに接続された第1の端子と、第2のトランジ
スタのコレクタに接続された第2の端子と、第1および
第2のトランジスタの共通接続ベースに接続され九第3
の端子と金有すること全特徴とする半導体装置。
first and second transistors whose bases are connected to each other; a first capacitor that connects the collector of the first transistor and the emitter of the second transistor; and the emitter of the first transistor and the second transistor. a second capacitive element fully connected to the collector of the first transistor; a first terminal connected to the collector of the first transistor; a second terminal connected to the collector of the second transistor; The ninth transistor is connected to the common connection base of the third
A semiconductor device having all the characteristics of having terminals and gold.
JP10287684A 1984-05-22 1984-05-22 Semiconductor device Pending JPS60246110A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10287684A JPS60246110A (en) 1984-05-22 1984-05-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10287684A JPS60246110A (en) 1984-05-22 1984-05-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60246110A true JPS60246110A (en) 1985-12-05

Family

ID=14339093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10287684A Pending JPS60246110A (en) 1984-05-22 1984-05-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60246110A (en)

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