JPH02132854A - Emitter-coupled logic circuit - Google Patents

Abstract

PURPOSE:To improve an integration degree and to contrive the improvement of a switching rate in a wiring region by a method wherein an element isolation region is covered with a thick insulating film and an electrostatic capacity is formed under the element isolation region. CONSTITUTION:In a wiring region, an opposite conductivity type semiconductor layer 3 isolated electrically from other regions is formed in a one conductivity type semiconductor layer 1 constituting one side of power supplies and a thick insulating film 6 is formed on the layer 3. The layer 3 penetrates the thick film 6, is connected to a reference voltage circuit and a reverse bias is applied between the layers 1 and 3. In such a way, an electrostatic capacity is formed under an element isolation region, which is covered with the thick layer 6 and is not used normally. Therefore, even if a wiring is formed on the film 6, a parasitic capacity is not generated between the wiring and the electrode on one side of electrodes, between which the electrostatic capacity is formed. Thereby, the improvement of a switching rate and an integration degree can be contrived simultaneously.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of emitter-coupled logic circuits (hereinafter referred to as ECL circuits) used as gate arrays, etc., we have developed 11 ECL circuits that simultaneously satisfy increased integration and improved switching speed. A semiconductor layer of an opposite conductivity type is formed on a semiconductor layer of one conductivity type that forms one electrode of a power supply, and this semiconductor layer of an opposite conductivity type is electrically isolated from other regions. A thick insulating film is formed on the semiconductor layer of the opposite conductivity type, and the semiconductor layer of the opposite R conductivity type is connected to the reference voltage circuit through the thick insulating film. A reverse bias is applied between the semiconductor layer and the semiconductor layer of the opposite conductivity type.

[Industrial application field]

The present invention aims to improve emitter-coupled logic circuits (hereinafter referred to as ECL circuits) used as gate arrays, and in particular to improve the degree of integration and switching speed of ECL circuits used as gate arrays. Concerning improvements realized at the same time. ? Prior Art] See Figure 4 Figure 4 is a circuit diagram of an example of the basic form of an ECL circuit. Two transistors T. -T. The emitters of are connected to each other and connected to the negative voltage B■■, the collectors are connected to the ground potential VCe through resistors R1 and R8, respectively, the base of the transistor T1 is connected to the signal input circuit IN, and the base of the transistor T1 is connected to the signal input circuit IN. ．． The base of is connected to the reference voltage circuit Vl. If the signal input to the input circuit IN of the transistor T is lower than the voltage of the reference voltage circuit ■8,
Since the transistor T is not conductive and only the transistor T3 is conductive, the output signal generated at the resistor R8 becomes "O" and the output signal generated at the resistor R1 becomes "1". When the signal input to the input circuit IN of the transistor T is higher than the voltage of the reference voltage circuit V, the transistor T is conductive and the transistor Tt is not conductive.
Resistance R! The output signal generated at is “1”, and the resistance R,
The output signal generated in this case is "0", and the circuit configuration is such that the output signal is inverted. When the signal input to the signal input circuit IN changes, the base current flowing through the transistor T2 changes, which causes the voltage of the reference voltage circuit to change and the switching speed to slow down. Therefore, in order to suppress the voltage fluctuation of the reference voltage circuit vl, it is necessary to connect the voltage between the it source VCC and the reference voltage circuit vyoi, or between the reference voltage circuit ■1 and the power source ■. A capacitance 1c is now added between. See Fig. 5 Fig. 5 shows a part of the ECL gate array in the $■ area.
1 is a cell area, and 12 is a wiring nod area connecting between cell areas. If the capacitance C is formed in the cell region 11 of the ECL gate array, the cell size will increase and the degree of integration will decrease. If the capacitance 1c is formed in the wiring region 12, there is no need to reduce the degree of integration. See FIG. 6 FIG. 6 is a cross-sectional view when a capacitive IC is formed in the wiring area. For example, an n-type impurity is ion-implanted into a p-type silicon base 1 to form an n-type buried layer 3, and then CVD is applied on top of the n-type buried layer 3.
A silicon layer 4 is formed using a method such as a method, and a thick silicon dioxide film 6 is formed except for the capacitance formation region, and a thin silicon dioxide film 6 is formed in the capacitance formation region to prevent damage during ion implantation. An insulating film 13 is formed, a p-type diffusion layer 14 is formed by ion-implanting p-type impurities, and an opening is formed in a partial region of the thin silicon dioxide insulating film 13, and an opening is drawn therein. Form pole 9. The extraction electrode 9 is connected to the reference voltage circuit v5 shown in FIG. 4, and the n-type buried N3 is connected to the power supply ■. When connected to the ECL, a reverse bias is applied between the p-type diffusion N14 and the n-type buried 113, forming a capacitance.
The wiring connecting each cell of the gate array is made of thin silicon dioxide vP! ．． It is formed on the lamina 13. [Invention tries to solve it! Problem i] If the capacitance C is formed in the wiring region 12 in order to improve the degree of integration, the wiring must be formed on the thin insulating film 13 formed to form the p-type diffusion layer 14. Therefore, p-type diffusion J! which is one electrode of wiring and capacitance C! A parasitic capacitance is generated between the il4 and the thin insulating film 13, reducing the switching speed. On the other hand, if the capacitor 1c is formed in the cell nozzle region 11 in order to avoid a decrease in switching speed, the degree of integration will decrease. In other words, there is an antinomic relationship between improving the degree of integration and improving switching speed, and in the prior art, it has been impossible to satisfy both at the same time.

The purpose of the present invention is to eliminate this drawback, and to provide an EC that satisfies both the degree of integration and the improvement of switching speed.
The objective is to provide an L circuit. [Means for Solving the Problems] The above object is such that a semiconductor layer (3) of an opposite conductivity type is formed on a semiconductor layer (1) of one conductivity type forming one III of the power supply, and The semiconductor layer (3) is electrically isolated from other regions, and a thick insulating film (6) is formed on the semiconductor layer (3) of the opposite conductivity type. (3) is connected to the reference voltage circuit (Vl') through the thick insulating film (6), and is connected to the semiconductor layer (1) of one conductivity type and the semiconductor layer (1) of the opposite conductivity type.
3) is achieved by an emitter-coupled logic circuit to which a reverse bias is applied. [Operation] In the ECL circuit according to the present invention, the thick LOcoss
A capacitance 1c is formed under the element isolation region that is covered with the edge film 6 and is not normally used, and a thick LOcos1! Even if the wiring is formed on the edge film 6, parasitic capacitance is not generated between the wiring and one electrode constituting the capacitance C, thereby simultaneously improving the switching speed and the degree of integration. I decided to do so. [Example] Hereinafter, with reference to the drawings, an EC according to an example of the present invention will be explained.
The capacitance connected to the L circuit, particularly the ECL circuit which is the gist of the present invention, will be explained. See Figure 1a Figure 1a is a circuit diagram of an example of the basic form of an ECL circuit. The emitters of transistors T1 and T2 are connected to each other and connected to the negative power supply v0 through a constant current source l5, and the collectors are connected to the ground power supply VCC through respective resistors R+R2.
and the transistor T. The base of the transistor T, is connected to the signal input circuit IN, and the base of the transistor T, is connected to the reference voltage circuit vll. i! iv. and reference voltage circuit■
7 or between the reference voltage circuit V, and the voltage flV t
A capacitance C according to the gist of the present invention is connected between t and t. This is to prevent the base voltage of the transistor T3 from varying due to the application of the input signal. Capacitance 1
A method for forming the ECL gate array wiring region 12 shown in FIG. 5 will be described below. Refer to FIG. 2. For example, a resist film 2 having an opening in a capacitance forming region is formed on a p-type silicon substrate 1, and an n-type impurity such as arsenic is ion-implanted to form an n-type buried N3. Refer to FIG. 3.Resist film 2 is removed, n-type silicon layer 4 is formed using CVD method, etc., silicon nitride film 5 is formed thereon, and this is patterned to form a separation layer. The silicon nitride film 5 remains in the capacitance extraction electrode formation region and is oxidized to form a thick LOCOS insulating film 6.

Referring to FIG. 1b, the silicon nitride film 5 on the isolation layer forming region is removed, and a p-type impurity such as boron is ion-implanted to form an isolation layer 7.
The silicon nitride film 5 on the lead-out electrode formation region is removed,
A resist film is formed on the isolation N7, and an n-type impurity such as arsenic is ion-implanted to form an electrode contact region 8. The resist film is removed, an aluminum layer is formed on the entire surface, and this is patterned to connect to the electrode contact region 8 to form an extraction electrode 9. The drawer 1t pole 9 is connected to the 1st a
The p-type silicon substrate l is connected to the reference voltage circuit V shown in the figure, and the p-type silicon substrate l is connected to one of the if B V. If connected to n-type buried N3 and p
A reverse bias is applied between the mold silicon substrate 1 and a capacitance is formed. The wiring connecting the cells is formed on the thick edge film 6. Note that when forming a p-type buried layer on an n-type silicon substrate, the n-type silicon substrate is
The p-type buried layer may be connected to the reference voltage circuit Vll.

The case where the n-type buried N3 and the n-type silicon N4 are electrically isolated from other regions using an insulating trench instead of the isolation layer 7 will be described below. Refer to FIG. 1c. Similarly to the above method, for example, an n-type buried layer 3 is formed on a p-type silicon substrate 1, and an n-type silicon layer 114 is formed on the n-type buried layer 3.
After forming, an n-type buried layer 3 is formed surrounding the capacitance formation region.
A separation trench is formed between the silicon oxide film and the n-type silicon N4, and a silicon nitride film is formed in the region where the extraction electrode 9 is formed, and is oxidized to form a thick silicon dioxide insulating film 6 and an insulating trench 10. Next, the silicon nitride film is removed, and an n-type impurity such as arsenic is ion-implanted to form an electrode contact region 8, and further, an extraction electrode 9 is formed. [Effects of the Invention] As explained above, in the ECL circuit according to the present invention, outside the cell formation region, a semiconductor layer of an opposite conductivity type is formed on a semiconductor layer of one conductivity type that forms one side of the power supply, and The semiconductor layer of one conductivity type is electrically isolated from other regions, a thick insulating film is formed on it, and the semiconductor layer of one conductivity type is connected to the base T41 voltage circuit through this thick insulating film. A capacitance is formed between a semiconductor layer and a semiconductor layer of the opposite conductivity type by a reverse bias applied to one TL'lH and a reference voltage circuit, so when forming a capacitance in a cell region, The degree of integration is improved compared to .

In addition, since the wiring that connects the cells of the ECL gate array is formed on a thick insulating film, parasitic capacitance is formed between the wiring and the semiconductor layer of the opposite conductivity type that constitutes one electrode of the capacitance. The switching speed is improved.

[Brief explanation of the drawing]

FIG. 1a is an ECL circuit diagram according to an embodiment of the present invention. FIGS. 1b and 1c are cross-sectional views of capacitors connected to an ECL circuit according to an embodiment of the present invention. FIG. 2 and FIG. 3 show the capacitor manufacturing process circle. FIG. 4 is a circuit diagram of the ECL basic form. FIG. 5 is a diagram showing the arrangement of the cell size area and wiring area of the ECL gate array. FIG. 6 is a cross-sectional view of a capacitor connected to an ECL circuit according to the prior art. One conductivity type semiconductor layer, resist layer, opposite conductivity type semiconductor layer (buried layer), opposite conductivity type semiconductor layer, silicon nitride layer, 6 ・ ・ 7 ・ 8 ・ 9 ・ 1l ・ 12 ・ 13 ・ 14 ・15. ・ T1 , ■o, ■3 ・ R,, C ・ ・ ・Thick insulating film, ・Separation layer, ・Electric scraping contact area, ・Extraction electrode, ・Insulating groove, ・Cell area, ・Wiring area, ・Thin Insulated olfactory, p-type expanded fPI. Layer, - constant current source, T2...transistor, VEt...power supply,...reference voltage circuit, R2...resistance, -electrostatic capacitance crab. V冫E Present invention Figure 10 Figure 2

Claims (1)

[Claims] A semiconductor layer (3) of an opposite conductivity type is formed on a semiconductor layer (1) of one conductivity type forming one electrode of a power source, and the semiconductor layer (3) of the opposite conductivity type is a semiconductor layer (3) of another conductivity type. a thick insulating film (6) on the semiconductor layer (3) of the opposite conductivity type;
is formed, and the opposite conductivity type semiconductor layer (3) is formed as the thick insulating film (6).
) and connected to the reference voltage circuit (V_R), and a reverse bias is applied between the semiconductor layer (1) of one conductivity type and the semiconductor layer (3) of the opposite conductivity type. Features an emitter-coupled logic circuit.