JPS60232796A - Logic circuit - Google Patents

Abstract

PURPOSE:To detect an error also in incorrect transfer data by conneting plural inversion circuits for inverting parity bits outputted from plural transmission registers, decoding a selecting singnal and inhibiting the operation of the inversion circuit corresponding to the transmission register to be selected. CONSTITUTION:The transmission registers 11-14 store 8-bit data and 1-bit parity bits. The 8-bit data outputs from the registers 11-14 are inputted to a selecting circuit 2 and parity bit outputs are inputted to the circuit 2 through the inversion circuits 71-74. The circuit 2 inputs selecting signals 41, 42, selects the outputs of an optional transmission register and its corresponding inversion circuit in accordance with the selecting signals and supplies the selected outputs to a receiving register 3. On the other hand, a decoder 5 inputs selecting signals 41', 42', decodes these signals and turns signal lines 61-64 corresponding to the transmission register to be selected to the high level. Consequently, the inversion circuit connected to the transmission register to be selected is inhibited at its inverting operation. Thus, an error can be detected even if the inversion circuit executes malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical field to which the invention pertains The present invention relates to a data processing device that uses one of a plurality of registers in a data processing device.
The present invention relates to a logic circuit that selects one and transfers data to a receiving register, and particularly relates to an improvement for accurately checking transferred data.

Prior Art Conventionally, as shown in FIG. 1, this type of logic circuit inputs the outputs of a plurality of transmit registers 11 to in to a selection circuit 2, and the selection circuit 2 selects an arbitrary register output according to a selection signal 4. The configuration is such that the received signal is inputted to the reception register 3. In order to check whether the transfer data has been transferred correctly, each transmit register adds a parity bit to the data bit and transfers the data, and the data stored in the receive register 3 is parity-checked by a check circuit (not shown). Ru.

In the conventional logic circuit described above, a data error occurring on a data transfer path can be immediately detected by a parity check. However, due to a failure in the 1 selection circuit 2, the wrong data in the transmit register is transferred to the receive register 3.
If the data is stored in the same format, the error cannot be detected by a parity check, so one erroneous data will be transferred as is, which will cause the data processing device to malfunction. It is extremely difficult to find the cause of this error, not only when it is detected by software, but even if invalid data is detected by hardware or firmware.

OBJECTS OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a logic circuit that can detect errors even when incorrect data is transferred due to a failure in a selection circuit or the like. .

Structure of the Invention The logic circuit of the present invention includes a plurality of transmitting registers that accumulate data bits and parity bits, and a selection circuit that selectively selects the outputs of the plurality of transmitting registers using a selection signal and supplies the selected outputs to a receiving register. , in a logic circuit comprising a reception register that stores an output of the selection circuit and a parity check circuit that checks data bits and parity bits of the reception register, each of the parity bits output from the plurality of transmission registers is inverted. The present invention is characterized by comprising a plurality of inversion circuits and a decoder that decodes the selection signal and inhibits the inversion operation of the inversion circuit corresponding to the transmission register to be selected.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

It is now assumed that each of the plurality of transmission registers 11-14 stores 8 bits of data and 1 bit of parity bit. The 8-bit data output of each transmitting register is input to the selection circuit 2, and the parity bit output of each transmitting register is input to the inverting circuits 71 to 74, respectively.
The 0 selection circuit 2 inputs the selection signals 41 and 42 to the selection circuit 2, selects the output of an arbitrary transmission register and its corresponding inverting circuit according to the selection signal, and sends the selected output to the reception register 3. supply On the other hand, the decoding circuit 5
inputs the selection signals 41' and 42', decodes them, and connects the signal line (61) corresponding to the transmission register to be selected.
~64) is set to high level. As a result, the inverting circuit connected to the transmission register to be selected is prohibited from inverting, and the other inverting circuits invert their respective parity bits and supply them to the selection circuit 2. For example, the selection signal 41,
42 or 'oo', the signal line 61 becomes "1" and all other signal lines become "°0". Therefore, the inverting circuit 71 changes the parity bit of the transmitting register 11. It is passed through as is and supplied to the selection circuit 2,
The inversion circuits 72 to 74 invert their respective pari bits and supply them to the selection circuit 2. Similarly, the selection signal is
In the case of ``'', the signal line 62 becomes ``L'', and ``J! When the interpretation signal is ``10'', the signal !163 becomes 1'', and when the selection signal is ``11'', the signal line 64 becomes ``l''.

Now, all data bits in transmit registers 11 to 14 are
'oooo oooo'', the parity bits are all ``1'', and the selection signal is 00'', the data in the transmitting register 11 is ``0000oo'', for example.
oo” and the parity bit “1” are output, and the inversion circuit 71 supplies the parity bit “1” to the selection circuit 2. Therefore, when the 1 selection circuit 2 correctly selects the transmission register 11, the output of the transmission register 11 data to be
ooo oooo” and the output “l” of the inversion circuit 71 are transferred to and stored in the reception register 3.Reception register 3
The data "oooo oooo" and the parity °°l" stored in the . when,
Since the selection circuit 2 selects the transmission register 13, the data “oooo oooo” and the inverted parity bit “o” output from the inversion circuit 73 are transferred to the reception register 3.
Of course, even if the 0 selection signals 41' and 42', which are transferred to the 0 and detected by the parity check circuit 8, are erroneous, an error will also be found.

Effects of the Invention As described above, in the present invention, inverting circuits are provided to invert the parity bits output from a plurality of transmitting registers, and the selection circuit receives data output from each transmitting register and the output of the inverting circuit. On the other hand, the selection signal is decoded to inhibit the inverting operation of the inverting circuit corresponding to the transmitting register to be selected. When transferred to the receiving register, it has the effect of detecting errors by parity checking.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of a conventional logic circuit, Figure 2 is a block diagram showing an example of a conventional logic circuit.
The figure is a block diagram showing one embodiment of the present invention. In the figure, 2: selection circuit, 3: reception register, 4.4
], 42.41', 42': Selection signal, 5: Decode circuit, 8: Parity check circuit, 11°12, +3
．． +4: Transmission register, 61, 62, 83, 84: Signal line, ? +, 72, 73.74: Inversion circuit. Applicant: NEC Corporation Agent, Patent Attorney: Toshimune Sumita), 11 yen, Fang 2 Diagram

Claims (1)

[Claims] a plurality of transmission registers that accumulate data bits and parity bits; a selection circuit that selectively selects the outputs of the plurality of transmission registers using a selection signal and supplies the selected signals to the reception register; and a reception circuit that stores the outputs of the selection circuits. A logic circuit comprising a register and a parity check circuit for checking data bits and parity bits of the reception register, the logic circuit comprising a plurality of inversion circuits for respectively inverting parity bits output from the plurality of transmission registers, and a plurality of inversion circuits for inverting the parity bits output from the plurality of transmission registers, and A logic circuit comprising: a decoder that inhibits an inversion operation of the inversion circuit corresponding to a transmission register to be decoded and selected.