JPS6022799A - Programmable monolithic integrated circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution and to attain a high level of integration by applying no current in a read mode to the collector side of a transistor (TR) which supplies a base current to the TR of the final stage of a decoder circuit and then applying the current in a write mode. CONSTITUTION:In a read mode the voltage within a logical voltage area is impressed to an external terminal EXT, but the inflow of a current is prevented by a Zener diode D5. Thus a TRQ6 and Q7 are turned off and on respectively together with a TRQ5 turned off respectively. Therefore a TRQ4 is actuated to lead in a read current of about 0.5mA from a WL1. While in a write mode, the voltage over the logical voltage area is impressed to the terminal EXT. Thus the diode D5 is turned on and a current is supplied to the TRQ5 via a resistance R9 as a base current. As a result, the TRQ6, Q7 and Q5 are turned on, off and on respectively. Therefore a current is supplied form a power supply Vcc through the TRQ5 and a resistance R6, and a base current which is enough for the TRQ4 of the final stage to lead in a current of about 200mA from the WL1 is supplied via a TRQ3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable monolithic integrated circuit;
For more information, see Programmable Read-Only Memory
The present invention relates to a decoder circuit of a programmable monolithic integrated circuit in which information is written by making each memory cell of a "FROM" conductive state (short-circuited) or non-conductive state (opened state) with a current.

Generally, a FROM is composed of an address inverter, a decoder, a memory cell, an output buffer, a programming circuit, etc. The memory cell is connected to each intersection of the word line and the T line, and generates heat due to the write current. There are two types: the junction destruction type, which shorts the emitter/reverse/base junction, and the heat type, which fuses the vapor-deposited metal or polycrystalline silicon with a write current.

In such programmable monolithic integrated circuits, as storage capacity increases, it is necessary to reduce the size of the memory cell portion and to simplify and downsize the decoder circuit.

FIG. 1 is a diagram showing an example of a conventional programmable monolithic integrated circuit, particularly a junction breakdown type P-OM.

In the figure, Gatel to Gate4 are inverters,
L1 to L4 are address signal lines, 1 is a decoder circuit, Q
t~Q4 is a transistor, ~RII is a resistor, Dl is a diode, 2 is a memory cell section, Qll~Q, , -
Q.

~Q□ is (mXn) memory cells, wI,, ~'W
Lm indicates a word line, and DL1 to DL indicate bit lines.

First, the write operation of the write circuit will be described using as an example a case where information is written by shorting the emitter-base junction of the memory cell Q1m of the memory cell section 2.

Address signal is inverter Ga t e 1 and Ga t
When applied to input terminals 3 and 3, the signal line goes to at.

~L4 is set to a level corresponding to the signal levels of Ao and A. That is, Ao is at a low level.

is the LOW level tosult L1 is at the high level, L is at the low level, L is at the high level, and L4 is at the low level. Memory cell Q to be selected
In a decoder circuit in which word lines WL to which 1□ are connected are connected, the emitters of multi-emitter transistor Q1 in the input stage are connected to address signal lines L1 and L3, and both are at H" level, so transistor Q1
is turned off and current is supplied from the power supply vec to the base of transistor Q through resistor 1, so transistor Q2 is turned on and transistors Qs and Ql are turned on, that is, WLI is selected. At this time, a write current of about 200 mA is applied to the memory cell Q+t, DLi-Ql, -
q-GND path, the emitter paste junction of memory cell Q11 is short-circuited, and writing is performed. At this time, a write current of approximately 20
A base current large enough to absorb 0mA flows,
The base current of the transistor Q4 is the transistor Q*
, Qs K is supplied.

Next, the read operation of this circuit will be described for the memory cell Q11 in which information is written as described above. To read information, it is sufficient to detect whether or not the memory cell QllK current flows, so there is no need to flow a large current through the bit line as in the above writing. That is, at the time of reading, a low level and an AtKlow level are applied to Ao, which turns off transistor Q, and transistors Q, , Q
,, Ql is turned on in the same way as during writing, but bit @DLl and word line WL1 have a read current of about 0.5 mA, which is much smaller than that during writing.
It flows along the path of DL IQ II-Ql-GND. At this time, the diode D1, which was off due to the high potential of the inclination WL during writing, is turned on during the read because WL is at a low potential. The base current of Q is smaller than that during writing, and therefore the base current of Q is small enough to draw a current of about 0.5 mA to WL.

The write current and read current are 200mA and 0.5
In FROM, which has a large difference in A, such as mA, if the base current of transistor Q4, which draws a read current even during reading, is made to flow with a base current large enough to draw a write current of 200 mA during writing, the base current will be excessive. In this case, the transistor Q4 becomes saturated and excessive charge is accumulated in the base, which lengthens the off time when Ql turns off, making it unsuitable for high-speed operation. In order to prevent this, in the conventional decoder circuit, a feedback circuit having a diode D1 is provided so that appropriate base currents are supplied to Ql during writing and reading, respectively. However, providing such a feedback circuit complicates the circuit configuration, which is not preferable for increasing the degree of circuit integration.

Also, as shown in Figure 1, the feedback circuit line transistor Q
In order to connect the collector of transistor Q2 and the collector of transistor Q4 via the diode DI, it is necessary to cross the wiring of transistor Q8, which has the disadvantage of complicating the wiring. Of course, the power supply ■ does not require such a feedback circuit. It is also possible to switch 0 between writing and reading, but since the power supply VCC is a voltage that is supplied not only to the decoder but also to other circuits, switching VCC should be done in conjunction with other circuit designs. There is a limit.

SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional drawbacks and provide a programmable monolithic integrated circuit that has a simple circuit configuration and can be highly integrated.

The feature of the present invention is that the progera i pull
In a monolithic integrated circuit, when reading a selected memory cell, no current is applied to the erector side of the transistor that supplies the base current of the final stage transistor of the decoder circuit connected to the word line, and when writing, the final stage transistor applies the write current. The goal is to apply a current that will create a base current large enough to absorb the current.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of a programmable monolithic integrated circuit according to the present invention, particularly a decoder circuit in which word lines WLl are connected, and the same reference numerals as in FIG. 1 indicate the same elements. Although memory cells other than QIs are not shown,
It exists in the same way as in Figure 1.

Features of this example circuit ← No transistor Q and feedback circuit via diode DI, final stage transistor Q
The external terminal EXT is provided at the collector portion of the transistor Q, which supplies the base current to the transistor Q4, via the transistors Q, Q, Q, Q, which have resistors R6 to R1, and the Zener diode island.

In such a circuit, when reading, the external m
X 'I' Kftalji within voltage range (-0,5V~+
5. sV)ノ! If pressure is applied, the Zener diode D blocks the inflow of the current, turning off the transistor Q6, turning on the transistor Qy, and turning off the transistor Q5. Therefore, the transistor Q4 is operated only by the base current supplied by the current flowing from VCC through the resistor R+1) transistor Q1 and the current flowing from VCC through the resistor R,,) transistor Q3.
A read current of about 0.5 mA is drawn from L. On the other hand, during writing, the voltage is higher than the logic voltage range (for example, 12
) is applied to EXT, the Zener diode is turned on, and a current is supplied as the base current of the transistor Q6 through the resistor 9, turning on the transistor Q6, turning off the transistor Qy, and turning on the transistor Qs.

Therefore, current flows from the power supply VCC through the transistor Qs1 and the resistor R6, and the final stage transistor Q4 is 200 m
A base current of sufficient magnitude to draw a current of ~VL as much as A is supplied through transistor Q3.

In this way, by supplying the base current of the final stage transistor Q4 at the time of 1 loading, a feedback circuit like the conventional circuit is not required, and the number of stages is increased to supply a stain current other than the decoder circuit and the current can be amplified. There is no need to perform this process, and the number of stages can be reduced.

However, in FIG. 2 showing an embodiment according to the present invention, it is sufficient to apply a voltage within the logical voltage range to the external terminal EXT for the read operation.FIEXT is shared with the input terminal in order to save the number of terminals. Can be used with conventional FR
A read operation similar to an OM is possible, but in addition to the write specifications of a conventional FROM, a voltage higher than the logic voltage range must be applied to the external terminal EXT during a write operation.
It has the disadvantage that the write specifications are different from OM.

In the present invention, in order to overcome this drawback, the write current is
A pass circuit is provided to bypass the circuit (for example, t!, Attention was paid to the fact that the read operation and write specifications similar to those of conventional FROM are possible at both time and write.

This will be explained using FIG. 3, which shows a second embodiment of the present invention. Although FIG. 3 does not show the inverter or memory cells other than 91m, it is similar to FIG. 1.

During a read operation, transistor Q6 is turned off and transistor Q is turned on, and during a write operation, a portion of the write current applied to the output terminal is transferred to the PNP transistor Q.
tt, turns on the Zener diode D, turns on the transistor Qso y Qu, and turns on the resistors R1,..., R.
11! Transistor Q, so that the potential difference across resistor R12 at that time, flowing into
-Q□, resistances R11 to R0,.

When diode D1 and Zener diode D are set, transistor Q6 turns on during writing, and transistor Q
, is turned on, and during reading, transistor Q6 is turned off and transistor Q is turned on.

Therefore, during reading, transistor Q is turned off and v
Current flows from cc through resistor 1 and transistor Q1, and from VCC through resistor I (!, transistor Q.

Transistor Q4 is operated only by the base current supplied by the current flowing through WLl to 0.
A readout current of about 5mA is drawn. On the other hand, during writing, the transistor Q is turned on, and current flows from the power supply VCC through the transistor Qs and the resistor kL, and the base current of the transistor Q is large enough for the final stage transistor Q4 to draw a current of about 200 mA from the transistor Q.
8.

As explained above, according to the present invention, the base percentage of the final stage transistor of the decoder circuit is
Since a feedback circuit for switching the L current is not required, a programmable monolithic integrated circuit with a simple circuit configuration and mask design during manufacturing and a high degree of integration can be obtained, and the effects of the present invention are enormous.

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional programmable monolithic integrated circuit, FIG. 2 shows a non-inventive embodiment, and FIG. 3 shows a second embodiment of the present invention. Q, ~Q4...Transistor, DI...
·diode.

Claims (3)

[Claims] (1) Corresponds to the collector section of the transistor that supplies the base current of the final stage transistor of the decoder circuit connected to the word line in a programmable monolithic integrated circuit that writes information by making the memory cell conductive or non-conductive. A programmable monolithic integrated circuit characterized by having a circuit that supplies current only when writing to a memory cell. (2) The current and the supply circuit are controlled by an external terminal other than the terminal to which programming power is applied in order to write information to the memory cell/L-. Programmable monolithic integrated circuit. (3) The programmable monolithic integrated circuit according to claim (1), wherein the circuit for supplying the current is controlled by a terminal that applies programming power to write information to the memory cell. .