JPH06325577A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the delay time of data read extremely by installing a current detection type sense amplifier to a semiconductor storage device having BiCMOS constitution and bringing the voltage of a common data line on the side, through which currents do not flow, to a approximately the same value as the voltage of a bit line connected to a common data line on the side, through which currents flow, at the time of read by using the sense amplifier. CONSTITUTION:A current detection type sense amplifier 52 is mounted on a storage device, the sources of PMOS transistors 44a, 44b constituting the sense amplifier 52 are connected to the drains of PMOS transistors 41b, 41a respectively, and the voltage of the bit line of one of selected columns and the bit line of the other is made to be the same or approximately the same at the time of read. That is, the source of the transistor 44a is connected to the drain of the transistor 41b without being bonded with a VRS voltage line, and the source of the transistor 44b is also connected to the drain of the transistor 41a without being bonded with the VRS voltage line. A write data Din input to a data input terminal 10 is selected while using a write control signal/WE as 'L' at the time of write.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a BiCMOS structure provided with a so-called current detection type sense amplifier.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device of this type,
For example, there is known one whose main part is shown in FIG.

This semiconductor memory device is a so-called SRAM.
(Static random access memory), in the figure, 1 is a chip body, and 2 is a memory cell array section in which memory cells are arranged.

Further, 3 ₀ and 3 _n are row address signals X ₀ ,
A row address signal input terminal 4 to which X _n is input is a row decoder which decodes the row address signals X ₀ ... X _n to select a word line.

Further, 5 ₀ and 5 _m are column address signal input terminals to which the column address signals Y ₀ and Y _m are input, and 6
Is a column decoder which decodes the column address signals Y ₀ ... Y _m and outputs a column selection signal for selecting a column.

Further, 7 is a column selection circuit for selecting a column based on a column selection signal output from the column decoder 6, and 8 is detection of data read from the memory cell array section 2 via the column selection circuit 7. A sense amplifier / write circuit unit including a sense amplifier for performing the above and a write circuit for writing data.

Further, 9 is a data output terminal for outputting the read data D _OUT , 10 is a data input terminal for inputting the write data D _IN , and 11 is a write control signal / WE.
Is a write control signal input terminal to which is input.

[0008] Here, FIG. 8 is a circuit diagram showing a memory cell array 2 and the column selection circuit 7, 12 _0, 12 _x
Are columns constituting the memory cell array section 2, 13 ₀ , 1
3 _y is a word line for selecting a memory cell.

Further, 14 ₀ and 14 _X are column switch circuits constituting the column selection circuit 7, and 15a and 15b are common data lines provided so as to be shared by the columns 12 ₀ ... 12 _X of the memory cell array section 2. Is.

In column 12 ₀ , 16 ₀ , 16
_y is a memory cell for storing data, 17a and 17b are data writing to the memory cells 16 ₀ ... 16 _y ,
Bit lines used to read data from the memory cells 16 ₀ ... 16 _y .

In the memory cells 16 ₀ and 16 _y ,
18 ₀ and 18 _y are resistance load type flip-flop circuits, and 19 ₀ and 19 _y are VCC power supply lines for supplying a power supply voltage VCC (0 [V]).

[0012] In _{addition, 20 0a, 20 0b, 20} ya, 20 yb nMOS transistor is a driving transistor, 21
_{0a, 21 0b, 21 ya,} 21 yb is the load resistance, VEE denotes a power source voltage of the low voltage side (-4.5 [V]).

Further, 22 _0a and 22 _0b are nMOS transistors forming transfer gates whose ON (ON: conduction) and OFF (OFF: conduction) are controlled via the word line 13 ₀ , and 22 _ya and 22 _yb are NM forming a transfer gate whose on / off is controlled via the word line 13 _y
It is an OS transistor.

Further, in the column switch 14 ₀ , 2
3a and 23b are analog switches, and 24a and 24
b is a pMOS transistor, 25a and 25b are nMOS
It is a transistor.

CL ₀ is a column selection signal, 26 is an inverter, 27a and 27b are bit lines 17a and 27a, respectively.
The pMOS transistor and VRC forming the load of 17b are a constant voltage (-1.6 [V]).

FIG. 9 is a circuit diagram showing the sense amplifier / write circuit section 8. Reference numeral 28 is a sense amplifier and 29 is a write circuit. In the write circuit 29, 30 is A.
ND / NAND circuits and 31, 32 are NOR circuits.

In the sense amplifier 28, 33 is a VCC power supply line, 34a and 34b are NPN transistors,
35a and 35b are load resistors, 36 is a constant current source, and these NPN transistors 34a and 34b and the load resistor 3
A differential amplifier 37 is composed of 5a and 35b and a constant current source 36.

Numerals 38a and 38b are sense amplifier output terminals for outputting the sense amplifier outputs S _OUT and / S _OUT .

Further, 39a, 39b, 40a, 40b are VRS voltage lines for supplying a constant voltage VRS (-0.8 [V]), 41a, 41b are common data lines 15a, 1 respectively.
5b is a pMOS transistor forming a load.

Further, 42a is an NPN transistor for driving the common data line 15a, 43a is a high resistance, and the NPN transistor 42a and the high resistance 43a constitute an emitter follower circuit.

Further, 42b is an NPN transistor for driving the common data line 15b, 43b is a high resistance, and the NPN transistor 42b and the high resistance 43b constitute an emitter follower circuit.

Further, 44a is a pMOS transistor, 4
Reference numeral 5a is an nMOS transistor, and the pMOS transistor 44a and the nMOS transistor 45a form an inverter.

Further, 44b is a pMOS transistor, 4
Reference numeral 5b is an nMOS transistor, and the pMOS transistor 44b and the nMOS transistor 45b form an inverter. Incidentally, 46a and 46b are nMOS transistors for writing.

In this SRAM thus configured, at the time of writing, the write control signal / WE is set to "L" and the write data D _IN is input to the data input terminal 10 to select the selected memory cell. Is written to.

[0025] In this case, depending on the value of the write data D _IN, one of the NOR circuits 31 and 32 is "H", but the other is "L", for example, the write data D _IN =
When “0” = “L”, the output of the NOR circuit 31 =
“H”, the output of the NOR circuit 32 = “L”.

As a result, the pMOS transistor 44a =
OFF, nMOS transistor 45a = ON, N
The PN transistor 42a is turned off and nM
The OS transistor 46a is turned on.

Further, the pMOS transistor 44b = 0
N, nMOS transistor 45b = OFF, NP
The N-transistor 42b is turned on and the nMOS is turned on.
The transistor 46b is turned off.

Here, for example, when the memory cell 16 ₀ is selected, in the column switch circuit 14 ₀ , the column selection signal CL ₀ = “L”, the output of the inverter 26 =
It is set to "H".

As a result, the analog switches 23a, 23
b = ON, pMOS transistors 27a, 27b = OF
F, bit lines 17a and 17b, and common data line 1
5a and 15b are respectively connected.

In the other column switch circuits, the analog switches corresponding to the analog switches 23a and 23b are turned off, and the bit lines are separated from the common data lines 15a and 15b.

Further, in the memory cell array section 2,
The voltage of the word line 13 ₀ is set to “H”, and the memory cell 16 ₀
, NMOS transistors 22 _0a and 22 _0b = O
N.

As a result, from the VCC power supply line 19 ₀ to the load resistance 21 _0a , the nMOS transistor 22 _0a and the bit line 17
a, analog switch 23a, common data lines 15a, n
A current flows to the VEE power supply line via the MOS transistor 46a, and the voltage of the common data line 15a and the bit line 17a is lowered to about VEE = about −4.5 [V].

On the other hand, in the sense amplifier 28, pM
Since the OS transistor 44b = ON, the nMOS transistor 45b = OFF, the NPN transistor 42b = ON, and the nMOS transistor 46b = OFF, the common data line 15b and the bit line 17 are set.
The voltage of b is approximately VRS-VBE = approximately -1.6 [V].

As a result, the nMOS transistor 20 _0b is forcibly turned off and the nMOS transistor 20 _0a is forcibly turned on, that is, the voltage of the node 47 _0a = “L”, the node 4
The voltage of 70 _b is set to “H”, and the write data “0” is written to the memory cell 16 ₀ .

When the write data D _IN = “1”, the operation on the common data line 15a side and the common data line 15
Writing is performed in the same manner as described above, except that the operation on the b side is reversed.

On the other hand, at the time of reading, the write control signal / WE is set to "H", the outputs of the NOR circuits 31 and 32 are set to "L", and the pMOS transistors 44a and 44b are set to O.
N, nMOS transistors 45a, 45b, 46a, 4
6b = OFF.

As a result, the NPN transistors 42a, 4
The base voltage of 2b is approximately VRS = approximately −0.8 [V] via the pMOS transistors 44a and 44b, respectively.
Therefore, the voltages of the common data lines 15a and 15b are both approximately VRS-VBE (base of the NPN transistor.
The voltage between the emitters) is approximately -1.6 [V].

Since the NPN transistor 42a and the high resistance 43a constitute an emitter follower circuit, the VRS voltage line 39a is connected to the pMOS transistor 41.
A small current always flows through the VEE power line through the a, the NPN transistor 42a and the high resistance 43a, and the common data line 1
The voltage of 5a is maintained at about VRS-VBE = about -1.6 [V].

Further, since the emitter follower circuit is composed of the NPN transistor 42b and the high resistance 43b, the pMOS transistor 41 is connected from the VRS voltage line 39b.
b, a small current always flows through the VEE power line through the NPN transistor 42b and the high resistance 43b, and the common data line 1
The voltage of 5b is also maintained at about VRS-VBE = about -1.6 [V].

Here, for example, when the memory cell 16 ₀ is selected, in the column switch circuit 14 ₀ , the column selection signal CL ₀ = “L”, the output of the inverter 26 =
It is set to "H".

As a result, the analog switches 23a, 23
b = ON, pMOS transistors 27a, 27b = OF
F, bit lines 17a and 17b, and common data line 1
5a and 15b are respectively connected.

In the other column switch circuits, the analog switches corresponding to the analog switches 23a and 23b are turned off, and the bit lines are separated from the common data lines 15a and 15b.

Further, in the memory cell array section 2,
The voltage of the word line 13 ₀ is set to “H”, and the nMOS transistor forming the transfer gate of the memory cell connected to the word line 13 ₀ is turned on. That is, in the memory cell 16 ₀ , the nMOS transistor 22 _0a ,
22 _0b = ON.

Here, for example, the nMOS transistor 2
0 _0a = ON, nMOS transistor 20 _0b = OFF, that is, node 47 _0a = “L”, node 47 _0b = “H”, and this memory cell 16 ₀ stores data “0”. And

Then, from the VRS voltage line 39a to the pMOS
Transistor 41a, NPN transistor 42a, common data line 15a, analog switch 23a, bit line 1
7a and nMOS transistors 22 _0a and 20 _0a
Current flows to the EE power line.

As a result, the drain voltage of the pMOS transistor 41a is approximately VRS-ΔVR (voltage drop due to the on resistance of the pMOS transistor 41a) = approximately -0.8.
[V] −ΔVR, and the voltage of the bit line 17a is approximately V
RS-VBE- [Delta] VA (voltage drop due to the on resistance of the analog switch 23a) = approximately -1.6 [V]-[Delta] VA.

On the other hand, from the bit line 17b to the memory cell 16
Since no current flows into ₀ , no current flows into the pMOS transistor 41b and the pMOS transistor 4b
The drain voltage of 1b is approximately VRS = approximately −0.8 [V], and the voltage of the bit line 17b is approximately VRS−VB.
E = approximately -1.6 [V].

In the meantime, the differential amplifier 37 has the pMOS
The difference between the drain voltage of the transistor 41a and the drain voltage of the pMOS transistor 41b is detected, and the sense amplifier output S _OUT = “H”, / S _OUT = “L” corresponding to the data stored in the memory cell 16 ₀ is output. To be done.

Here, in FIG. 10, in this SRAM, the memory cell 16 ₀ storing “0” at the time of reading.
After (node 47 _0a = “L”, node 47 _0b = “H”) is selected, the memory cell 16 _y that stores “1” (node 47 _ya = “H”, node 47 _yb ) is selected. =
FIG. 7 is a waveform diagram showing an operation when “L”) is selected.

In the figure, the solid line 48 is the voltage of the bit line 17a,
The solid line 49 is the voltage of the bit line 17b, and the solid line 50 is the pMOS.
The drain voltage of the transistor 41a, the solid line 51 is pMO
The drain voltage of the S transistor 41b is shown.

Here, when the memory cell 16 ₀ storing “0” is selected at the time of reading and then the memory cell 16 _y storing “1” is selected, No current flows from the bit line 17a to the memory cell 16 ₀ .

As a result, the voltage of the bit line 17a is approximately V
RS-VBE-ΔVA = approximately -1.6 [V] -ΔVA is raised toward approximately VRS-VBE = approximately -1.6 [V], and the drain voltage of the pMOS transistor 41a is approximately VRS-ΔVR. = Approx. -1.6 [V] -ΔVR
To rise towards VRS.

On the other hand, on the bit line 17b side, from the VRS line 39b to the pMOS transistor 41b,
NPN transistor 42b, the common data line 15b, the analog switches 23b, the bit line 15b, current flows in the nMOS transistor 22 _yb, 20 VEE power supply line via a _ya.

As a result, the voltage of the bit line 17b is approximately V
RS-VBE = approximately-1.6 [V] to approximately VRS-VBE
−ΔVA = approximately −1.6 [V] −Lowered toward ΔVA, and the voltage of the pMOS transistor 41b is
Approximately VRS−ΔVR = reduced toward approximately −0.8 [V] −ΔVR.

Meanwhile, in the differential amplifier 37, p
The drain voltage of the MOS transistor 41a and pMO
A difference from the voltage of the drain of the S-transistor 41b is detected, and sense amplifier outputs S _OUT = “L” and / S _OUT = “H” corresponding to the data stored in the memory cell 16 _y are output.

[0056]

As described above, this SR
In AM, when reading, within the same column,
When different memory cells are continuously selected, such as when memory cells that store different values as data are continuously selected, the selected column and the data value stored in the selected memory cell Depending on the relationship, the bit line voltage of the selected column changes greatly, so it takes a considerable time to charge and discharge the parasitic capacitance of the bit line, which hinders the speeding up of data reading. .

In this SRAM, the voltage of the common data lines 15a and 15b is set to approximately VRS-V during reading.
BE = approximately -1.6 [V] can be maintained,
Column selection circuit 7 such as analog switches 23a and 23b
If the on-resistance of the analog switch that makes up the circuit can be made substantially zero, the voltage change of the bit line can be made substantially zero, and the time required for charging / discharging the parasitic capacitance of the bit line can be made substantially zero. The speed can be increased.

However, in order to make the on resistance of the analog switch forming the column selection circuit 7 substantially zero, pM
OS transistor 24a, nMOS transistor 25a
It is necessary to make the gate widths of the transistors forming these analog switches considerably large, and the area occupied by the column selection circuit 7 must be made considerably large. Therefore, there is a limit in performing this in relation to the chip area. However, after all, it is impossible to make the on resistance of these analog switches substantially zero.

It should be noted that if the parasitic capacitance of the bit line can be reduced, the speed of data reading can be increased, but the bit line is originally long and connected to a large number of memory cells. Therefore, it is impossible to reduce the parasitic capacitance.

In view of the above point, the present invention sets the voltage change (amplitude) of the bit line of the selected column to zero or minute at the time of reading, so that the data reading is performed by charging / discharging the parasitic capacitance of the bit line. It is an object of the present invention to provide a semiconductor memory device in which the delay time is set to be zero or minute and the speed of data reading can be increased.

[0061]

In a semiconductor memory device according to the present invention, first and second bit lines and first and second data input / output terminals are connected to the first and second bit lines, respectively. A plurality of memory cells are provided so that, when selected at the time of reading, a current flows from either the first or second data input / output terminal according to the data to be stored. Column and a plurality of columns corresponding to these columns, and the first ends of the columns are connected to the first and second bit lines, respectively, and on / off control is performed based on a column selection signal. Provided corresponding to the first and second connection switch elements, and the plurality of columns,
The first and second common data lines connected to the second ends of the first and second connection switch elements and the currents flowing through the first and second common data lines at the time of reading, respectively. In a semiconductor memory device configured to include a sense amplifier that detects data stored in a selected memory cell by detecting, the sense amplifier is improved.

That is, in the present invention, the sense amplifier causes the voltage of the first common data line to be related to the voltage of the voltage detection point on the second common data line side for data detection during reading, The voltage of the second common data line is configured to be related to the voltage of the voltage detection point on the side of the first common data line for data detection.

[0063]

As described above, in the present invention, the sense amplifier causes the voltage of the first common data line to be related to the voltage of the voltage detection point on the second common data line side at the time of reading, and the second common data line. Since the voltage of the line is configured to be related to the voltage at the voltage detection point on the side of the first common data line, the voltage of the common data line on the side on which no current flows at the time of reading is set to the common data on the side on which the current flows. The voltages of the bit lines connected to the lines can be the same or substantially the same, and the voltages of the first and second bit lines of the selected column can be the same or substantially the same.

As a result, at the time of reading, the voltage change of the first and second bit lines of the selected column is set to zero or minute, and the delay time of data reading due to charging and discharging of the parasitic capacitance of the bit line is set to zero or. It can be minute.

[0065]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
A case in which the present invention is applied to an SRAM will be described as an example, together with the embodiments to the fourth embodiment. In FIGS. 1 and 3 to 6, parts corresponding to those in FIGS. 8 and 9 are designated by the same reference numerals,
The duplicate description will be omitted.

First Embodiment FIG. 1 and FIG. 2 FIG. 1 is a circuit diagram showing a main part of the first embodiment of the present invention.
3 illustrates a sense amplifier / write circuit unit provided in the first embodiment of the present invention.

In the first embodiment, a sense amplifier 52 which is an improvement of the sense amplifier 28 shown in FIG. 9 is provided, and the other parts are the conventional SRAM shown in FIG.
Is configured similarly to. Therefore, the memory cell array section 2 and the column selection circuit 7 are also configured as shown in FIG.

Here, in the sense amplifier 52, p
The source of the MOS transistor 44a is not connected to the VRS voltage line, but is connected to the drain of the pMOS transistor 41b.

The source of the pMOS transistor 44b is also not connected to the VRS voltage line, but is connected to the drain of the pMOS transistor 41a. Others are the same as those of the sense amplifier 28 shown in FIG.

In the first embodiment thus constructed, the write control signal / WE is set to "L" at the time of writing to select the write data D _IN input to the data input terminal 10. Writing to the memory cell is performed.

[0071] In this case, depending on the value of the write data D _IN, one of the NOR circuits 31 and 32 is "H", but the other is "L", for example, the write data D _IN =
When “0” = “L”, the output of the NOR circuit 31 =
“H”, the output of the NOR circuit 32 = “L”.

As a result, the pMOS transistor 44a =
OFF, nMOS transistor 45a = ON, N
The PN transistor 42a is turned off and nM
The OS transistor 46a is turned on.

Further, the pMOS transistor 44b = 0
N, nMOS transistor 45b = OFF, NP
The N-transistor 42b is turned on and the nMOS is turned on.
The transistor 46b is turned off.

Here, for example, when the memory cell 16 ₀ is selected, in the column switch circuit 14 ₀ , the column selection signal CL ₀ = “L”, the output of the inverter 26 =
It is set to "H".

As a result, the analog switches 23a, 23
b = ON, pMOS transistors 27a, 27b = OF
F, bit lines 17a and 17b, and common data line 1
5a and 15b are respectively connected.

In the other column switch circuits, the analog switches corresponding to the analog switches 23a and 23b are turned off, and the bit lines are separated from the common data lines 15a and 15b.

Further, in the memory cell array section 2,
The voltage of the word line 13 ₀ is set to “H”, and the memory cell 16 ₀
, NMOS transistors 22 _0a and 22 _0b = O
N.

As a result, from the VCC power supply line 19 ₀ to the load resistance 21 _0a , the nMOS transistor 22 _0a and the bit line 17
a, analog switch 23a, common data lines 15a, n
A current flows to the VEE power supply line through the MOS transistor 46a, and the voltage of the bit line 17a is approximately VEE = approximately −4.
It is lowered to 5 [V].

On the other hand, in the sense amplifier 52, pM
Since the OS transistor 44b = ON, the nMOS transistor 45b = OFF, the NPN transistor 42b = ON, and the nMOS transistor 46b = OFF, the common data line 15b and the bit line 17 are set.
The voltage of b is approximately VRS-VBE = approximately -1.6 [V].

As a result, the nMOS transistor 20 _0b is forcibly turned off and the nMOS transistor 20 _0a is forcibly turned on, that is, the voltage of the node 47 _0a = “L”, the node 4
The voltage of 70 _b is set to “H”, and the write data “0” is written to the memory cell 16 ₀ .

Further, write data D _IN = “1”
In the case of ("H"), writing is performed in the same manner as described above, only the operation on the common data line 15a side and the operation on the common data line 15b side are reversed.

On the other hand, at the time of reading, the write control signal / WE is set to "H", the outputs of the NOR circuits 31 and 32 are set to "L", and the pMOS transistors 44a and 44b are set to O.
N, nMOS transistors 45a, 45b, 46a, 4
6b = OFF.

Here, for example, when the memory cell 16 ₀ is selected, in the column switch circuit 14 ₀ , the column selection signal CL ₀ = “L”, the output of the inverter 26 =
It is set to "H".

As a result, the analog switches 23a, 23
b = ON, pMOS transistors 27a, 27b = OF
F, bit lines 17a and 17b, and common data line 1
5a and 15b are respectively connected.

In the other column switch circuits, the analog switches corresponding to the analog switches 23a and 23b are turned off and the bit lines are separated from the common data lines 15a and 15b.

Further, in the memory cell array section 2,
The voltage of the word line 13 ₀ is set to “H”, and the memory cell 16 ₀
, NMOS transistors 22 _0a and 22 _0b = O
N.

Here, for example, the nMOS transistor 2
0 _0a = ON, nMOS transistor 20 _0b = OFF, that is, node 47 _0a = “L”, node 47 _0b = “H”, and this memory cell 16 ₀ stores “0”. To do.

Then, from the VRS voltage line 39a to the pMOS
Transistor 41a, NPN transistor 42a, common data line 15a, analog switch 23a, bit line 1
7a and nMOS transistors 22 _0a and 20 _0a
Current flows to the EE power line.

As a result, the drain voltage of the pMOS transistor 41a is approximately VRS-ΔVR (voltage drop due to the on-resistance of the pMOS transistor 41a) = approximately -0.8.
[V] −ΔVR.

On the other hand, from the bit line 17b to the memory cell 16
Since no current flows into ₀ , no current flows into the pMOS transistor 41a and the pMOS transistor 4a
The drain voltage of 1b is approximately VRS = approximately −0.8 [V].

As a result, the voltage of the common data line 15a becomes
Approximate VRS-VBE = Approximately -1.6 [V], bit line 17a
Is approximately VRS-VBE-ΔVA (voltage drop due to ON resistance of the analog switch 23a) = approximately -1.6.
It becomes [V] -ΔVA.

In addition, the common data line 15b and the bit line 1
The voltage of 7b is approximately VRS−ΔVR−VBE = approximately −1.6.
[V] −ΔVR.

Therefore, in the first embodiment, ΔV
The gate widths of the pMOS transistor 24a, the nMOS transistor 25a, and the pMOS transistor 41a are set so that A = ΔVR = ΔV.

The pMOS transistor 24b and nM
OS transistor 25b and pMOS transistor 41b
The same applies to the above, and in other column switch circuits, pMOS transistor 24a, nMOS transistor 25a, pMOS transistor 24b, nM
Transistor corresponding to OS transistor 25b and pM
The same applies to the OS transistors 41a and 41b.

As a result, the voltage of the common data line 15a = approximately VRS-VBE = approximately -1.6 [V], the common data line 15
Voltage of b = approximately VRS−ΔV−VBE = approximately −1.6 [V]
−ΔV, voltage of bit line 17a = approximately VRS−ΔV−VB
E = approximately -1.6 [V] -ΔV, voltage of bit line 17b =
About VRS−ΔV−VBE = about −1.6 [V] −ΔV, and the voltage of the bit line 17a and the voltage of the bit line 17b are substantially the same.

In the meantime, the differential amplifier 37 has pMOS
The difference between the drain voltage of the transistor 41a and the drain voltage of the pMOS transistor 41b is detected, and the sense amplifier output S _OUT = “H”, / S _OUT = “L” corresponding to the data stored in the memory cell 16 ₀ is output. To be done.

FIG. 2 shows a memory cell 16 ₀ storing "0" at the time of reading in the first embodiment.
After (node 47 _0a = “L”, node 47 _0b = “H”) is selected, the memory cell 16 _y that stores “1” (node 47 _ya = “H”, node 47 _yb ) is selected. =
FIG. 7 is a waveform diagram showing an operation when “L”) is selected.

In the figure, the solid line 56 is the voltage of the bit line 17a,
The solid line 57 is the voltage of the bit line 17b, and the solid line 58 is the pMOS.
The drain voltage of the transistor 41a, the solid line 59 is pMO
The drain voltage of the S transistor 41b is shown.

Here, when the memory cell 16 ₀ storing “0” is selected at the time of reading, and subsequently the memory cell 16 _y storing “1” is selected, no current flows in the memory cell 16 ₀ from the bit line 17a, the drain voltage of the pMOS transistor 41a is
It rises toward the constant voltage VRS.

On the other hand, on the bit line 17b side, from the VRS line 39b to the pMOS transistor 41b,
A current flows to the VEE power supply line through the NPN transistor 42b, the common data line 15b, the analog switch 23b, the bit line 17b, and the nMOS transistors 22 _0b and 20 _0b .

In this case, the voltage of the bit line 17b starts to drop due to the ON resistance of the analog switch 23b, but as described above, the drain voltage of the pMOS transistor 41a rises toward the constant voltage VRS.
The voltage on the bit line 17b drops once, then
Promptly, about VRS-ΔV-VBE = about -1.6 [V]
-Returned to ΔV.

On the other hand, the common data line 15a and the bit line 1
Since no current flows through 7a, its voltage is the drain voltage of the pMOS transistor 41b before the voltage drop of ΔV-the base-emitter voltage of the NPN transistor 42a, that is, about VRS-VBE = about -1.6. It begins to rise toward [V].

However, the drain voltage of the pMOS transistor 41b is approximately VRS−ΔV = approximately −0.8 [V] −Δ.
Since it becomes V, the common data line 15a and the bit line 17a
Voltage rises a little, and then quickly rises to about V
RS-ΔV-VBE is returned to approximately −1.6 [V] −ΔV.

In the meantime, the differential amplifier 37 has pMOS
The difference between the drain voltage of the transistor 41a and the drain voltage of the pMOS transistor 41b is detected, and the sense amplifier output S _OUT = “L”, / S _OUT = “H” corresponding to the data stored in the memory cell 16 _y is output. To be done.

At the time of reading, the memory cell 16 ₀ storing “0” (node 47 _0a = “L”, node 47 _0b).
= “H”) is selected, and subsequently, the case where the memory cell of the column 12 _x selected by the word line 13 _y is selected will be described.

However, in the column 12 _x , the memory cell selected by the word line 13 ₀ stores “0” like the memory cell 16 ₀ (node 47 _0a = “L”, node 47 _0b = “H”). However, it is assumed that the memory cell selected by the word line 13 _y stores “1” similarly to the memory cell 16 _y (node 47 _ya = “H”, node 47 _yb = “L”).

[0107] pMO this case, while the column 12 ₀ is selected, in the column switch circuit 14 _x, corresponding to the pMOS transistor 27a from the VRC voltage line
S-transistor, bit line corresponding to bit line 17a,
Current flows to the VEE power supply line through the nMOS transistors 22 _0a and 20 _0a .

If the gate width of this pMOS transistor is set so that the voltage drop due to the on-resistance of the pMOS transistor corresponding to the pMOS transistor 27a becomes ΔV, the voltage of the bit line corresponding to the bit line 17a is set. Is approximately VRC−ΔV = approximately −1.6 [V] −Δ
It becomes V.

On the other hand, since no current flows in the bit line corresponding to the bit line 17b, its voltage is approximately VR.
C = approximately -1.6 [V].

[0110] As a result, the voltage of the bit line corresponding to the bit line 17a in the case where the memory cells selected by the word line 13 _y of the column 12 _x is selected, the bit line 1
7b, the voltage of the bit line, the drain voltage of the pMOS transistor 41a, and the pMOS transistor 41a.
The drain voltage of b is the same as that shown in FIG.

That is, the voltage of the bit line corresponding to the bit line 17a changes as shown by the solid line 56 in FIG. 2, and the voltage of the bit line corresponding to the bit line 17b changes in the solid line 57 in FIG.
It changes as shown in.

Thus, in this first embodiment,
When reading, set the voltage of the common data line where the current does not flow to
The voltage of the bit line connected to the common data line on which the current flows (approximately VRS-VBE-ΔV = approximately -1.6 [V]
-ΔV) and the voltages of the bit lines on one side and the other side of the selected column are substantially the same voltage (approximately VRS-VBE-).
ΔV = approximately −1.6 [V] −ΔV) can be set.

As a result, according to the first embodiment, at the time of reading, the voltage change of the bit line of the selected column is made minute and the delay time of data reading due to the charging / discharging of the parasitic capacitance of the bit line is made minute. Therefore, the speed of data reading can be increased.

Second Embodiment ... FIG. 3, FIG. 4 FIGS. 3 and 4 are circuit diagrams showing the essential parts of a second embodiment of the present invention. FIG. 3 shows the second embodiment of the present invention. FIG. 4 shows a sense amplifier / write circuit section, and FIG. 4 shows a memory cell array section 2 and a column selection circuit 7 included in the second embodiment of the present invention.

That is, the second embodiment is provided with a sense amplifier 53 which is an improvement of the sense amplifier 52 shown in FIG. 1. Correspondingly, as shown in FIG. 4, the column switch circuit 14 _{0 is provided.} , A constant voltage VRS (-0.8 is applied to the sources of the pMOS transistors 27a and 27b.
[V]).

The same applies to the other column switch circuits. Others are the same as those of the first embodiment shown in FIG.

Here, in the sense amplifier 53, p
The source of the MOS transistor 41a is not connected to the VRS voltage line, but is connected to the VCC power supply line 33, and the drain of the pMOS transistor 41a is
It is not directly connected to the base of the NPN transistor 34a, but is connected to the NPN transistor 54a and the constant current source 55.
It is connected to the base of the NPN transistor 34a via an emitter follower circuit consisting of a.

Further, the source of the pMOS transistor 41b is not connected to the VRS voltage line but to the VCC power supply line 33, and the drain of the pMOS transistor 41b is directly connected to the base of the NPN transistor 34b. Is not connected and the NPN transistor 5
4b and a constant current source 55b, and is connected to the base of the NPN transistor 34b via an emitter follower circuit. In other respects, the configuration is similar to that of the sense amplifier 52 provided in the first embodiment.

In the second embodiment thus constructed, when a current flows through the common data line 15a during reading, the drain voltage of the pMOS transistor 41a becomes approximately VCC-ΔV = approximately -ΔV, and the pMOS transistor 41a The drain voltage of 41b is approximately VCC = approximately 0 [V].

As a result, the voltage of the common data line 15a = approximately VCC-VBE = approximately-0.8 [V], the voltage of the bit line 17a = approximately VCC-VBE-ΔV = approximately-0.8 [V] -Δ
It becomes V.

The voltage of the common data line 15b = approximately VC
C-ΔV-VBE = approximately −0.8 [V] −ΔV, voltage of bit line 17b = approximately VCC−ΔV-VBE = approximately −0.8
[V] −ΔV.

The bases of the NPN transistors 34a and 34b of the differential amplifier 37 are respectively pMOS.
Since a voltage obtained by lowering the drain voltage of the transistors 41a and 41b by VBE is applied, the NPN transistor 3
Saturation of 4a and 34b is prevented.

According to the second embodiment, the operating voltage is different from that of the first embodiment, but at the time of reading, as in the case of the first embodiment, the voltage of the common data line on the side where current does not flow is changed. , The voltage of the bit line connected to the common data line on the side where the current flows (approximately VCC-VBE-ΔV = approximately -0.8 [V] -Δ
V) and the voltages of the one and the other bit lines in the selected column are substantially the same voltage (approximately VCC-VBE).
It can be set to −ΔV = approximately −0.8 [V] −ΔV).

As a result, also in the second embodiment, at the time of reading, the voltage change of the bit line of the selected column is made minute, and the delay time of data reading due to the charging / discharging of the parasitic capacitance of the bit line is made minute. Therefore, the data reading speed can be increased.

Further, according to the second embodiment, the voltage of the bit line can be increased by 0.8 [V] as compared with the case of the first embodiment, so that the constant voltage VRC (-1. 6
No circuit is needed to obtain [V]).

Third Embodiment FIG. 5 FIG. 5 is a circuit diagram showing an essential part of a third embodiment of the present invention.
9 illustrates a sense amplifier / write circuit unit provided in a third embodiment of the present invention.

In the third embodiment, a sense amplifier 60, which is an improvement of the sense amplifier 53 shown in FIG. 3, is provided, and the other parts are configured similarly to the first embodiment shown in FIG.

Here, in the sense amplifier 60, p
The source of the MOS transistor 44a is not connected to the drain of the pMOS transistor 41b, and
It is connected to the emitter of the transistor 54b.

The source of the pMOS transistor 44b is not connected to the drain of the pMOS transistor 41a, but is connected to the emitter of the NPN transistor 54a. Others are similar to those of the sense amplifier 53 of the second embodiment.

In the third embodiment, when a current flows through the common data line 15a during reading, the drain voltage of the pMOS transistor 41a = approximately VCC-ΔV = approximately -Δ.
V, drain voltage of pMOS transistor 41b = approximately V
CC becomes approximately 0 [V].

As a result, the voltage of the common data line 15a = approximately VCC-2 × VBE = approximately -1.6 [V], the bit line 17
Voltage of a = approximately VCC−2 × VBE−ΔV = approximately −1.6
[V] −ΔV.

The voltage of the common data line 15b = approximately VC
C−ΔV−2 × VBE = approximately −1.6 [V] −ΔV, the voltage of the bit line 17b = approximately VCC−ΔV−2 × VBE = approximately−
It becomes 1.6 [V] -ΔV.

That is, also in the third embodiment, during reading, the voltage of the common data line on the side where no current flows is changed to the voltage of the bit line connected to the common data line on the side where current flows (approximately VCC-). 2 × VBE−ΔV = approximately −1.6 [V] −
ΔV) and the voltage of one and the other bit lines of the selected column is substantially the same voltage (approximately VCC-2 × VBE).
−ΔV = approximately −1.6 [V] −ΔV) can be set.

As a result, also in the third embodiment, at the time of reading, the voltage change of the bit line of the selected column is made minute and the delay time of data reading due to the charging / discharging of the parasitic capacitance of the bit line is made minute. Therefore, the data reading speed can be increased.

Here, in the first and second embodiments, in order to prevent saturation of the NPN transistors 42a and 42b, the voltage drop ΔV due to the load pMOS transistors 41a and 41b is VBE = 0.8 [V ], And is normally set to 0.4 [V] or less.

On the other hand, in the third embodiment, the base voltage of the NPN transistors 42a and 42b becomes lower than the collector voltage by VBE, and ΔV becomes V.
Even if it exceeds BE, it is not saturated and ΔV becomes 2 × VBE,
Since it saturates, increase ΔV, for example, 1.2 [V]
It can be a degree.

Thus, according to this third embodiment, Δ
Since V can be increased, the gate width of the transistors of the column switch circuits 14 ₀ ... 14 _x can be reduced, and the area occupied by the column selection circuit 7 can be reduced.

Fourth Embodiment FIG. 6 FIG. 6 is a circuit diagram showing an essential part of the fourth embodiment of the present invention.
9 illustrates a sense amplifier / write circuit section provided in a fourth embodiment of the present invention.

In the fourth embodiment, a sense amplifier 61, which is an improvement of the sense amplifier 60 shown in FIG. 5, is provided, and in other respects, the configuration is similar to that of the first embodiment shown in FIG.

Here, in the sense amplifier 61, V
A diode 62a is connected in the forward direction between the CC power supply line 33 and the base of the NPN transistor 54a.

A diode 62b is connected in the forward direction between the VCC power supply line 33 and the base of the NPN transistor 54b. Otherwise, the configuration is similar to that of the sense amplifier 60 shown in FIG.

In the third embodiment, when a current flows through the common data line 15a during reading, the drain voltage of the pMOS transistor 41a = approximately VCC−ΔV = approximately −Δ.
V, drain voltage of pMOS transistor 41b = approximately V
CC becomes approximately 0 [V].

As a result, the voltage of the common data line 15a = approximately VCC-2 × VBE = approximately -1.6 [V], the bit line 17
Voltage of a = approximately VCC−2 × VBE−ΔV = approximately −1.6
[V] −ΔV.

Further, the voltage of the common data line 15b = approximately VC
C−ΔV−2 × VBE = approximately −1.6 [V] −ΔV, the voltage of the bit line 17b = approximately VCC−ΔV−2 × VBE = approximately−
It becomes 1.6 [V] -ΔV.

That is, also in the fourth embodiment, at the time of reading, as in the case of the third embodiment, the voltage of the common data line on the side where no current flows is connected to the common data line on the side where current flows. Bit line voltage (approx. VCC-2 x VBE
−ΔV = approximately −1.6 [V] −ΔV), and the voltage of one and the other bit lines of the selected column is approximately the same voltage (approximately VCC−2 × VBE−ΔV = approximately −1. 6 [V]
-ΔV).

As a result, also in the fourth embodiment, at the time of reading, the voltage change of the bit line of the selected column is made minute, and the delay time of data reading due to charging / discharging of the parasitic capacitance of the bit line is made minute. Therefore, the data reading speed can be increased.

In the third embodiment shown in FIG. 5, the NPN transistor 42a is read at the time of reading immediately after writing.
Alternatively, the NPN transistor 42b raises the common data line 15a or the common data line 15b and the bit line 17a or the bit line 17b that have been pulled down to VEE to the voltage at the time of reading, during writing, but at this time, the transient current flowing causes the pMOS transistor 42b. A large voltage drop may occur in 41a or pMOS transistor 41b and saturate NPN transistor 42a or 42b.

On the other hand, according to the fourth embodiment,
Even when such an excessive current flows, the pMOS
Since the voltage drop due to the ON resistance of the transistors 41a and 41b does not exceed the forward voltage VBE of the diodes 62a and 62b, the NPN transistors 42a and 4b.
It is possible to prevent 2b from being saturated, and it is possible to secure more stable operation than in the third embodiment.

[0149]

As described above, according to the present invention, the sense amplifier, at the time of reading, changes the voltage of the first common data line to the voltage of the voltage detection point on the second common data line side for data detection. The voltage of the second common data line is configured to be related to the voltage of the voltage detection point on the first common data line side for data detection.
The voltage of the common data line on the side where no current flows is set to be the same or substantially the same as the voltage of the bit line connected to the common data line on the side where current flows, and the first and second columns of the selected column
Since the voltages of the bit lines can be made to be the same or substantially the same, at the time of reading, the voltage change of the first and second bit lines of the selected column is set to zero or minute, and the parasitic capacitance of the bit lines is reduced. The delay time of data reading due to charging / discharging can be zero or minute, and the speed of data reading can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part (sense amplifier / write circuit part) of a first embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a main part of a second embodiment (sense amplifier / write circuit section) of the present invention.

FIG. 4 is a circuit diagram showing a main part (memory cell array part, column selection circuit) of a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part (sense amplifier / write circuit part) of a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part (sense amplifier / write circuit part) of a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a main part of an example of a conventional SRAM.

8 is a circuit diagram showing a memory cell array portion and a column selection circuit which constitute the conventional SRAM shown in FIG.

9 is a circuit diagram showing a sense amplifier / write circuit unit that constitutes the conventional SRAM shown in FIG. 7;

10 is a waveform diagram showing an operation of the conventional SRAM shown in FIG.

[Explanation of symbols]

29 write circuit 52, 53, 60, 61 sense amplifier S _OUT , / S _OUT sense amplifier output

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11C 17/00 309 B

Claims (5)

[Claims] 1. A first and second bit line, and first and second data input / output terminals are connected to the first and second bit lines, respectively, and when selected at the time of reading, Corresponding to a plurality of columns provided with a plurality of memory cells configured so that a current flows from either the first or second data input / output terminal according to the data to be stored, and each of the plurality of columns. First and second connection switch elements each having a first end connected to the first and second bit lines and controlled to be turned on and off based on a column selection signal. , The first and second common data lines provided corresponding to the plurality of columns and respectively connected to the second ends of the first and second connection switch elements, and the first and second common data lines at the time of reading, By detecting the current flowing through the first and second common data lines, In a semiconductor memory device including a sense amplifier that detects data stored in a selected memory cell, the sense amplifier is configured to detect the voltage of the first common data line for data detection during reading. The voltage of the voltage detection point on the second common data line side is related, and the voltage of the second common data line is related to the voltage of the voltage detection point on the first common data line side for data detection. A semiconductor memory device having the above structure. 2. The sense amplifier is configured to drive the first voltage as a high-voltage side power supply voltage and the second voltage lower than the first voltage as a low-voltage side power supply voltage. A differential amplifier, lower than the first voltage, the second voltage
A third voltage higher than the voltage on the first end is applied to the first end,
A first load element having a second end connected to the first data input end of the differential amplifier; and the third voltage supplied to the first end, and the second end connected to the first end. A second load element connected to the second data input terminal of the differential amplifier, and a first controlled electrode connected to the second end of the first load element to provide a second controlled element. A first transistor having an electrode connected to the first common data line, a first controlled electrode connected to the second end of the second load element, and a second controlled electrode A second transistor connected to the second common data line, and a third connection switch for connecting the second end of the second load element to the control electrode of the first transistor during reading. An element and, when read, connects the second end of the first load element to the control electrode of the second transistor. The fourth semiconductor memory device according to claim 1, characterized by being constituted by a connection switch element. 3. The sense amplifier is configured to drive the first voltage as a power supply voltage on the high voltage side and a second voltage lower than the first voltage as a power supply voltage on the low voltage side. A differential amplifier and a first controlled electrode are connected to a first voltage line that supplies the first voltage, and a second controlled electrode is connected to a first data input terminal of the differential amplifier. And a first transistor connected to a second voltage line that supplies the second voltage via a first constant current source, and a first controlled electrode connected to the first voltage line. A second transistor having a second controlled electrode connected to a second data input terminal of the differential amplifier and a second constant current source connected to the second voltage line; One end is connected to the first voltage line and the second end is the control electrode of the first transistor. A first load element connected, first
A second load element having an end connected to the first voltage line and a second end connected to the control electrode of the second transistor, and a first controlled electrode connected to the first load electrode. A second controlled electrode connected to the second end of the load element;
A third transistor connected to the common data line, a first controlled electrode connected to the second end of the second load element, and a second controlled electrode connected to the second common electrode. A fourth transistor connected to the data line, and a third connection switch element for connecting the second end of the second load element to the control electrode of the third transistor when reading,
4. A fourth connection switch element that connects the second end of the first load element to the control electrode of the fourth transistor during reading, and is configured. The semiconductor memory device described. 4. The sense amplifier is configured to drive a first voltage as a high-voltage side power supply voltage and a second voltage lower than the first voltage as a low-voltage side power supply voltage. A differential amplifier and a first controlled electrode are connected to a first voltage line that supplies the first voltage, and a second controlled electrode is connected to a first data input terminal of the differential amplifier. And a first transistor connected to a second voltage line that supplies the second voltage via a first constant current source, and a first controlled electrode connected to the first voltage line. A second transistor having a second controlled electrode connected to a second data input terminal of the differential amplifier and a second constant current source connected to the second voltage line; One end is connected to the first voltage line and the second end is the control electrode of the first transistor. A first load element connected, first
A second load element having an end connected to the first voltage line and a second end connected to the control electrode of the second transistor, and a first controlled electrode connected to the first load electrode. A second controlled electrode connected to the second end of the load element;
A third transistor connected to the common data line, a first controlled electrode connected to the second end of the second load element, and a second controlled electrode connected to the second common electrode. The fourth transistor connected to the data line and the second controlled electrode of the second transistor are connected to the third transistor during reading.
A third connection switch element connected to the control electrode of the transistor, and a fourth connection switch element connecting the second controlled electrode of the first transistor to the control electrode of the fourth transistor during reading. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises: 5. A first diode is connected in a forward direction between the first voltage line and a control electrode of the first transistor, and the first voltage line and the second voltage line are connected to each other. The second diode is connected in the forward direction between the control electrode of the transistor and the control electrode of the transistor.
The semiconductor memory device described.