JPS60225279A - Fourier transform device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of overflow during the high-speed Fourier transform operation by using a buffer memory to perform a complete gain control for input data in a saturation gain controller. CONSTITUTION:An output (c) of an arithmetic memory 8 is reduced to a half and is sent to a butterfly arithmetic part 9. The butterfly arithmetic part 9 multiplies input data by a twist factor and subjects data to two-point DFT (discrete Fourier transform) and stores the result in the arithmetic memory 8. At this time, the second saturation gain control circuit 6b monitors the output of the butterfly arithmetic part and detects a maximum value of all data of the first butterfly arithmetic output. If the number of bits of the maximum value reaches a maximum bit length, the second saturation gain control circuit 6b controls the second shifter 7b in the second butterfly arithmetic so that the shifter 7b shifts down data 1/2 times; but otherwise, the circuit 6b controls the second shifter 7b so that the shifter 7b does not shift data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a Fourier transform device used, for example, in a radar signal processing device.

A Fourier transform device used in a radar signal processing device performs frequency analysis of the Doppler component of a received signal, suppresses unnecessary signal components, improves the S/N ratio, and detects a target. The present invention is a saturation gain control device that minimizes the loss of small signal data due to underflow during calculation in the Fourier transform device, by completely controlling the gain of input data using a buffer memory. , which is characterized by preventing overflow from occurring during fast Fourier transform operations.

FIG. 1 shows an example of a radar signal processing device using the above Fourier transform device. In Figure 1, the radio waves emitted from the antenna (!) are reflected from the target.

A part of the reflected echo is received again by the antenna O) and detected by the receiver (2). Receiver (2)
The video signal output from is input to the previous stage signal processing device (3). The video signal is converted into a digital signal in the pre-stage signal processing device (3), and processing such as suppression of clutter, which is an unnecessary signal, and pulse compression are performed. The output of the pre-stage signal processing device (3) is input to the Fourier transform device (4) of the present invention, where it is multiplied by a time window function and then subjected to 5 Fourier transform (hereinafter referred to as FFT) operations to be decomposed into frequency components. The output of the Fourier transform device (4) has distance direction information divided into frequency bins, and is input to the subsequent signal processing device (5). After removing the contents of the frequency bins containing clutter components, the subsequent signal processing device (5) automatically detects the target within each frequency bin, making it possible to derive the position and velocity of the target.

In the Fourier transform device (4), the operation is a repetition of multiplication and addition. At this time, in the case of high-speed processing such as radar signal processing, floating point arithmetic is difficult, and fixed point arithmetic is usually performed. Therefore, since there is a possibility that data may overflow during calculation, overflow is prevented by shifting down the output by 11:+it every time addition is performed.

However, if a small signal is input, the signal may be lost during calculation because 1 bit is cut off and discarded in the shift down.

In order to solve this problem, there is a saturation gain control circuit that has a function of preventing the above-mentioned overflow and at the same time minimizing signal loss. The present invention relates to this saturation gain control circuit.

[Prior art]

FIG. 2 is an example of a fast Fourier transform device using a conventional saturation gain control circuit. In Figure 2, the saturation gain control circuit (6) receives complex input data (t).
Coherent processing
interval (data sampling time for performing Fourier integration) is monitored, and the maximum absolute value of the complex human force data 0 during that period is detected and held. After that, in the first-order CP process, the output of the saturation gain control circuit (6) is adjusted so that the complex input data is shifted up within the range where the maximum value does not overflow when the complex input data (A) passes through the thick (7). The control signal 0) is controlled.

For example, in FIG. 2, the bit length of the data line of complex input data (g) is m.

The maximum absolute value between cp workers was nhlt)
Then, in the next cp work, shifter (7) is (m-n) b
Carry j and t. The output of 71 is stored in the calculation memory (8) for > cpI, and then the butterfly calculation is repeated with the butterfly calculation unit +93. For example, t
When performing point FFT, calculations are repeated 20g21 times between the calculation memory (8) and the butterfly calculation unit (9). There is an adder in the butterfly operation section (9).

Depending on the input busyness, the output may overflow. Therefore, the input of the butterfly operation section (9) is 1/2
With yQl, the digit is always downsized by 1/2.

As mentioned above, the Fourier transform device shown in Fig. 2 shifts up the complex input data (a) within a range that does not saturate it, and then uses the FF
By performing T calculation, signal loss during calculation can be suppressed more than K. However, in the above device, l
Since the maximum value of the next CP is predicted using the data before oPl, a maximum value larger than the prediction is input between 021 of the first order, and overflow may occur at thick (7).

FIG. 3 shows a Fourier transform device that solves the above problem by using a buffer memory that temporarily stores data for loPl. In FIG. 3, the maximum absolute value of the complex input data between tapI is detected in the saturation gain control circuit (6) and simultaneously stored in the buffer memory. The complex input data ω stored in the buffer memory 6n in the next CP is read out and shifted by a shifter (7). At that time, a control signal (
() is generated using the maximum value of the complex input data (a).

Data never overflows in the shifter (7).

This buffer memory (2) is originally used to temporarily store input data, which is a radar reception signal that is constantly sent, for FFT calculation.

[Summary of the invention]

By the way, the Fourier transform device shown in Fig. 3 carries the input data for performing the F'FT operation to the maximum bit length to prevent the loss of the operation value during the F'FT operation. In this case, the loss of small signals due to undercarriage during calculation is still a problem.

The present invention solves the above problem by performing saturation gain control during transfer from the arithmetic memory to the butterfly arithmetic section.

[Embodiments of the invention]

FIG. 4 shows an example of the Fourier transform device of the present invention. In FIG. 4, the complex input data is transferred to the buffer memory (II) at the same time that the maximum absolute value between 1 CPI is detected by the first saturation gain control device (6a), similar to the device shown in FIG.
is stored in The first saturation gain control device (6a) consists of an absolute value detection circuit, a maximum value comparator, and a register between ) to determine the amount of shift.

The complex input data for loPl stored in the buffer memory α9 is sequentially read out in the next OP process, and the first chic (
7a). At this time, since the control signal (A) of the first thick (7a) is determined by the maximum value of the complex input data currently being sent to the first shifter (7a), the first shifter (7a) The output will never exceed 70-.

The output of the shifter (7a) is sent to the calculation memory (8) and performs FFT calculation with the butterfly calculation section (7). The output (c) of the arithmetic memory (8) is sent to the second chic (7b). The second thick (7b) performs a 1/2 or 1 times shift, and the output ←) of the calculation memory (8) is first shifted by 1/2 or 1 times.
It is doubled and sent to the butterfly calculation section (9). The butterfly calculation unit (9) multiplies the input data by the distortion factor, performs two-point DFT (discrete Fourier transform), and stores the result in the calculation memory (81).At this time, the second saturation gain control circuit (6b) Monitor the output of the arithmetic unit and
The maximum value of all the data of the first butterfly calculation output is detected. In the second butterfly operation, if the number of bits of the maximum value reaches the maximum bit length, the second saturation gain control circuit (6b) controls the second shifter (7b1 so that the digit is downsized to 1/2). If the value has not been reached, the second shifter (7b) is controlled to 1 times.Arithmetic memory (
8) and the butterfly calculation unit (9) increases as the number of FFT points increases, as described in the explanation of FIG. 2. Therefore, if the conventional device performs the number of operations, it becomes 1/2 times -J? Although it is possible that the signal is lost.

In the device shown in Fig. 4, a butterfly calculation unit (9) is used for each calculation.
As long as the output of the shifter does not reach the maximum bit length, the signal does not decrease because the shifter is 1 times.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform complete saturation gain control without signal loss or overflow during FFT calculation with a large number of points.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a radar signal processing device using the Fourier transform device of the present invention, and FIG.
FIG. 3 is a diagram showing a Fourier transform device using a saturation gain control circuit shown in FIG. FIG. 4 is a diagram showing a Fourier transform device of the present invention using a saturation gain control circuit.
) is the receiver, (3) is the front-stage signal processing device, (4, is the Fourier transform device, (5) is the rear-stage signal processing device 6?, (6)
is a saturation gain control circuit, (7) is a shifter, and (8) is an arithmetic memory. (9) is the butterfly calculation section, Ql is the 1/2 scale unit 9
Port 1) is a buffer memory. Identical or corresponding parts in each figure are designated by the same reference numerals. Agent Masuo Oiwa

Claims (1)

[Claims] Real-time complex input data can be converted to IO2 (C!Oh8ren)
a first saturation gain control circuit that detects the maximum value between tapI of the complex input data and controls a first thick; and a first saturation gain control circuit that changes the gain of the buffer memory output. a shifter, a calculation memory that stores the output of the first chic for 1cp, a butterfly calculation unit that performs FFT calculation between the calculation memory, and a control signal that detects the maximum value of the output of this butterfly calculation unit. A Fourier transform device comprising: a second saturation gain control circuit that generates a saturation gain; and a second shifter that controls the output of the arithmetic memory.