JP2662694B2 - Digital protection relay device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital protection relay device provided with a digital filter.

[Conventional technology]

Conventional digital protection relay is 105
No. 12, p. 12 (Showa 60) and Hitachi Review Review Vol. 61, No. 11 (1979-11)
The input filter consists of an RC active filter as discussed in. In general, the protection relay operation is performed by sampling input data filtered at a frequency 12 times the fundamental wave and using this data.

[Problems to be solved by the invention]

However, the above prior art has the following problems to be solved.

That is, since the sampling frequency of the input data is 12 times the fundamental wave frequency of the input data (30 electrical pitch), the relay operation determination related to the protection relay calculation should be shorter than 30 pitch. However, there is a problem that high-speed determination is limited and high accuracy is hindered.

In addition, since the input filter is an analog filter using an RC active filter, it is not possible to avoid variations in the characteristics of elements constituting the filter, such as a resistor, a capacitor, and an operational amplifier. Therefore, when a plurality of RC active filters are provided in parallel in order to filter a plurality of input data at the same time, there is a problem that characteristics are varied among them and accuracy is reduced.

An object of the present invention is to solve the above-mentioned conventional problems, in other words, to provide a filter processing device capable of contributing to high accuracy and high-speed determination of a protection relay, and a protection relay device using the filter processing device. To provide.

[Means for solving the problem]

In order to achieve the above object, a digital protection relay device according to the present invention includes an A / D conversion unit that captures input data at a constant sampling period Ts and converts the input data into digital data, and filters the A / D converted input data. Digital filter means for performing arithmetic processing, and protection relay means for performing protection relay arithmetic processing based on the input data filtered by the digital filter means, wherein the digital filter means comprises an integer N of the sampling period Ts. It is assumed that N filter operations are executed during the sampling period Ts at a period Tp of twice the frequency (where N is 2 or more). In one execution period of the N filter operations, Performs a filter operation on A / D-converted input data, and in other execution cycles, based on input data input in the past. Interpolation input data determined according to the procedure defined because (hereinafter, referred to as pseudo input data.)
, And the protection relay means executes the protection relay calculation in synchronization with the cycle Tp and based on the input data filtered in the execution cycle.

It is preferable that the filter calculation process is performed based on input data of several consecutive points in the past including the pseudo input data.

It is preferable that the digital filter means and the protection relay means are integrally configured using the same digital signal processor, and the filter operation and the protection relay operation are executed in a time division manner within the execution cycle Tp.

As the pseudo input data, the latest input data is used (that is, it is assumed that there is no change in the input data), and the interpolation data obtained from the input data including several past pseudo input data is used. One that sets the pseudo input data to zero, sets the execution period Tp of the filter operation to 1/2 of the sampling period Ts, and uses the latest A / D converted input data multiplied by a predetermined coefficient. can do.

[Action]

 According to the present invention, the object is achieved by the following actions.

According to the protection relay device having the above configuration, first, input data indicating state quantities such as input voltage and current is A / D-converted at each sampling cycle Ts. After that, the filter processing by the digital filter operation is performed. This filtering process is repeated at intervals of 1 / N of the sampling period Ts Tp based on a preset filter coefficient. Therefore, it is possible to provide input data required for the protection relay operation at a frequency higher than the sampling frequency. This can achieve high-speed operation determination and contribute to high accuracy of the protection relay.

It is needless to say that the filter operation processing has a frequency characteristic of passing the fundamental frequency component of the input data while removing the high-speed wave. For this reason, even if filtering is performed on the pseudo input data instead of the true input data, the high-frequency components generated by the simulation are removed, and substantially the same as sampling at a short pitch of N times the frequency. Fundamental wave data can be obtained.

In addition, the digitalization of the filter processing makes it possible to eliminate the problems inherent in analog filters such as RC active filters, that is, variations due to changes in element characteristics, and achieves high precision in this aspect as well. .

On the other hand, according to the protection relay device having the digital filter processing device having the above configuration, the pitch of the protection relay arithmetic processing is shortened, the speed of operation determination is improved, and highly accurate determination can be performed.

According to the differential relay, the transmission cycle of the communication line can be lengthened, and the load on the communication line can be reduced.

〔Example〕

Hereinafter, the present invention will be described using examples. FIG. 1 shows a digital protection relay device according to an embodiment to which the present invention is applied, and particularly shows a block configuration centering on an analog input section.

In the figure, aliasing error prevention filter 1A, 1B ... 1M is a filter for removing a signal of 1/2 or more of the frequency components of the sampling frequency fs in the input data D ₁ Dm.
These outputs are sequentially stored in a sample / hold circuit (S / H) 3 via a multiplexer (MPX) 2 and simultaneously converted into digital input data in an A / D converter 4 and stored in a buffer memory 5. Is done. The contents of the buffer memory 5 are input to a digital signal processor (DSP) 7 via an internal bus 6. Also, D
The SP 7 is connected via the internal bus 6 to a ROM 8 in which a DSP instruction program is stored and a dual-port RAM 9 which can be accessed from both directions. The RAM 9 can be connected to another processing device via the interface circuit 10 and the standardization bus 11. The timing control circuit outputs a synchronization signal required for each of the above-described constituent blocks.

Here, a schematic configuration of the DSP 7 is shown in FIG. As shown in the figure, DSP7 is an instruction ROM 21, m bits × m
Bit high-speed parallel multiplier (MPY) 22, Data RAM 23, DSP7
Address register (AR) 24, data register (DR) 25, and ALU (Arithmetic Logic Unit) 2 as an arithmetic unit for performing processing such as addition and subtraction
6, accumulator (ACC) 27, timing control circuit 28,
The DSP 7 includes an internal bus (data bus, address bus) 29. The high-speed parallel multiplier MPY22 multiplies the input data inA and inB during one instruction cycle,
The result outC is output. Configured like this
DSP7 features MPY22, which enables multiply-accumulate operations during one instruction cycle, and enables high-speed numerical operations on fixed-point and floating-point data by enabling pipeline processing. It is known that can be realized.

Therefore, the present invention is suitable for a digital filter operation that requires a product-sum operation of fixed / floating-point data to be repeated at high speed. Also, digital filters have advantages over analog filters in that they do not require adjustments in mounting, do not change over time, easily change specifications and characteristics, and can be miniaturized.

FIG. 3 shows a conceptual block diagram of a digital filter. Needless to say, this configuration is realized by the program of the DSP7. FIG. 1A shows an IIR (Infinite extent).
Impulse Response) type filter.
It is a block configuration of a (nite extent Impulse Response) type filter.

In FIG. (A), Xn is the input signal, reference numeral 31 is a respective coefficient block, K is a gain _{factor, A 1, A 2, B} 1 and B ₂ is the filter coefficient. Reference numeral 32 denotes a delay block, which is a block (Wn _-1 ) that delays the signal Wn by one time of the filtering period Tp and a block (Wn) that similarly delays the signal Wn by two times.
n- ₂ ). Reference numeral 33 denotes an addition block, and Yn denotes filter output data. When FIG. 7A is represented by an equation, the processing of the following equations (1) and (2) is performed.

Wn = K ・ Xn + B ₁・ Wn _-1 + B ₂・ Wn _-2 (1) Yn = Wn + A ₁・ Wn _-1 + A ₂・ Wn _-2 (2) K: Gain coefficients A1, A2, B1, B2: Filter coefficient Xn: Input data Yn: Output data Wn _-1 : One time delay data of Wn Wn _-2 : Two time delay data of Wn Performed sequentially using a plurality of data of voltage and current data.
The calculation result is stored in the internal RAM 23 of the DSP 7. On the other hand, in FIG. 3B, X'n indicates input data and Y'n indicates output data. Numeral 34 is a delay block, X'n- ₁ is a block delayed by one time in the same manner as described above, and X'n- ₂ is 2
Indicates a block delayed by the time. Reference numeral 35 denotes a filter coefficient block, each filter coefficients _{A '0, A' 1,} A '2 is set. Reference numeral 36 denotes an addition block. This figure can be expressed by the following equation (3) when expressed by an arithmetic equation.

_{Y'n = A '0 · X'n +} A' 1 · X'n -1 + A '2 ·
X'n _-2 (3) The configuration of the filter is not limited to the one described above, and it goes without saying that filters of different types and filters of different orders can be arbitrarily configured and changed in software.

Taking the above-mentioned IIR type digital filter as an example, with the same configuration, as shown in the following equations (4) to (),
The low-pass filter, the hand-pass filter, the high-pass filter, the notch filter, the low-pass filter, the high-pass notch filter, and the all-pass filter can be realized only by changing the filter coefficients. Note that H (z) is a transfer function, and Z corresponds to S in an analog system.

_{Here, r = 2 · cos2πf 0 ·} T T: sampling interval f _0: stopping frequency FIG. 4 shows a frequency characteristic diagram of these filters.

 (A) is a low-pass filter, (b) is a band-pass filter, (c) is a high-pass filter, (d) is a notch filter, (e) is a low-pass filter, (f) ) Is a high-pass notch filter, and FIG. 3G is an all-pass filter.

Regarding the operation of the embodiment configured as described above,
This will be described with reference to the flowchart of the processing procedure shown in FIG. 5 and FIG.

The state data D _{1 to} Dm of the system detected by the voltage transformer or the current transformer provided in the power system are input to the MPX 2 via the return error prevention filters 1A to 1M. The return error prevention filters 1A to 1M remove a return error caused by sampling and operate as an input buffer.
The MPX 2 switches the input data D _{1 to} Dm periodically and sequentially and inputs the data to the S / H circuit 3. The S / H circuit 3 is intended to hold between the analog input data D ₁ Dm same time the A / D converter 4 is operated, thereby to increase the A / D conversion accuracy. The A / D converted input data is stored in the buffer memory 5. The DSP 7 fetches the input data stored in the buffer memory 5 via the internal bus 9 and performs arithmetic processing based on the program stored in the instruction ROM 8.

The DSP 7 writes the operation result into the multi-port RAM 8 via the internal bus 9 again. The RAM 8 is a dual-port RAM and can be accessed in both directions, so that output data can be output via the interface circuit 10 from a port different from the port written from the DSP 7 side. Here, the procedure of the arithmetic processing in the DSP 7 shown in FIG. 5 will be described. Step 101 is an initial process in which the memory and registers in the DSP 7 are cleared, and the digital filter coefficients according to the equations (1) and (2) are set.
The data is input to the data RAM 23 inside the DSP 7. The coefficient of the digital filter is the frequency fp of the execution cycle of the filter operation.
Is designed to be N times (N: an integer) the sampling frequency fs of the input data.

In step 102, a periodic process is performed to set an interrupt waiting state. Then, in step 103, the buffer memory 5
Then, the input data is read out and taken into the data RAM 23. At step 104, a filter operation according to the above equations (1) and (2) is performed on the input data.
In the next step 105, a protection relay operation for detecting an accident in the power system is executed according to a preset procedure based on the input data that has been filtered. For example,
In the case of a distance relay for obtaining the distance to the accident point, the calculation shown in the following equation (9) is executed.

Σ (I · Z−V) I · Z> α (9) I: current value V: voltage value Z: set value α: comparison value In step 106, the result of the operation judgment or the like obtained by the protection relay calculation is calculated. Output to dual port RAM9.

Next, in step 107, it is determined whether or not the number of executions of the filter operation and the protection relay operation in the sampling period Ts has reached N. If affirmative, next sampling period
In order to shift to the process of Ts, the process returns to the synchronization process of step 102. When a negative determination is made, the process proceeds to the pseudo input data calculation in step 108, and the pseudo data of the input data to be subjected to the next filtering process is set.
Repeat step 105.

As described above, the following method can be applied as a method of creating the pseudo input data.

A method using the latest input data (that is, a hypothesis that there is no change in the input data), a method using interpolation data obtained from input data including several past pseudo input data, and setting the pseudo input data to zero, Execution cycle T _{F of} filter operation
Is set to 1/2 of the sampling period Ts, and the latest input data subjected to A / D conversion is multiplied by a predetermined coefficient.

Here, the above-described processing procedure will be described with reference to a time chart.

FIG. 6 is a time chart in the case where N = Ts / Tp (= fp / fs) of the above cycle is set to 2. FIG. 6A shows the timing of the sampling hold command signal given to the S / H circuit 3, and the input data D ₁ to m at the point m in the synchronization Ts.
Dm are sequentially held at the time a ₁ ~am. FIG.
The timing of the command signal given to the A / D converter 4 is shown, and the input data D _{1 has the} same cycle as the sampling cycle Ts.
~Dm are successively converted into digital input data X ₁ through XM at time b ₁ to Bm. Then, as shown in FIG. 3C, the data is sequentially stored in the buffer memory 5 at times c _{1 to} cm. The timing shown in FIG.
DSP7 processing is started. It takes the input data X ₁ through XM buffer memory 5 at time period d _11, with respect to their input data X ₁ through XM in the time period d _12, to perform each first filter operation. Then the time zone d ₁₃ performs a protective relay operation based on the data X, which is filtered. Then, outputs the result of the protective relay computation in hours d _14. Following this output, the second filter operation and protection relay operation are started. First, to determine the pseudo input data by calculation or the like by any of the techniques described above with the time zone d _21. In the next time zones d ₂₂ and d ₂₃ , the filter operation and the protection relay operation are performed in the same manner as the first time, and the results are expressed in the time periods d ₂₂ and d _23.
Output with d ₂₄ and exit. As described above, the filtering process and the like are performed twice in the execution cycle Ts / 2 within one sampling cycle T _S.

7 to 9 show a method of setting pseudo input data and a comparison between output waveforms filtered by the method. In both cases, N = 2, in which (a) shows the sampling period Ts, (b) shows the waveform to be subjected to the filtering process including the pseudo input data (indicated by a dotted line in the figure), and c)
Indicates a waveform resulting from the filtering.

FIG. 7 shows an example of the above-described method. At times t ′ ₁ , t ′ ₂ ,... Where no true input data is obtained, it is assumed that there is no change in the input data. This is an example of processing using data as it is. According to this, it is possible to obtain a signal of only the fundamental wave component as shown in FIG. That is, high-frequency components are removed from the stop band of the filter operation processing, and highly accurate input data is obtained.
As a result, the protection relay operation can be performed at a frequency fp that is twice the sampling frequency fs.

FIG. 8 shows an example of the above-described method. At the time of execution of times t ′ ₁ , t ′ ₂ ,... Where true input data cannot be obtained, the slope of the input data at the immediately preceding t ₁ or t ₂ is calculated. This is to set the pseudo input data by interpolation. According to this example, a signal having only the fundamental wave component can be obtained as in FIG.

Figure 9 is an example of the aforementioned methods, the time t _'1, t' ₂ can not be obtained a true input data, ... at the time of execution, and processes in fiction to zero input data. According to this example, a signal having only the fundamental wave component can be obtained as in FIG.

Although not shown, the above-mentioned method is also used.
It can be easily understood that similar results are obtained from the examples of FIGS. 7 to 9.

Here, the frequency characteristic of the filter obtained by setting the frequency fp of the execution cycle of the filter processing to N times the frequency fs of the sampling cycle of the input data will be described.

FIG. 10 shows an example of the frequency characteristic of the band-pass filter of the digital filter processing device according to the present embodiment. The horizontal axis in the figure represents frequency, and the vertical axis represents gain. In the figure, a curve 41 is a target characteristic, a curve 42 is a characteristic of the present embodiment, and a curve 43 is fs.
This is the characteristic when fp is equal.

Generally, a bandpass filter sets the zero frequency to OHz and 1/2
Since it is set to fp (1/2 of the filter execution frequency), f
When s = fp, as indicated by the characteristic curve 43, the target curve 41
From the characteristics. On the other hand, according to the present embodiment, the filter execution frequency fp is equal to the sampling frequency fs.
Is zero, the zero frequency is twice that of curve 43,
The error with the target characteristic 41 is reduced, and the accuracy is improved.

Also, since digital filters are discrete signal processing,
Filters 1A to 1M at the previous stage of S / H circuit 3 to prevent aliasing error
It is necessary to cut off a frequency equal to or more than 1/2 times the sampling frequency fs.

In this respect, according to the present embodiment, since the processing execution frequency fp of the digital filter is increased, the characteristics of the filters 1A to 1M for preventing aliasing errors are sufficient if the filter has a gentle attenuation. As a result, the size of the folding error prevention filter can be reduced.

FIG. 11 shows an embodiment in which a differential relay device is configured using the digital filter processing device according to the present invention. As shown in the figure, protection relay devices 52A and 52B having the same configuration are respectively installed at two distant points of the transmission line 51, and a system state quantity (current data) is exchanged between them via a signal transmission line 53 to obtain a difference. It is intended to determine an accident in the system by dynamic calculation. Each protection relay device 52A, 52B is a current transformer 54,
It comprises a transformer 55, A / D converters 56A and B including S / H circuits, digital filters 57A, B and C, a communication terminal 58, and a protection relay operation block 59.

In such a differential relay device, it is desirable in terms of accuracy to increase the sampling frequency fs of the current data. However, there is a case where fs cannot be increased due to the limitation due to the transmission capacity of the transmission path 53. In this regard, according to the digital filter processing device of the present invention, even if the sampling frequency fs of the input data to be transmitted is low, it is possible to obtain the input data processed at N times the frequency by the filtering process, and to obtain a highly accurate It is possible to perform a protection relay operation.

〔The invention's effect〕

As described above, according to the digital filter processing according to the present invention, the input data necessary for the protection relay operation can be obtained at a frequency (density) N times the sampling frequency.
Thus, by configuring the protection relay device using this, the speed of the relay operation determination can be increased, and the accuracy can be increased.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part of a digital protection relay device according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a DSP of the embodiment of FIG.
FIG. 3 is a conceptual configuration diagram of a specific example of the digital filter of the embodiment of FIG. 1, FIG. 4 is a filter characteristic diagram, and FIG. 5 is a flowchart of a processing procedure of filter operation and protection relay operation of FIG. 6, FIG. 6 is a time chart showing the operation of the embodiment of FIG. 1, FIGS. 7 to 9 are waveform diagrams showing the operation of the embodiment of the pseudo input data, and FIG. 10 is the frequency characteristic of the embodiment of FIG. FIG. 11 is a configuration diagram of a differential relay device according to an embodiment of the present invention. 3 ... Sample hold circuit, 4 ... A / D converter, 7 ... Digital signal processor, 52A, 52B ... Protection relay device, 53 ... Signal transmission line.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-221516 (JP, A) JP-A-60-182829 (JP, A) JP-A-61-213926 (JP, A) JP-A-62-162 250816 (JP, A)

Claims (4)

(57) [Claims] A / D conversion means for taking input data at a fixed sampling period Ts and converting the data into digital data;
Digital filter means for performing a filter operation on the A / D-converted input data, and protection relay means for performing a protection relay operation based on the input data filtered by the digital filter means, wherein the digital The filter means performs N filter operations during the sampling period Ts with a period T _P having a frequency that is an integer N (where N is 2 or more) times the sampling period Ts. In one execution cycle of the filter operation, the filter operation is performed on the A / D-converted input data, and in another execution cycle, the filter operation is performed according to a predetermined procedure based on input data input in the past. A filter operation is performed on the interpolated input data, and the protection relay means performs a filter operation in synchronization with the cycle Tp and in the execution cycle. Digital protection relay apparatus configured to perform a protection relay operation based on the input data. 2. The digital protection relay device according to claim 1, wherein said interpolated input data is obtained based on past several consecutive points of input data and interpolated input data. 3. The digital protection relay device according to claim 1, wherein the interpolation input data is obtained by multiplying the latest input data by a predetermined coefficient. 4. The digital filter means and the protection relay means are integrally formed using the same digital signal processor, and a filter operation and a protection relay operation are executed at an execution cycle.
4. The method according to claim 1, wherein the processing is performed by time division within Tp.
Digital protection relay device according to any one of the above.