JPS60225253A - Information processing device - Google Patents

Abstract

PURPOSE:To start a microprogram in accordance with each system architecture by preparing instruction control information corresponding to an instruction code for each of plural system architectures. CONSTITUTION:A system firmware which controls an instruction control arithmetic unit 3 recognizes an architecture to set a corresponding bit of a mode register 305 to ''1'' before an instruction firmware starts execution. Then, a selecting circuit 304 selects the output of a read register 303a from outputs of read registers 303. That is, address data read out from a compartment 302a of a control memory 302 is selected. When the instruction is stored in an instruction register 301 and is started, contents of a read register 303b are set to an address register 306, and a microprogram is read out from a control store 307, and the execution is started.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to microprogram control in an information processing device, and more particularly to a microprogram control method capable of operating according to a plurality of system architectures.

Prior Art Conventional information processing devices are designed to operate according to one system architecture, and one operating system (OS) runs exclusively on the machine. In recent years, the concept of a virtual machine has been introduced, which allows multiple operating systems to run on a single machine, making the machine appear virtual to each operating system, and controlling each operating system as if it were its own machine. being born.

In a virtual machine, each operating system follows a different system architecture, so the information processing device that implements the virtual machine must have hardware and firmware configured to satisfy multiple different system architectures. However, in the instruction system specified for each system architecture, the instruction code of the instruction is assigned regardless of the function of the instruction, so the microprogram to be uniformly activated is determined according to the instruction code. Conventional information processing devices that process instructions have the disadvantage that the arrangement of microprograms must be changed each time an operating system occupies the machine.

OBJECTS OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks, and to prepare instruction control information corresponding to instruction codes for each of a plurality of system architectures in advance so that the system firmware manages system architecture modes. The object of the present invention is to provide an information processing device that can comply with a plurality of system architectures by making it possible to start a microprogram according to each system architecture.

Structure of the Invention The information processing apparatus of the present invention includes a control memory storing a microprogram start address, etc. corresponding to each instruction code in a plurality of architectures in each of a plurality of compartments read and addressed by the instruction code;
a control store storing a plurality of microprograms consisting of a series of microinstructions; a mode register storing system management information specifying which of the plurality of system architectures is to be followed based on output information of the control store; a selection circuit that selectively selects a plurality of address information, etc. output from a plurality of compartments of the control memory according to the output of the mode register, and outputs a read address signal, etc. of the control store; It is characterized by performing microprogram control that can support system architecture.

Embodiment 1 of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, the instruction word is read from the main memory device 1 via the storage control unit 2 to the instruction control arithmetic unit 3 and stored in the instruction register 301 in the instruction control arithmetic unit 3. An 8-bit instruction code 301a is stored in a part of the instruction register 301. The instruction code 301a stored in the instruction register 301 is used as a read address signal for the control memory 302.

Control memory 302 has four compartments 302a
~ 302d, and in each compartment, the activation address of the microprogram to be activated is stored in advance in correspondence with the instruction code of each system architecture. Compartment 302a has 16
It has a capacity of 256 bits x 256 words, and stores instruction control information corresponding to the instruction code of system architecture-A, such as the starting address of a microprogram.

The compartments 302b to 302d store microprogram startup addresses and the like corresponding to the instruction codes of the system architecture B to D, respectively. The read register 303 is a 16-bit x 4 register.
Consisting of two read registers 303a to 303d,
Converter) 302a to 302d output (each 16
bits). Read registers 303a-303
The output of d is input to a four-person output selection circuit 304, and the one selection circuit 304 automatically selects and outputs the four inputs according to instructions from the mode register 305 and sets it in the address register 30B. Address register 30B is 1
A 6-bit register stores the output of the selection circuit 304 and outputs it as a read address signal for the control store 307.

The mode register 305 is a 4-bit register as shown in FIG. 2, and each bit stores information indicating which of system architectures A to D is specified. When operating according to architecture-A, bit 0 is set to "l" as shown in FIG. 3(A), and when operating according to architecture-B-D, as shown in FIG. 3(B) to (D), respectively. , bits 1 to 3 are “1”
”. This information can be changed at the output of the read register 308 of the control store 307.

That is, it is set by the system firmware. Furthermore, the contents of the mode register 305 can be referenced by the hardware and firmware of the instruction control arithmetic unit 3 at any time.

Various microprograms are stored in the control store 307, and the output thereof is stored in a read register 308. The output of the read register 308 controls each part (not shown) in the instruction control arithmetic unit 3, and the microprogram is executed. Ru. Further, a part of it is used to change the contents of the mode register 305.

Next, we will explain the operation of this embodiment. When this device operates according to system architectures A to D, the system firmware that controls the instruction control arithmetic unit 3 determines which architecture - is recognized and the corresponding bit of mode register 305 is set to "t".

Now, for example, when an operating system according to system architecture-B is running, the system firmware recognizes this and sets bit 1 of the mode register 305 to '1' as shown in FIG. 3(B). Accordingly, the selection circuit 304 selects the read register 30
Out of the three outputs, the read register 303a is selected.

In other words, among the control memory 302, the conversion member)
The address data read from 302a is selected.

Each compartment 302a-30 of control memory 302
2d are microprogram start addresses ADD corresponding to instruction codes in architectures A to D, respectively.
(A) to ADD (D) are stored (see FIG. 4).

Therefore, when an instruction word is stored in the instruction register 301,
Instruction code 30! The address of the control memory 302 is specified in step a, the contents of the address are read from each compartment of the control memory 302 and set in the read register 303, and the selection circuit 304 selects the contents of the read register 303.
03b is selectively output. Then, when the instruction is activated, the contents of the read register 303b are changed to the address register 3.
08, the microprogram is read from the corresponding address in the control store 307, the microprogram starts execution, and the device is operated as a machine according to system architecture-B until the running operating system is changed. When the running operating system changes, the system firmware again sets the corresponding bit in the mode register 305 to "1" and reads the microprogram from the control store 307 in response to the instruction code of any operating system in the same manner as described above. By reading , it operates as a machine following any system architecture.

Effects of the Invention As described above, the present invention provides a control memory that stores instruction control information such as a microprogram start address corresponding to each instruction code, and a control memory that corresponds to a plurality of system architectures. a selection circuit that selectively selects the output of the memory, reads out a starting address of the microprogram corresponding to the instruction code from the control memory in accordance with the system architecture of the running operating system, and reads out the starting address of the microprogram corresponding to the instruction code from the control memory; Since it is configured to execute microprograms, it has the effect of enabling microprogram control that can support a plurality of system architectures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a mode register of the above embodiment, and FIGS.
(D) is a diagram showing the set information of the mode register when operating according to system architectures A to D, respectively, and FIG. 4 is a diagram showing the contents of each compartment of the control memory. In the figure, l: main storage device, 2: storage control unit,
3: Instruction control arithmetic unit, 301: Instruction register, 3
01a: Instruction code, 302: Control memory, 302a
~302d: =I partment, 303,30
3a to 303d: read register, 304: selection circuit, 305: mode register, 306: address register, 307: control store, 308: read register. Applicant NEC Co., Ltd. Agent Patent Attorney Toshisuke Sumita 1 Figure 2 Figure 3/j and Figure 4

Claims (1)

[Claims] Each of the plurality of compartments whose reading address is specified by the instruction code contains a control memory storing the start address of the microprogram corresponding to each instruction code in the plurality of architectures, and a plurality of microprograms consisting of a series of microinstructions. a mode register that stores system management information specifying which of a plurality of system architectures is to be followed by the output information of the control store; and a selection circuit that selectively selects a plurality of address information output from the control store and outputs a read address signal, etc. of the control store, thereby providing microprogram control capable of supporting multiple system architectures. An information processing device characterized by: