JPH03257572A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To shorten the data transfer time and to reduce the load of a secondary processor by storing a microprogram from the secondary processor with a memory write instruction given to a memory of the secondary processor itself. CONSTITUTION:A control program memory 23 is provided in a memory address of a secondary processor 10 in order to store a control microprogram that actuates a main processor 20. Then the processor 10 stores a memory write instruction into a memory of the processor 10 itself. Thus the processor 10 can store the microprogram into a control program of the processor 20 just by performing a writing operation to the memory of the processor 10 itself. Therefore it is not required for the processor 10 to transfer the data to the processor 20 for each word based on a program and with output of a data transfer instruction. As a result, the data transfer time is shortened and the load of the processor 10 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multiprocessor system having a general-purpose microprocessor that controls the entire system and a dedicated processor for processing data with a special structure at high speed.

(Prior Art) FIG. 4 is a block diagram showing an example of a multiprocessor system.

The illustrated system consists of a main processor 20 and a secondary processor 10.

The sub-processor 10 starts and stops the main processor and controls the equipment.

This sub-processor 10 is usually called a front-end processor.

The main processor 20 is a dedicated processor controlled by the sub-processor 10, and is, for example, a 64-bit long A
It has an LU 29 and a main storage device 32, and executes data processing that cannot be processed at high speed by the sub-processor 10.

In the sub-processor IO, a microprocessor 11 controls the entire system. Although the microprocessor 11 is not limited to a specific processor, the present invention will be described using an 8086.16-bit microprocessor manufactured by Intel Corporation.

The pass line 12 connects the microprocessor 11 and each I1
0 device and the main processor 20.

In the illustrated example, due to the conditions of the microprocessor 11 described above, it is composed of 16 data lines, 20 address lines supporting the IMB address space, and bus control signals.

The memory 13 is a memory on the sub-processor 10 side.

The floppy control device 14 controls a floppy magnetic disk device.

The hard disk control device 16 controls hard disk devices.

The keyboard/display control device 15 controls the keyboard and display device.

The main processor 20 is connected to the path line 12 on the sub-processor 10 side through an adapter control section 21.

The control program memory 23 is a rewritable memory in which a microprogram for controlling the main processor 20 is stored. The microprogram stored in this control program 23 is for operating the main processor 20 at high speed, and in order to control as many conditions as possible with one instruction, one word is usually 32 bits or 1 word. It is composed of 64 bits, etc.

In the illustrated example, the explanation will be given assuming that a microprogram with one word having a length of 32 bits and an address of 64 kilowords is adopted. 1
This requires a function equivalent to 64 kilowords in the address direction (microinstructions), and a commercially available SRAM with a 64 kilobyte x 4 bit configuration, as will be described later, can be used.

The switching gate 22 switches the address line input to the control program memory 23. This is to switch between the address information from the sub-processor 10 sent from the address register 33 and the address information from the sequencer 27 for controlling the execution of the microprogram. This address information is composed of 16 signal lines in order to support the 64 km address space of the control program memory 23.

The sequencer 27 specifies the address of the microprogram executed by the main processor 20 side.

The instruction decoder 25 is a control program 2
It specifies the address of each microprogram sent from 3. That is, the instruction decoder 25 is a microinstruction decoder that decodes each microprogram sent from the control program memory 23 and generates various control signals.

The instruction decoder 26 is a decoder for instructions sent onto the address line by the microprocessor 11 of the sub-processor 10, and executes control such as starting and stopping the main processor 20.

The bus controllers 28 and 30 are for controlling the flow of data on the internal bus on the main processor side.

Performs bit operations such as swapping the upper and lower bytes of data.

The control register 31 is a variety of control registers on the main processor side, and is composed of general-purpose registers, registers for interrupt processing, and the like.

In such a dedicated processor, the main memory 32 is devised to enable high-speed processing of data, such as one word or 64-bit length, for example.

The gate 24 is connected to the control register 31-? 1 sequencer 27
This is a switching gate for the sub-processor 10 to read the states such as.

FIG. 3 is a flowchart showing the control procedure of the multiprocessor system of FIG.

In the figure, in step S31, a microprogram for controlling the main processor 20 shown in FIG. 4 is loaded into the memory 13 of the sub-processor 10. It is assumed that this system control microprogram is stored in the floppy disk device 14 or hard disk device 16 in advance.

Next, in step S32, the microprogram loaded into the memory 13 of the sub-processor 10 is stored in the control program memory 23 of the main processor 20. In this case, in FIG. 4, the switching gate 22 selects the address lines from the address register 33 and sequentially stores them in the control program memory 23, but the details will be described later. Subsequently, in step S33, the microprocessor 11 of the sub-processor 10 sends a startup command to the main processor 20. This startup command is decoded by the command decoder 26 shown in FIG. 4, and the main processor 20 side starts operating. In this case, since the switching gate 22 selects the address line from the sequencer 27, the microprograms to be executed are sequentially output from the control program memory 23, and necessary processing is executed.

In step S34, the microprocessor 11 of the sub-processor 10 is in a state of waiting for an operation end interrupt from the main processor 20 side. When an interrupt occurs, in step S35, the microprocessor 11 of the sub-processor 10 clears the interrupt at the end of the operation, etc. After reading the operation end status stored in the control register 31 in FIG. 4, it is determined in step S36 whether or not the operation has ended normally, and the series of operations is completed.

Next, details of the operation of sequentially storing microprograms in the control program memory in step S32 in FIG. 3 will be explained.

FIG. 2 is a circuit diagram showing the main peripheral configuration of a conventional control program memory.

The memories 41 to 48 are for storing microprograms, and are composed of commercially available SRAMs. For example, this SRAM is 64 kg x
A 4-bit configuration SRAM is available, and the memory 41
~44 stores the upper 16 bits of the microprogram, and memories 45~48 store the lower 16 bits of the microprogram.
It stores a total of 32 bits x 64 kilowords of microprograms.

The address line 50 is an address line to the control program memory 23, and is composed of 16 signal lines to support an address space of 64 kilobytes.
This signal is supplied to all SRAMs. Furthermore, the second
In the figure, address lines for the memories 42 to 48 are omitted.

The gate 51 is a gate for switching the address line, and when the selection signal S is "0", the B signal is selected and "
1'', the A signal is selected.

Address signal 52 is an address signal from sub-processor 10.

Address register 53 is set in control program memory 23 when sub-processor 10 accesses control program memory 23 . This address register 53
is 16 bits long.

This address register 53 corresponds to the address register 33 in FIG. 4. A data bus 54 is connected from the sub-processor 10.

Data bus 54 has a width of 16 bits. This signal is connected to the ADP 21 in FIG. Gates 55 and 56 control whether the signals on data bus 54 are output to control program memory 23 or not. gate 5
5.56, the output becomes valid when the G signal is at the "O" level. Gates 55 and 56 are respectively D31~
This is for controlling D16 or D15 to Do.

The instruction decoder 57 corresponds to the instruction decoder 25 in FIG. 4 and generates various control signals for the main processor. The instruction decoder 58 corresponds to the instruction decoder 26 in FIG. 4, and decodes instructions from the sub-processor 10 and generates various control signals.

In the illustrated example, four types of signals are output: address set, upper set, lower set, and write signal. These signals are all negative outputs. The address set signal is sent to the address register 53.
This is used to set the storage address to the control program memory 23. The upper set and lower set each have memories 41 to 41 constituting a control program memory.
A signal line that controls whether to set data in memory 44 (16 bits of upper D31 to D16) or to memories 45 to 48 (16 bits of lower D15 to Do) that constitute the control program memory. It is. Also,
The WR multiplication signal is a timing signal for storing data in the control program memory, and is used to generate a timing signal that matches the characteristics of the SRAM used in the control program memory. The RUN signal 59 is at the "O" level while the main processor is operating. This signal line is connected to the lead terminal of the SRAM of the control program memory 23, and always enables the output of the control program memory 23 when the main processor 20 is in operation.

Further, the RUN signal 59 is applied to the switching gate 51 of the address line.
When the main processor is in operation, the address line from the B-side sequencer is always input to the control program memory 23. gate 60
．． 61 are control program memories 41 to 44 and 4, respectively.
This is for creating a 5 to 48 WR multiplied signal. In the illustrated example, it operates as an AND gate of negative signals.

FIG. 5 is a flowchart showing the procedure for writing a microprogram into the control program memory.

In FIG. 5, first, in step S51, address information for storing the microprogram in the control program memory is set. In this case, the microprocessor 11 in FIG. 4 sends an address set command to the main processor 20. This command is decoded by the command decoder 58 of FIG. 2 and becomes an address set signal. The storage address of the control program memory is set in the address register 53 of FIG. 2, and this signal is further supplied through the gate 51 as address information of the control program memories 41-48.

When the S signal of the gate 51 is set to the control program memory 23, the RUN signal is at the level "1" because the main processor 20 is not in operation, and the A signal is selected. .

Next, in step S52, D3 of the microprogram is
Data 1 to D16 are stored in control program memories 41 to 44.
The data is stored in the SRAM. In this case, the microprocessor 11 in FIG. 4 sends an upperset command to the main processor 20, this command is decoded by the command decoder 58 to become an upperset signal, and this signal causes the G signal of the gate 55 to , becomes “O” level,
The output becomes valid, and the contents of microinstructions D31 to D16 carried on the data line are stored in the control program memories 41 to 44.

Next, in step S53, the microprogram DI
The data of 5 to Do are stored in the control program memories 45 to 48. In this operation, the lower set signal is output in the same manner as in step S52, and the contents of microinstructions D15-Do carried on the data line are stored in the control program memories 45-48.

Next, in step S54, the microprocessor 11 of the sub-processor 10 determines whether or not the final address has been set, and all microprograms are executed by repeatedly executing steps S51 to S54 until the final instruction is set. The operation of storing in the control program memory is completed.

(Problems to be Solved by the Invention) However, the multiprocessor system configured as described above has the following problems.

That is, in order to set a microprogram in the control program memory, it is necessary for the subprocessor to transfer data word by word according to the program according to the sequence shown in FIG. 5, which has the drawback that it takes a long time to complete the transfer. .

For example, in the case of the conventional example mentioned above, the structure of the microprogram is 64 kilowords x 32 bits, so 1
Even when transferring data in units of 6 bits, 65536x
2 = 131072 data transfers are required,
Also, since the address register needs to be set 65,536 times, assuming that the execution speed of the I10 instruction on the sub-processor side is approximately 10 μs/time, the total processing time T is: T = (131072 + 65536) x 10 μS 4
It took 1.9 seconds, which had the disadvantage that it took time to start up the main processor.

In addition, in normal cases, the program written to the control program memory of the main processor is rewritten as needed according to the needs of the system, and the maximum processing time is approximately 1.
．． The fact that it took 9 seconds was a factor that reduced the response of the system, and was not technically satisfactory.

Another disadvantage was that the load on the subprocessor increased.

The present invention has been made with attention to the above points, and eliminates the problem that it takes time to set a microprogram in the control program memory of the main processor in a multiprocessor system, and lightens the load on the sub processor. The purpose is to provide an easy-to-use multiprocessor system.

(Means for Solving the Problems) A multiprocessor system of the present invention includes a sub-processor having a file device storing a microprogram to be transferred to a control program memory of a main processor, and a sub-processor for transfer from the sub-processor to the control program memory. In a multiprocessor system in which main processors that operate according to a microprogram are connected by a bus, a control program memory for storing a control microprogram that operates the main processor is located at a memory address of the subprocessor, and the This system is characterized in that a microprogram is stored by a memory write instruction from a subprocessor to its own memory.

(Operation) According to the multiprocessor system of the present invention, the sub-processor can store a microprogram in the control program of the main processor simply by performing an operation of writing it into its own memory.

Therefore, there is no need for the sub-processor to issue a data transfer command to the main processor using a program to transfer data word by word. Therefore, data transfer time can be significantly reduced.

(Embodiment) FIG. 1 is a block diagram showing the configuration of main parts of a multiprocessor system of the present invention.

This figure shows only the peripheral portion of the control program memory of the multiprocessor system of FIG. 4 described above.

The memories 41 to 48 are for storing microprograms, and are composed of commercially available SRAMs. For example, this SRAM is 64 kg x
A 4-bit configuration SRAM is available, and the memory 41
~44 stores the upper 16 bits of the microprogram, and memories 45~48 store the lower 16 bits of the microprogram.
It stores a total of 32 bits x 64 kilowords of microprograms.

The address line 50 is an address line to the control program memory 23, and is composed of 16 signal lines to support an address space of 64 kilobytes.
This signal is supplied to all SRAMs. Furthermore, the first
In the figure, address lines for the memories 42 to 48 are omitted.

The gate 51 is a gate for switching the address line, and when the selection signal S is "O", the B signal is selected and "
1'', the A signal is selected.

Address signal 52 is an address signal from sub-processor 10.

In FIG. 1, the main processor 2
A control program memory 23 for storing a control microprogram for operating the subprocessor 10 is located at a memory address of the subprocessor 10. That is, the address register 53 shown in FIG. 2 is not used, and the switching gate 51
Sixteen address lines A17 to A2 from the sub-processor 10 are connected to the six input signal lines 64. As a result, the microprogram is stored in the memory 13 (see FIG. 4) from the sub-processor 10 by a memory write command of the sub-processor 10 itself.

Further, among the outputs of the instruction decoder 58, the address set, upper set, and lower set signals are not used, and the address decoder 70, inverter 71, and gate 72
．． 73 circuits have been added.

The address decoder 70 outputs a negative (low level) signal when the address lines A19 and A18 are A19="1" and A18="0", respectively, and the MW (memory write) signal is valid. This signal is transmitted to inverter 7
1, AND conditions are determined in gates 72 and 73, and lower cell and upper cell signals (negative output) are output, respectively. Since the address line A1 is input to the inverter 71, the OR gate 72 inputs the address line A1.
When address = “0”, the AND condition of the “○” signal is established and the lower cell signal is output, and conversely, when address A1 = “1”, OR gate output cuff 3 is enabled and the upper cell signal is output. Output.

FIG. 6 is a diagram showing an address area of a control program memory according to the present invention.

FIG. 6(a) is a diagram showing an address selection signal for the control program memory, as will be described later.

FIG. 6(b) is a diagram showing memory mapping of the sub-processor.

Next, the operation of the multiprocessor system configured as described above will be explained.

With the above-described circuit configuration, the control program memory is arranged in the memory space of the microprocessor 11 shown in FIG. 4 as shown in FIG.
), address area 80000 (HEX)
~8FFFF (HEX)! ::The microprocessor 1 of the 10 sub-processors has been positioned.
1, just write to your memory,
It becomes possible to store microprograms in the control program memory 23.

For example, when a memory write is executed to address 80 (100 (HEX)), since Al of the address line is “O”, the lower cell signal of gate 72 in FIG. The output becomes valid and the data on data line 54 is stored in control program memories 45-48.
is input. At this time, the six inputs of the switching gate 51 are selected as the address to the control program memory.
Data on address lines A17 to A2 is input, and 0
Since the address is 000 (HEX), SRAM45
The data of one lower word (16 bits) of the microinstruction is stored at address 0000 (HEX) of 48 to 48. Similarly, when a memory write is executed to address 80002 (HEX), the upper cell signal of gate 73 is valid because A1 of the address line is "1"
Similarly to the conventional example described above, the control program memory 41 to
Data for one upper word (16 bits) of the microinstruction is stored at address 44(7)0000 (HEX).

This completes the storage of the first 32 bits of the microprogram, and then executes a memory write to address 80004 (H ~A23D
OO1 (HEX), and the microprogram will be stored at address 0001 of the control program memory 23. The above operation is performed at address BFFFF (HEX
) control program memory 2 by repeating up to the address
It becomes possible to store all microprograms within 3.

FIG. 6(a) is a diagram showing the address selection signal of the control program memory as described above.

That is, in this figure, the upper cell and lower cell are switched by the Al signal, 64 kilowords of control program memory address are selected by 16 bits of A17 to A2, and A19="
1” and A18="O" indicates that the control program memory selection area is selected.

As explained above, according to the present embodiment, when storing a microprogram in the control program memory, the microprocessor 11 on the sub-processor 10 side only needs to execute a store instruction for its own memory.
If the execution time of each store instruction is 1 μs, the processing time T required to transfer 256 kilobytes of the microprogram is T = (65536 x 2) The time is shortened and the load on the sub-processor side can be reduced.

In this embodiment, the address area is set as shown in FIG. 6(b), but it goes without saying that this can be freely selected depending on the conditions of the processor used in the system. In the example of FIG. 1, only the memory write operation from the sub-processor is shown, but it goes without saying that the read operation can also be handled by partially modifying the circuit. Further, according to the present invention, since the control program memory functions as a memory on the sub-processor side, a microprogram is stored in advance in a floppy disk or hard disk on the sub-processor side, and the control program memory is directly transferred to the control program memory by DMA transfer or the like. It is also possible to store microprograms in the microprocessor, and the load on the subprocessor can be significantly reduced.

(Effects of the Invention) As described above, according to the present invention, the control program memory on the main processor side is arranged in the memory space on the sub-processor side, so that the following effects can be obtained.

In other words, in order to store a microprogram from the subprocessor to the control program memory, it is sufficient to simply execute a memory write instruction in the subprocessor. This makes it possible to reduce the processing load due to

Further, according to the present invention, since the control program memory functions as a memory on the sub-processor side, a microprogram is stored in advance on a floppy disk or hard disk on the sub-processor side, and is directly transferred to the control program memory by DMA transfer. It is also possible to store microprograms, and the load on the subprocessor can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a peripheral circuit of a control program memory according to the present invention, FIG. 2 is a block diagram showing a peripheral circuit of a conventional control program memory, and FIG. 3 shows a control procedure of the multiprocessor system of FIG. FIG. 4 is a diagram showing an example of a multiprocessor system,
FIG. 5 is a flowchart showing a sequence for storing a microprogram, and FIG. 6 is a diagram showing an address area of a control program memory according to the present invention. 10... Sub-processor, 20... Main processor, 2
3... Control program memory, 52... Bus, 57
...Instruction decoder, 58...Instruction decoder. 70-cha Figure 3 to Figure 5 16 Pit memory 7 dress '9I area diagram during normal operation

Claims (1)

[Scope of Claims] A sub-processor having a file device that stores a microprogram to be transferred to the control program memory of the main processor, and a main processor that operates based on the microprogram transferred from the sub-processor to the control program memory, In a multiprocessor system connected by A multiprocessor system characterized by storing microprograms using a memory write instruction.