JP3006487B2 - Emulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation device using a microcomputer for controlling operation by a built-in microprogram, and more particularly to an emulation device using an evaluation microcomputer for developing an application device.

[0002]

2. Description of the Related Art Today, with the diversification of microcomputers (hereinafter, referred to as microcomputers), microcomputers of a microprogram system, whose operation is controlled by a microprogram built in the microcomputer itself, have become mainstream.

[0003] Such a microprogram type microcomputer has an advantage that, since various types of microprograms are incorporated in the microcomputer itself, different processes can be executed by the same hardware, so that the range of application is widened.

In such a microcomputer, the microprogram is stored in a ROM called a microROM in the microcomputer. Therefore, an evaluation microcomputer (hereinafter referred to as an evaluation chip) used for developing an application device using the microcomputer has to be configured in the same manner as a general microcomputer. That is, the microprogram for controlling the operation of the evaluation chip needs to be stored and held in the ROM in the evaluation chip.

[0005] However, the microprogram is stored in the internal ROM.
In an emulation device using an evaluation chip having a format stored in the CPU, simple function expansion such as expansion of an instruction set of a CPU core unit is troublesome when the evaluation chip is developed. For example, as described on pages 508 to 541 of “User's Manual μPD784040 Series 16 / 8-bit Single-Chip Microcomputer (Tentative Version)”, a new macro service function is added to the provided macro service function. If so, the corresponding microprogram must be added to the ROM. However, a new program cannot be added to a ROM that has already been manufactured. Therefore, even if only a small part of the microprogram is changed or added, the evaluation chip must be renewed for each change, resulting in cost and time.

Therefore, conventionally, a RAM instead of a ROM is built in the evaluation chip, and a microprogram for operation control is written into the RAM from outside of the emulation device when the emulation device is started, thereby coping with the change of the microprogram. . In this case, a temporary storage memory for temporarily storing an externally input operation control microprogram is provided in the emulation device, and the externally input microprogram is temporarily stored in the temporary storage memory when the emulation device is started. The microprogram is written from the temporary storage memory to the RAM in the evaluation chip. FIG. 5 shows a block diagram of such an emulation device.

FIG. 1 shows only a configuration necessary for writing a microprogram from outside the emulation device to a RAM in an evaluation chip, and omits other peripheral circuits. Note that an external host machine (not shown) is connected to the supervisor CPU 101, and communication between the emulation device and the outside is performed through the supervisor CPU. This operation mode is called a privilege mode or a supervisor mode.

As shown in the figure, a conventional emulation device includes an evaluation chip 100, a supervisor CPU for controlling the emulation device by communicating with the emulation device and a host machine outside the emulation device, and communicating with the evaluation chip 100 in the emulation device.
101, a control unit 501, an emulation memory 503 for replacing a program memory area of a user and a memory inside the microcomputer, and a temporary storage memory 502 for temporarily storing a microprogram input from an external host machine. I have.

The evaluation chip 100 includes an address bus EMA.
The emulation memory 503 and the temporary storage memory 502 are accessed via the data bus 104 and the data bus EMD105. EMRD111 and EMWR113 are a read signal and a write signal for the emulation memory 503, respectively. The MDLC 112 converts the microprogram stored in the temporary storage memory into an internal RA.
This is a microprogram load strobe signal to be loaded into M100. The SVMOD 110 transfers control of the emulation device to the evaluation chip or the supervisor CP.
It is a signal for switching whether to pass to U101.

The supervisor CPU 101 communicates with the outside of the emulation device, and accesses the emulation memory and the temporary storage memory via the address bus SA106 and the data bus SD107. SVRD 116 and SVWR 117 are a read signal and a write signal for the emulation memory 503, respectively. The SVWR is also used as a write strobe signal when a microprogram is externally written to the temporary storage memory.

FIG. 6 is a block diagram showing the configuration of the control unit 501. The control unit 501 includes an address selector 300,
Data selector 301, address decoder 601, NO
R gates 602 and 304, OR gate 305 and NA
An ND gate 306 is provided.

In response to the above-mentioned signal output from the evaluation chip or the supervisor CPU, the control unit 501 connects the address bus 108 and the data bus 109 to EMA, EMD, or SA and SD, respectively, and controls the chip for emulation memory. A select signal 118, a memory read 119 as a read strobe signal, a memory write 120 as a write strobe signal, and a chip select signal 503 for a temporary storage memory are output.

Conventionally, in the emulation apparatus configured as described above, when the emulation apparatus is started, the microprogram is loaded from the temporary storage memory to the RAM incorporated in the evaluation chip to cope with the change of the microprogram. I was Incidentally, this type of technique is disclosed in, for example, JP-A-60-186934 and JP-A-61-84737.

[0014]

As described above, in the conventional emulation device which can input a microprogram from the outside, in addition to the emulation memory as a memory area necessary for operating the user program area and the evaluation chip, It is necessary to separately provide a memory for temporarily storing a microprogram. Therefore,
It is necessary to route the address bus and the data bus not only to the emulation memory but also to a memory for temporarily storing a microprogram. Therefore, there is a disadvantage that the pattern area is increased by the length of the bus and the emulation device becomes large.

In particular, today, as microcomputers become more sophisticated and faster, the number of interfaces using microprogram address and address / data buses is increasing, and the pattern area due to the routing of the bus is also increasing. On the other hand, demands for downsizing of devices and cost reduction of products are increasing today.

In high-speed operation, the influence of noise due to an increase in the area of the bus wiring cannot be ignored. In order to reduce the influence of the noise as much as possible, it is necessary to examine the substrate pattern, which causes another disadvantage that the number of design steps is increased.

Therefore, from the viewpoint that a reduction in the substrate area due to downsizing and a reduction in design man-hours due to a shortened product life cycle are required, the micro RO
It is preferable to use design resources of an emulation device using an M-type evaluation chip (in this case, only the emulation memory is required) as much as possible.
In other words, it is more economical to add a circuit without modifying the existing circuit part as much as possible, since it is possible to suppress an increase in the number of evaluation steps and the like.

An object of the present invention is to provide an emulation which uses an evaluation chip for storing a microprogram in a built-in RAM and which can avoid an increase in a bus and an increase in a pattern area of a substrate while having means for temporarily storing a microprogram. It is intended to provide a device.

[0019]

To achieve the above object, the present invention provides an evaluation microcomputer having a rewritable microprogram storage means, an alternative means for substituting a user program storage means, and a privileged mode processing. And a control means for controlling the operation of each section, wherein the substitute means secures an area for temporarily storing a microprogram for operation control stored in the evaluation microcomputer. It has a configuration.

In another embodiment, the evaluation microcomputer is provided with the microprogram storage means, an execution means for executing an instruction described in a microprogram stored in the microprogram storage means, and an external input. And a strobe signal generation means for generating a strobe signal for writing the microprogram into the microprogram storage means when the reset signal is at an active level.

In another preferred embodiment, the control means selects and outputs one of address data from the evaluation microcomputer or the privileged mode processing microcomputer, Second selecting means for selecting and reading one of the operation control microprogram or data other than the microprogram from the data stored in the means; and the evaluation microcomputer reading the microprogram from the alternative means. And data read / write means for writing to the microprogram storage means.

According to the present invention, in an emulation apparatus using an evaluation microcomputer having a rewritable microcomputer program storage means, an alternative means for substituting a user program storage means stores the user program in the evaluation microcomputer. By securing an area for temporarily storing a control microprogram, a microprogram to be written to the evaluation microcomputer can be stored without physically adding any configuration.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a preferred embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the emulation device of the present invention. In the drawings, elements having the same configuration and function as those of the related art are denoted by the same reference numerals as those of the related art. In the figure, only a configuration necessary for writing a microprogram from outside the emulation device to the RAM in the evaluation chip is described, and other peripheral circuits are omitted.

An external host machine (not shown) is connected to the supervisor CPU 101, and communication between the emulation device and the outside is performed by the supervisor CP.
Via U.

Emulation memory 1 of the present embodiment
In a storage area 03, a microprogram for operation control is temporarily stored in addition to a storage area for storing user programs and data (hereinafter, general data) necessary for the evaluation chip to execute an instruction execution process. And a microprogram storage area 103A that stores the program.

When a supervisor interrupt request signal input from outside the emulation device becomes active (privileged mode), the supervisor CPU 101 outputs addresses and data sent from the host machine to the address bus SA106 and the data bus SD107. Then, the user program is written in the general data storage area in the emulation memory 103, and the microprogram for operation control is written in the temporary storage area 103A.

The control unit 102 controls the emulation memory 10 by the evaluation chip 100 and the supervisor CPU 101.
3 is controlled by various control signals output from the evaluation chip 101 and the supervisor CPU 101.

Here, the active level of each control signal is
SVMOD110 = “1”, EMRD111 = “0”,
MDLC 112 = “0”, EMWR 113 = “0”, power ON input 114 = “1”, RBSET 115 =
“0”, SVRD116 = “0”, SVWR117 =
“0”, chip select 118 = “0”, memory read 119 = “0”, memory write 120 = “0”, SVI
RQ121 = “1”. In addition, EMR
D, EMWR, SVRD and SVWR are mutually exclusive, and do not become active level at the same time.

FIG. 2 is a block diagram showing a configuration of the evaluation chip 100 which is one of the components of the present embodiment.

The evaluation chip 100 has a flip-flop 2
00, an inverter 201, an execution unit 202, and a supervisor flag 203.

The output of the flip-flop 200 becomes “1” only when the power ON input 114 is “1” and the RESET 115 is “0”.
DLC 112 becomes “0”.

In the execution unit 202, the output of the flip-flop 200 is "1" and the SVMOD 110 is "1".
In this case, the address of the microprogram storage area 103A in the emulation memory 103 is output to the EMA 104, and the microprogram data is input from the EMD 105 to the micro RAM 204.

On the other hand, when the SVMOD 110 is “0”, the execution unit 202
3 for executing an instruction based on the user program. At this time, the execution unit 202 executes EMA for accessing the emulation memory 103.
An address is output to an EMD 104, data is input and output to and from an EMD 105, and a read signal
The MRD 111 and the write signal EMWR 118 are output.

The execution unit 202 executes an instruction "R" for returning from the supervisor mode in the user program.
RETSVI205 when executing "ETSVI instruction"
Is set to “1” and output.

The supervisor flag 203 is set when the supervisor interrupt request signal SVIRQ 121 from the outside is "1", and is a reset signal RES.
The reset is performed when the ET 115 is “1” or the RETSVI 205 indicating that the ET 115 has returned from the supervisor interrupt is “1”. An output signal of the supervisor flag 203 is a signal SVMO indicating whether or not a supervisor mode is being performed.
It is output from the evaluation chip 100 as D110. Here, when SVMOD is "1", it indicates the supervisor mode.

FIG. 3 is a block diagram showing the configuration of the control unit 102 which is one of the components of the present embodiment.

As shown, the control section 102 comprises an address selector 300, a data selector 301, an address decoder 302, NOR gates 303 and 304, an OR gate 305, and a NAND gate 306.

The address selector 300 has the SVMOD1
When 10 is “0” or when SVMOD 110 is “1”
When the MDLC 112 is "0", that is, when the NAND
When the output of the gate 306 is “1”, the value of the EMA 104 is output to the address bus 108. Also, SVMOD1
When 10 is “1” and the MDLC 112 is “1”, that is, when the output of the NAND gate 306 is “0”, SA1
06 is output to the address bus 108.

The address decoder 302 receives the output signal of the NAND gate 306 and the value of the address bus 108 and outputs a chip select 118.

Here, the address mapping of the general data storage area of the emulation memory 103 viewed from the supervisor CPU 101 is "0 to FFFFh", and the address mapping of the microprogram storage area 103A is "10000 to 1FFFFh". Then, the chip select 118 is configured to be "0" when SVMOD110 = "1" and the value on the address bus is output from "10000 to 1FFFFh".

The memory read 119 output from the NOR gate 303 becomes active level "0" when any one of the EMRD 111, SVRD 116 and MDLC 112 is "0". Similarly, the memory write 120 output from the NOR gate 304 is output from the EMWR 112 or the SV.
When one of the WRs 117 is “0”, the active level becomes “0”.

Data selector 301 outputs the value of EMD 105 or SD 107 to data bus 109 when DIR 307 is “0”, and outputs the value of data bus 109 to EMD 105 or SD 107 when DIR 307 is “1”.
Take it into 107. At this time, the EMD 105 is selected when the output signal of the NAND gate 306 is “1”, and the SD 117 is selected when the output signal is “0”.

Next, referring to the time chart of FIG.
An operation of writing a microprogram from the external host machine connected to the supervisor CPU 101 to the microprogram storage area 103A in the emulation memory and writing the written microprogram to the microRAM 204 in the evaluation chip 100 will be described.

First, the supervisor CPU 101
A sequence for storing a microprogram in the emulation memory 103 will be described.

First, "1" is input to RESET 115, "0" is input to power ON input 114, and "0" is input to SVIRQ 121.
Are input from outside. As a result, the supervisor flag 203 is reset and its output SVMO
D110 becomes “0”. Further, the output of the flip-flop 200 in the evaluation chip 100 becomes “0”, and the MDL
C112 becomes "1". Thereafter, RESET 115 is set to “0” and SVIRQ 121 is set to “1”. F / F2
The output of 00 is unchanged and the MDLC 112 maintains “1”,
On the other hand, SVMOD 110 becomes “1” because the supervisor flag 203 is set.

SVMOD110 is "1" and MDLC1
Since 12 is “1”, the output signal of the NAND gate 306 in the control unit 102 becomes “0”. NAND gate 30
6 is "0", the address selector 300 outputs
A 106 is connected to the address bus 108, and the data selector 301 connects the SD 107 to the data bus 109.

After that, the supervisor CPU 101
The process of storing the micro program in the emulation memory 103 is started. The sequence is as shown below.

1-1) Supervisor CPU 101
Outputs the microprogram write start address “10000h” in the 103A to the SA 106 and the microprogram data sent from the outside to the SDI07.

1-2) Then, the supervisor CPU
Sets only SVWR 117 to “0”. As a result, the output of the OR gate 304 in the control unit 102 becomes 0, and the memory write signal 120 becomes “0”.

1-3) The output of the NAND gate 306 is "0", and the output DIR307 of the OR gate 305 is "0".
The address selector 300 outputs the value of SA106 to the address bus 108, and the data selector 301
The data of D107 is output to the data bus 109.

1-4) The value of the address bus 108 is "10
000h ”and the output of the NAND gate 306 is“ 0 ”, so that the address decoder 302 outputs the chip select 118 as“ 0 ”.

1-5) Therefore, the data of the microprogram is written at the address “10000h” in the microprogram storage area 103A.

1-6) Next, the supervisor CPU 1
01 increments the SA and outputs the next data sent from the external host machine to the SD 107.

By repeating the above steps 1-1) to 1-5) until the microprogram write end address "1FFFFh" is output, all the microprograms are written in the area 103A.

Next, the microprogram written in the area 103A is stored in the micro RAM in the evaluation chip 100.
A sequence for writing to the memory 204 will be described.

First, RESET 115 is "0" and SVI
The power ON input 114 is set to “1” while the RQ 121 remains “1”. Therefore, the output of the flip-flop 200 in the flip-flop 100 becomes “1”, and the MDLC 112 becomes the active level “0”.

When SVMOD110 is "1" and MDLC1
Since “12” is “0”, the output signal of the NAND gate 306 in the control unit 102 becomes “1”, and the output of the OR gate 303 becomes “0”. At this time, the address selector 30
0 sends the value of the EMA 104 output from the evaluation chip to the address bus 108, and the data selector 301 connects the data sent from the emulation memory 103 via the data bus 109 to the EMD 105 so as to be output.

Next, the evaluation chip 100 starts the process of reading the microprogram from the area 103A and storing it in the microRAM 204 inside the evaluation chip 100. The sequence is as shown below.

2-1) EVA chip 100 is MA104
, The microprogram reading start address “10000h” in the area 103A is output.

2-2) Since the output of the NAND gate 306 is "1" and the output of the OR gate 305 is "0",
The address selector 300 outputs the value of the EMA 104 to the address bus 108. The data selector 310 outputs data on the data bus 109 to the EMD 105.

2-3) Since the memory read signal 119 is "0" because the MDLC 112 is "0", the data of the microprogram at the address "10000h" of the area 103A is read out to the data bus 109, and Data on the bus 109 is sent to the EMD 105.

2-4) The microprogram data read out to the EMD 105 is written to the address “10000h” (the microprogram reading start address output to the EMA 104) of the micro RAM 204.

2-5) The evaluation chip 100 increments the EMA and repeats 2-1) to 2 until the microprogram write end address "1FFFFh" is output.
By repeating the sequence of -3), all microprograms are stored in the micro R
Write to AM204.

In the above, the microprogram is stored in the temporary storage area 103A, or the microprogram stored in the 103A is stored in the micro RAM in the evaluation chip.
Only the description of the operation to be written in is described. When the user program is written in the general data area, the operation is the same as that described above except that the address is for the general data area. When the supervisor signal SVMOD is “0”, the evaluation chip is in the emulation memory 1.
It goes without saying that the instruction is executed based on the instruction of the user program in the general data storage area 03.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to these embodiments.

[0067]

As described above, according to the present invention,
A microprogram to be written into the evaluation microcomputer can be stored without physically adding any configuration, and it is possible to easily cope with a change in the microprogram. Therefore, it is possible to use the existing hardware resources as they are and to reduce the number of evaluation steps,
It is economical.

Further, by using the existing hardware resources as they are, it is possible to prevent the pattern area on the substrate from increasing.

Furthermore, downsizing of the emulation device and significant cost reduction can be achieved.

Also, the circuit of the control unit may be a gate array or a PL.
The configuration using D is more effective because there is no need to increase hardware resources at all.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an emulation device according to an example of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an evaluation chip of the embodiment.

FIG. 3 is a block diagram showing a configuration of a control unit according to the embodiment.

FIG. 4 is a timing chart showing the operation of the emulation device according to the embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional emulation device.

FIG. 6 is a block diagram showing a configuration of a control unit used in a conventional emulation device.

[Explanation of symbols]

 Reference Signs List 100 evaluation chip 101 supervisor CPU 102 control unit 103 emulation memory 103A microprogram storage unit 204 microRAM

Claims (9)

(57) [Claims] 1. A first microcomputer having a rewritable first RAM for storing a microprogram for operation control, a rewritable second RAM for storing a user program, and an external interrupt instruction A second microcomputer for controlling a privileged mode such as an interrupt process when a command is input, and a microcomputer and the second RAM based on various controls output from the first and second microcomputers. And a control unit for controlling communication of the first RAM.
An emulation device having a temporary storage area for temporarily storing a micro program stored in a RAM of the emulation apparatus. 2. The first microcomputer according to claim 1, further comprising: an execution unit configured to execute a microprogram command stored in said first RAM; and first and second control signals input from outside. A first logic circuit for generating a read strobe signal to the temporary storage area, and a second logic circuit for generating a privileged mode signal indicating entering the privileged mode based on a third signal input from outside 2. The emulation device according to claim 1, comprising: Wherein the control unit is configured when the privileged mode signal and the read strobe signal at an active level of non-active level, the micro-program input from the outside through the second microcomputer one o'clock Storing the microprogram stored in the temporary storage area to the first RAM when the privilege mode signal is at an active level and the read strobe signal is at an active level. 3. The emulation device according to claim 2, wherein: 4. The control unit according to claim 1, wherein the control unit selects one of the address data from the first and second microcomputers and outputs the selected address data to the second RAM. Second input means for connecting the input / output data bus to one of the input / output data bus of the first microcomputer and the data bus of the first microcomputer; When the mode signal is active and the read strobe signal is inactive, an address output from the second microcomputer is selected, and the privileged mode signal is activated.
And when the read strobe signal is active,
The address selected by the first microcomputer is selected. The second selecting means selects the data bus of the first microcomputer when the privileged mode signal is inactive, and the privileged mode signal is activated. And the data bus of the second microcomputer is selected when the read strobe signal is inactive.
The privileged mode signal is active and the read
When the strobe signal is active, the first micro
3. The emulation device according to claim 2 , wherein a data bus of the computer is selected . 5. The emulation device according to claim 1, wherein the first microcomputer is an evaluation microcomputer used for developing an application device using the microcomputer. . 6. An evaluation microcomputer having a rewritable microprogram storage means, an alternative means for substituting a user program storage means, a microcomputer for performing a privileged mode process, and controlling the operation of each section. An emulation device, comprising: a control unit; and wherein the substitute unit secures an area for temporarily storing a microprogram for operation control stored in the evaluation microcomputer. 7. The evaluation microcomputer, wherein: the microprogram storage means; an execution means for executing an instruction described in a microprogram stored in the microprogram storage means; and a reset signal input from the outside. 7. The emulation device according to claim 6, further comprising: a strobe signal generation unit that generates a strobe signal that writes the microprogram to the microprogram storage unit when the microprogram is at an active level. 8. The emulation device according to claim 7, wherein said microprogram storage means is a micro RAM. 9. A control device comprising: first selection means for selecting and outputting one of address data from the evaluation microcomputer or the privileged mode processing microcomputer; and data stored in the substitute means. Second selecting means for selecting and reading one of the operation control microprogram or data other than the microprogram, and reading the microprogram from the alternative means to the microprogram storage means of the evaluation microcomputer. 7. The emulation device according to claim 6, further comprising: a data read / write unit for writing.