JPS60217386A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a display controller used in a computer terminal or a video game device, and particularly relates to an increase in the number of moving image patterns that can be displayed on a horizontal scanning line. This invention relates to a display controller designed to

[Prior art]

In recent years, display devices such as video game machines have become capable of displaying moving images and still images together. For example, when displaying a video of a bird flying, the bird pattern (this pattern itself is constant) is composed of a dot pattern of about 8 x 8 pixels, and this is stored in memory in advance as a display unit. A moving image is obtained by sequentially shifting the display position and displaying the images. Additionally, the background can be displayed as a still image.

By the way, in conventional display controllers, the number of moving image patterns that can be displayed on the -horizontal scanning line is small (for example, 4 patterns), which is a constraint on the screen configuration.

The reason for this will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a conventional display controller. In this figure, reference numeral 1 denotes a CPU, which displays a desired screen on a CRT display device 3 via a display controller 2. Further, 4 is a memory that provides various programs, work areas, etc. to the CPUI, and 5 is a VRAM (video RAM). As shown in FIG. 2, the VB and AM5 include a still image pattern table 5a that stores still image patterns in the form of dot patterns, a still image control table 5b that stores the display position of still image patterns, and a still image control table 5b that stores each still image pattern. It has a still image color table 5c for storing image pattern color codes (4 pits), a moving image pattern table 5d for storing moving image patterns, and a moving image control table 5e for storing display positions of moving image patterns. Here, as shown in FIG. 3(f), the moving image pattern table 5d includes 256 moving image patterns PO, Pl, P2, .
・It consists of P2S5, and the video control table 5e is shown in the same figure (
As shown in (b), it consists of 32 tables CD, CI, C2, . . . , C31 each consisting of 4 bytes.

Then, each video control table Ck (k=D, 1...3
1) includes the selected video pattern pi (i-0, 1
, 2...255) (third byte), the X coordinate (second byte) of the display position of this video pattern Pi, and the
Coordinates (first byte 0, a color code that defines the color of the moving image pattern Pi, and an EC pit (fourth byte) to be described later) are stored.

As shown in Fig. 4, the display position (X, Y) is determined by using the upper left corner of the screen as the origin (o+o), and with the origin as a reference, the number of pixels in the horizontal right direction is X, and the number of pixels in the vertical downward direction is The position where the number of pixels is Y indicates the upper left end of the displayed moving image pattern Pi. 5 Next, the display controller 2 will be explained.

First, the timing signal generation circuit 6 generates a basic clock, and forms horizontal and vertical synchronization signals based on the timing.
In addition to supplying the RT display device 3, a clock pulse is also supplied to the horizontal counter 7. horizontal counter 7 with
determines the display position of the display pixel in the horizontal direction, and each time the count value NH increases by 1, the display position of the pixel moves to the right by 1 bit. And count value NH=0
When NH=0, pixels are displayed at the left end of the screen, when NH=255, pixels are displayed at the right end of the screen, and from NH=256 to 340 is a horizontal non-display period. Also, count value N)(,=34
A pulse is supplied to the vertical counter 8 every time it becomes 0. This vertical counter 8 determines the vertical position of the display pixel, that is, the number of the horizontal scanning line, and each time the count value NV increases by 1, the horizontal scanning line moves down by one line. When the count value N, V = 0, pixels are displayed at the top of the screen, and when N = 191, pixels are displayed at the bottom of the screen, and there is a vertical non-display period between VH = 192 and 2.61. .

Next, the image data processing circuit 9 is connected to the CPUI via the interface circuit 10 and to the VRAM 5, and transfers data supplied from the CPUI to the VRAM 5.
At the same time, the written data is read out according to CPU commands and various display controls are performed. That is, in the case of still image display, the still image pattern name, display position, and color code written in the still image control table 5b during the vertical non-display period are displayed immediately before display (8
Based on these, the dot data to be displayed is extracted from the still image pattern table 5& and set in the shift register in the image data processing circuit 9.
When the display position is reached, this shift register is shifted one bit at a time, and a color code corresponding to the output "127"0' is supplied to the color palette 11. Color palette 11 uses this color code as R (red), G (green), and B.
(blue) and converts it to each color data and converts it to DAC (digital/
It is displayed on the CRT display device 3 via the analog/4G converter) 12.

On the other hand, moving image display is performed by cooperative processing between the image data processing circuit 9 and the moving image processing circuit 13 .

That is, the image data processing circuit 9 sequentially sets the name, display position, color code, and EC bit of the moving image pattern Pi to be displayed in the next frame in the moving image control table ch during the vertical non-display period according to a command from the CPU 1. , in each horizontal scanning period, the X coordinate of this moving image control table Ck is sequentially checked to determine whether there is a moving image pattern to be displayed in the next horizontal scanning period, and the moving image control table C&i predetermined with the moving image pattern to be displayed is checked. Registered video control table ch in each horizontal non-display period.
At the same time, transfer the X coordinate of
Count value NV of vertical counter 8 and video control table C
& is intertwined with the X coordinate) and set it in the pattern shifter in the video processing circuit 13. In this way, the pattern thick and X counters in each moving image processing circuit 13 are sequentially set with one line of dot data of the moving image pattern to be displayed during the next horizontal scan and its display start position X. At the same time, the color code of each moving image barcoon is also transferred to each moving image processing circuit 13 from the fourth byte of the moving image control table ch. Then, the next horizontal scan is started, and each time the count value NH of the horizontal counter 7 increases by 1, the value of each X counter is decreased by 1, and when this value reaches 0, it is synchronized with the count up of the horizontal counter 7. Then, the pattern shifter sequentially outputs one pit at a time, and this is displayed on the CRT screen.

In this case, when the output is a "1" signal, a color code is supplied from the video processing circuit 13 to the color palette 12, and the corresponding color is sent to the CR via the DAC 12.
It is displayed on the T screen, and when the signal is "0", nothing is supplied, so the screen becomes the background color.

By the way, in the above-mentioned conventional device, if a part of the video pattern is hidden on the left side of the screen, the X of the display position (x, y) of this video pattern becomes negative, and the X counter value becomes negative. Even if you decrease the value by 1, it will not become 0,
It becomes impossible to specify the correct position. Therefore, in such a case, as shown in Fig. 5, the screen should be shifted to the left by a predetermined pixel m (for example, 1□1=32), and the X counter should start counting from the left end of this virtual screen. Otherwise, shift the position (x, y) to the position (X-m, Y),
As a result, the moving image was shifted to the left by m pixels and displayed. This is specified in the video control table Ck mentioned above.
This is the EC bit within. That is, when the EC bit is on, the start of down-counting of the X counter is advanced by m counts, and the above processing is performed. According to this method, although the above-mentioned inconvenience can be eliminated, the start of down-counting of the X counter must be advanced by the number of shifts m, so the data set to the X-counter and pattern shifter of the video processing circuit 13 is also set earlier than the start of down-counting of the X-counter. It must be completed by. Therefore, the time within the horizontal non-display period that can be used for the data set is reduced by this amount. For example, considering the case where a 16x16 pixel video is enlarged twice and displayed, the shift number m must be set to 42. In this case, the horizontal non-display period (this is the count value NH of the horizontal counter 7) 256-340 8 B1
About % or more of the time (between counts) is taken away for the shift. As a result, the number of data that can be set in the moving image processing circuit 13 is reduced, and the number of moving images that can be displayed on the horizontal scanning line is also reduced.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned concerns, and its object is to provide a display controller that can increase the number of moving image patterns that can be displayed on a horizontal scanning line.

[Features of the invention]

In order to achieve the above-mentioned object, when the EC bit is on (that is, when a shift to the left of the screen is requested), instead of accelerating the start of counting of the X counter, the shift is made at the start of horizontal display. an addition means for adding a number m to an X counter; a latch means for latching the value of the X counter immediately after the addition as a display start bit of a video pattern; and an output of the latch means is decoded to designate the display start bit. It is characterized by comprising a decoder and a shift register that sequentially outputs dot data of a moving image pattern from the bit specified by the output of the decoder, and displays the moving image pattern sequentially from the display start bit to the left edge of the screen. .

〔Example〕

Hereinafter, the present invention will be described in detail based on the drawings.

FIG. 6 is a block diagram showing the configuration of the image data processing circuit 9 (see FIG. 1). In the figure, bus CW (a pit) is a novus for writing data from the CPUI, and bus CR
(8 pits) is the bus for reading data from the CPUI, bus A
H (10 bits) and AL (8 pits) are VRAM5
bus for address specification, bus AH is the top 10 pits,
Bus AL specifies the lower 8 pits. Bus VW is VRA
Bus for writing data to M5, bus VRL is VRAM5
A bus C (lr is a bus for carrying a color code, and is connected to the color palette 11 shown in FIG. 1).

Next, the register group B1 consists of registers Bla-Ble that store the start addresses of each table type. and,
These registers B1a''B1e store the start addresses of the still image control table 5b, still image color table 5a, still image pattern table 5a, moving image control table 5e, and moving image pattern table 5d. It can be rewritten from the CPUI via the CW.

The color information register B2 stores two types of still image color codes read from the still image color table in the VRAM 5, and stores the "1"/" color code output from the pattern shifter B3.
One of them is selectively outputted by the 0'' signal and placed on the color bus C1r.The pattern shifter B3
is a shift register that converts the image data read from the VRAM 5 via the bus VRL into parallel to serial, and supplies its output "1"/"0" to the color information register B2 to determine the display color.

Next, the video number counter B4 counts each video control table C.
A 7-pit counter that stores the number k of & (video number) and the X-coordinate storage address in this table C& (in this example, the 0th byte; see Figure 3 (b)). Indicates video number k, and the lower 2 bits are Y, X,
When the video table 5e is searched to find the video to be displayed on the next horizontal scanning line, the video number k is incremented sequentially. ing. At this time, the lower two pits are always "0" and indicate only the X coordinate of the moving image table. This search is performed by checking the X coordinate of each frame control table channel during the display period and comparing this with the count value NV of the vertical counter 8. When a moving image to be displayed is detected, The contents of the video number counter B4 are registered in the video number FIFO B5. In this case, videos are registered in descending order of video number i (o to 31), and once eight videos are registered, no more videos will be accepted. In this way, during the horizontal display period, up to eight video numbers k to be displayed on the next horizontal scanning line are registered in the video number FIFO B5, and then these are sequentially read out during the horizontal non-display period to control the video. From table C&, video X coordinate, X coordinate, video pattern Pi
This is the address used to read out the name, color code, EC bit, etc. Then, the data read from each video control table ch is transferred to and set in a video processing circuit 20 (8 sets are provided), which will be described later, via the bus VRL. Note that the 9th moving image number that was not entered into the moving image FIFO B5 is registered in the register B6.

Next, the ALU (arithmetic unit) B7 compares the count value NV of the vertical counter 8 with the X coordinate, calculates the address of the video image data, etc., and sends the result of the operation to the decoder B9 via the status B8. supplied to Decoder B9 is a mode register.

Under the regulations of StarBIO, microprograms '□
It decodes instructions supplied from the ROM (hereinafter referred to as μ program ROM) B11 and controls the sequence of data to be loaded onto each bus. This μ program ROM
A horizontal counter 7 and a vertical counter 8 are connected to the BII, and specify the read address of the instruction.

Next, FIG. 7 is a block diagram showing the configuration of the moving image processing circuit 20. This moving image processing circuit 20 is provided in place of the conventional moving image processing circuit 13 shown in FIG. 9 and is also connected to a color palette 11 via a bus Car. Here, the bus VRL has eight lines VRLO to
Starting from VRL7, these lines VRLj (j=0
, 1...7) are connected to the data input terminal Di of each bit 21j of the 8-bit (256 base) It is connected to the data input terminal D1 of the VRL4 compatible device (not used) and each data input terminal D of each storage element 23-24j of the shift register 23.24.

Then, before the display of each horizontal scanning line is started, that is, during the horizontal non-display period, each bit 21j of the X counter 21 is
A load signal XL is applied to the load terminals I and D of the latch circuit 22, a signal CL is applied to the clock terminal CK of each latch element 22j of the latch circuit 22, and a signal CL is applied to the load terminal LDK signal of each storage element 23, jt, and 24j of the shift register 23, 24. I, L,
When RL is applied sequentially, the lines VRLO to VR
Each data is set via L7.

First, the X counter 21 is supplied with the value X (which, as described above, indicates the display start position of the video pattern) from the video control table ch, after being inverted by the inverter INV, and is supplied with an initial value NX.

It will be closed and set. In this case, the X counter 21 is 25
Since it is a hexadecimal counter, the initial value NX is as follows: NX0=255-X (1).

Next, the latch circuit 22 is supplied with the color code and the EC bit from the fourth byte of the video control table ch, and the color code is set in the latch elements 220 to 223 and gt is set in the latch element 227. .

Further, dot data to be displayed is supplied to the shift registers 23 and 24 from the moving picture pattern table 5d shown in FIG. 3(A) and set therein. Note that dot data is set in the shift register 24 only when the size of the moving image pattern is 16×16 pixels, and the load signal RL is applied only in this case.

In this way, before the start of horizontal display, the initial value NX is set in the X counter 21, the color code and EC bit in the latch circuit 22, and the dot data of the moving image pattern to be displayed in the shift registers 23 and 24.

Then, when horizontal display is started, parallel processing is performed in eight sets of moving image processing circuits 20, and moving image display is performed using the data set above.

First, in the video processing circuit 20 with the EC bit off, the X counters 21 start counting up all at once (this up counting is done in synchronization with the horizontal counter 7), and the display positions of the pixels are shown in FIG. When it comes to position (X, Y), start shifting the shift registers 23 and 24,
In other words, the input terminal C1 of each bit 21j of the X counter 21 of each moving image processing circuit 20 is connected to the carry output terminal CO of the previous bit, and the lowest bit (210) is used to display the dot data set in these. Input end Ci
is the SR set by the count start signal C8.
The Q output terminal of the flip 70 tube (hereinafter referred to as 5RFF) 25 and the carry output terminal Co of the most significant bit 217 are connected to the set terminal S of 5RFP 270 via an AND gate 26, and a count start signal C is applied at the start of horizontal display.
8 is set to 5RF)'25, the X counter 21 sequentially counts up starting from the initial value NX0 (=255-X) shown in equation (1). This up-counting is performed in synchronization with the up-counting of the horizontal counter 7, as described above, and when the pixel display position reaches X, the count value NX becomes 255. At this time, the outputs of all the pits 210 to 217 become "1", and the output of the AND gate 28 becomes "1", which is supplied to the shift controller 29 and shifts of the shift registers 23 and 24 are started.

On the other hand, in the moving image processing circuit 20 with the EC pit turned on, the value 32 is first added to the initial value NXo of the X counter 21 to update the initial value, and up-counting is performed from the updated initial value NXo.

As a result, the moving image pattern Pi is
It moves two pixels to the left and is displayed from the position (X-32°Y).

More specifically, between the carry output terminal co of the bit 214 of the X counter 21 and the input terminal Ci of the bit 215, an OR game) 301L is inserted;
The output of the analog game 30b is supplied to the other input terminal of 0a.

Ant game) 30b performs the logical product of the start signal Ho supplied at the start of horizontal display and the EC bit!
0, when the EC bit is on, a "1" signal is supplied to the input terminal ci of the pit 215 when the start signal Ha is supplied, and a value of 32 is added to the X counter 21. in this case,
Since the initial value NX of the X counter 21 was 255-X, the initial value NXo after addition of 32 is NXo=255-X+32 (21). Sometimes the initial value NXo is 2
If the value is 55 or less, the same processing as when the EC bit is off is performed.

When X≦31, the initial value NXo becomes 256 or more. Here, in the X counter 21, "256
” = “0”, NXo is: NXo = 256-X + 31 = 31-X −・・・−・+
81, so when the value X is 31 or less, NX0≧
It turns out that it becomes 0. This corresponds to a case where part of the video pattern is hidden on the left side of the screen, and bit 2 is
A “1” signal is output from the carry output terminal CO of No. 17,
The 5RFF 27 is set by the ``1'' output of the AND gate 30b, which is in an open state. When the 5RFF 27 is set, a ``1'' signal is supplied from the Q output terminal of the ``1'' output to the shift controller 29. , as will be described later, dot data is sent from the intermediate pits of the shift registers 23 and 24. Note that the above component 30
a, 30b and 215 constitute the adding means 30.

Next, the output of the lower 4 bits 210 to 213 of the X counter 21 is output to each pit 310 to 3 of the 4-pit selector 31.
The output of the lower 4 bits excluding the lowest pit 210 is supplied to the first input terminal D1 of the bit 310.
~313 second input terminal D2... This selector 31 switches the input data according to the signal MAG supplied to the select end SK of each pit 310 to 313. ”, and becomes “0” when not performed (normal display). And signal MA
When G is “0”, the lower 4 bits 2 of the X counter 21
When the outputs of 10 to 213 are "1", the outputs of the lower 4 bits 211 to 214 excluding the least significant bit 2101 are 4.
Each latch element 320 to 323 of the bit latch circuit 32
is supplied to the input end of

The latch circuit 32 latches data supplied from the selector 31 using a signal C8a supplied to its clock terminal CK. Signal C8a is 5RFF27
When the Q output of is "1" (that is, when the EC bit is on and X≦31), it is output from the shift controller 29 based on the count start signal C8. and,
When the count value NX of the X counter 21 increases by 1 from the initial value NX0 (=31-X) given by equation (3),
That is, when NX=32-X (4), the output data of the selector 31 is latched into the latch circuit 32.

Here, when the signal MAG is "0", the output of the selector 31 is the lower 4 bits of the count value NX (=52-X), and when the signal MAG is "1", this count value NX The value n set in the latch circuit 32 corresponds to the value X as shown in Table 1. And -tan latch circuit 3
The value n set to 2 is the next count start signal C.
8 is held until the reset signal C8b outputted from the shift controller 29 based on the reset signal C8b is applied to the reset terminal R of each of the latch elements 320 to 323.

As a result, the value n latched in the form of a binary code by the latch circuit 32 is converted into a hexadecimal code by the decoder 33, and n=0. 1. 2...15 signals FD, F1 . F2...F15 is the 7y gate An and AI from the decoder 33.

It is supplied to each first input terminal of A2...A15. on the other hand,
ANDGATE An, AI...A7. A8...A15
The storage elements 237, 236...230, 247...240 of the shift register 23.24 are connected to each second input terminal of the shift register 23.
Each output is supplied. In addition, each output of AND gate Table 1 AO to A7 is input to each input terminal of OR game) 34a,
Ant-game) Each output of A8 to A15 is or-game) 34b
The outputs of the OR gates 34a and 34b are supplied to the input terminal Di of the storage element 35 via the OR gate 34o.

As a result, the AND gate An opened corresponding to the above value n does not function as the dot data take-out gate, and the dot data stored in the shift registers 23 and 24 is transferred from the AND gate An to the OR gate 34a (34b). )→OR gate 34c→memory element 35, and is output from this memory element 35 as a serial signal PT. And this signal P
Latch elements 220 to 22 depending on "1'/"0' of T
The color code latched to 3 is turned on/off,
This is supplied to the color palette 11 shown in FIG. 1 via the color bus C11r, and displayed on the CRT display device 3 via the DAC 12.

The shift registers 23 and 24 have 8 pits or 16 pits.
It stores bit dot data, and when the dot data is 8 pixels (when the video pattern is 8 x 8 pixels)
In this case, the shift register 23 is used alone, and in the case of 16 pits (when the moving image pattern is 16×16 pixels), the shift register 23 and the shift register 24 connected thereto are used together.

As already mentioned, the load signal LL supplied from the shift controller 29 to the load terminal LD of each storage element 230 to 237 of the shift register 23 during the horizontal non-display period determines what should be displayed in the next horizontal display period. The dot data is set in the memory elements 230 to 237 (hereinafter, at this point, each memory element 240 to 247 of the register 24 is set to the memory elements 230 to 237).
, 8'-bit dot data to be displayed following the above dot data is set by the load signal RL supplied to each load terminal LD (hereinafter, the data set in the memory elements 240 to 247 at this point will be The dot data are called EO to E7). Then, when entering the horizontal display period,
These dot data DO-D7, EO-E7 are sequentially output from the take-out game (AIIL) while being controlled by the shift signal S and hold signal H supplied from the shift controller 29.

First, when the Q output of the 5RFF 27 is "0'", that is, when the entire moving image pattern is displayed on the screen, the value n latched by the latch circuit 32 is 0.
A signal FO is output from 3.

Therefore, if the computer (A) Atl is in an open state, this becomes the dot data extraction gate. Then, the X counter 21 counts X, and the count value NX becomes 255.
Then, from the AND gate 28 to the shift controller 2
9 is supplied with a "1" signal. This allows the signal MA
When G is "0", the shift signal S is output from the shift controller 29 in synchronization with the count of the horizontal counter 7, and when the signal MAG is "1", the shift signal S is output from the X counter 21.
The shift signal S/hold signal H is alternately outputted from the shift controller 29 in accordance with whether the count value NX is even/odd. As a result, when the signal MAG#rO'', the dot data D7, D6...Do
, (E7. EO...EO) are output in sequence, and these are displayed in order from position X above one horizontal scan, and the signal MAG
is "1", dot data D7. D7. D6°D6. ...Do, DO, (E
7. E7. EO, EO...EO, EO) are sequentially output and displayed.

Next, when the Q output of the 5RFF 27 is "1", that is, when a part of the moving image pattern is hidden on the left side of the screen, the value n (n≠0) is latched in the latch circuit 32, and a signal is sent from the decoder 33. Fn is output. Therefore, the AND gate An becomes open and serves as a gate for extracting dot data.

Then, every time the count value NX of the X counter 210 increases by 1, when the signal MAG is "0", the shift signal S is output from the shift controller 29, and the signal MAG becomes "1".
', the shift signal S/hold signal H is alternately sent to the shift controller 2 in accordance with the even/odd count value NX.
Output from 9.

As a result, when the signal MAG is "0", the antgame
) An outputs the dot data shown in Table 2 sequentially,
These are displayed in order from the left end of the screen. For example, when n=5, acid gate A5 is opened and dot data D2t Dl,D.

(E7...EO) are sequentially output and displayed from the left end of the screen. Furthermore, when the signal MA'G is "1'",
These dot data are displayed twice, and the video pattern is enlarged twice.

Next, the operation of the embodiment according to the above-described configuration will be explained.

According to this embodiment, up to eight moving image patterns can be displayed per Vc1 horizontal scanning line on a still image displayed on the CRT display device 3. In this case, video patterns with the lowest video number have a higher priority, and still images have a lower priority than videos. Therefore, the portion of the still image that overlaps with the moving image pattern is automatically deleted.

Hereinafter, after an overview of the method for displaying still images, the display of moving images, which is the main part of this embodiment, will be described in detail.

Prisoner Still image display.

Still images are displayed in the still image pattern table 5a with 8x
Still image patterns stored in 8-pixel units are read out in the specified order. This specification is made in the still image control table 5b, in which the names of still image patterns to be displayed are registered in the order of display. Then, the dot data of the still image pattern to be displayed is read out in the following procedure and set in the pattern shifter B3 in 1-byte units.

(2) The ALUB 7 performs a predetermined calculation on the count value NHSNV of the horizontal counter 7 and the vertical counter 8, and determines the read address of the still image control table 5b.

(2) Read the name of the still image pattern to be displayed next from the address.

(2) The ALUB 7 determines the read address of the still image pattern table 5a from the name and the count value NV.

(2) Read dot data (1 byte) from the address and transfer it to pattern shifter B3.

In this way, when 8 bits, that is, 8 pixels worth of dot data is set in pattern shifter B3, this dot pattern is shifted by 1 pixel, and the color code of color information register B2 is changed according to the "1"/"0". Selectively output. The color code is supplied to the color palette 11 shown in FIG. 1 via the Calanibus Cl1r, and the DAC
12 on the CRT display device 3.

■ Video display under normal conditions (when EC bit is off).

Display of a moving image is performed by assigning a display position to a moving image pattern Pi stored in units of 8×8 pixels or 16×16 pixels in the moving image pattern table 5d. Each video control table ch assigns this display position, and a video can be displayed by appropriately shifting the display position. Then, the dot data and display position of the moving image pattern to be displayed are determined in the following procedure and set in the moving image processing circuit 20.

■ First, the presence or absence of a moving image to be displayed on the next horizontal scanning line during the horizontal display period is detected. That is, the ALUB7 sequentially examines the video control table c'k according to the address specification of the video number counter B4, and successively compares each Y coordinate with the vertical count value NV to determine whether there is a video to be displayed. When there is a video to be displayed, the contents of the video number counter B4 at this time are stored as the video number FIFO-B.
Set to 5. In this way, the addresses of the video control table Ck that specify the video pattern Pi to be displayed in the next horizontal scanning line are set in the video number FIFO B5, until eight addresses are set, or the last video control This process is completed when the investigation up to table C31 is completed.

■ In the next horizontal non-display period, the video number FIFO-
The video control table Ck registered in 85 is sequentially stored in VRAM.
The data in each table channel and the dot data of the moving image pattern Pi to be displayed are sequentially set in eight sets of moving image processing circuits 20. That is, the X coordinate (hereinafter referred to as value X) of the video control table ch is inverted,
Initial value NX, (=
255-X) and the busy, color code and EC bits are set in the latch circuit 22.

Also, from the name of the video pattern Pi of the video control table Ck and the vertical count value NV, the video pattern table 5&
The read L7 address is determined (this operation is performed in ALUB7), and the dot data DO~])7 read from this address, Eo~E7 are stored in the shift register 23.2.
Each is set to 4.

However, dot day) EO to E7 are shift registers 24
The video pattern p (16X'1t) is set to
5 pixels, that is, only when the signal 5IZp (FIG. 7) is "1". Thus, the processing of the horizontal non-display period is completed.

(2) At the time of entering horizontal display, a start signal HO% count start signal C8 is supplied, and while 5RFF25 is set, 5RFF27 is reset. Due to this busy state, the output Q of the 5RPF 27 becomes "O1", and the reset signal C8b is output from the shift controller 29.
Each of the latch elements 320 to 323 of the latch circuit 32 is reset, and its output value becomes n=o.

Therefore, the output FO of the decoder 33 becomes "1", the gate (An) is opened, and the output S of the storage element 237 of the shift register 23 is opened.
O is supplied to the storage element 35 via the AND gate AO→OR gate 34a→OR gate 34o.

On the other hand, 5RFP25 is activated by count start signal C8.
When is set, the X counter 21 starts counting up. In this case, the initial value NX0 of the X counter 21 is 255-X, so if you count up the value X,
The count value NX of the counter 21 becomes 255, and the output of the AND gate 28 becomes "1".

As a result, the shift signal S is output from the shift controller 29, each bit of the shift registers 23 and 24 and the storage element 35 is shifted, and the dot data D7. D
6. Do, (E7E6...EO) are sequentially output from the storage element 35 as a serial signal PT. This signal PT turns on/off the color code latched by the latch circuit 22 via a priority circuit (not shown) (which erases the above-mentioned low-priority images), and this color code Color palette 11 via C1r
and pixels of a predetermined color are displayed. In this way, the moving image pattern Pi is displayed from the specified position (x, y) as shown in FIG. It will be displayed.

(Video display when CIEC bit is on and value X is 32 or higher.

In this case, data is set to each moving image processing circuit 20 in the same manner as in (2) and (2) above.

When the start signal HO is supplied at the start of horizontal display,
Since the EC pit is "1", the output of the AND gate 30b is "1". With this, or game) 301
The initial value NX0 (=255
-X) "32" is added. By the way, in this case
Since ≧32, the addition result does not exceed 256, and the initial value NXO of the X counter 21 only increases by "32" tb, after which the process returns to the above-mentioned 0 term. and,
The display of the moving image pattern Pi is performed from the position (X-52, Y), which is shifted leftward by 32 pixels from the position (X, Y). In this case, since the count of the X counter 21 is started at the start of horizontal display, the conventional disadvantage of having to start counting of the X counter a predetermined number of elements (for example, 32 pixels) before the start of horizontal display is eliminated. It can be resolved.

(c) Video display when the EC bit is on and the value X is 31 or less.

In this case as well, data is set to each moving image processing circuit 20 in the same manner as (2) (2) and (2) above.

Now, when the start signal HO is supplied at the start of horizontal display, the value "32" is added to the initial value NX0 (=255-X) of the X counter 21 in the same way as in the case of the 0 term. However, since X≦31 this time, the addition result exceeds 256 and the carry signal Cr is output from the highest pit 217, and the initial value NX is changed to the value 31-X given by equation (3). Ru. Furthermore, the 5RFF27 is set by this carry signal Cr, and the output Q is "3".
1" signal, signal C8 from shift controller 29
& is output. As a result, the latch circuit 32 has the value
The value n shown in Table 1 is set corresponding to
3 outputs a "1" signal Fn to open the analog gate (An), and this state is maintained during the horizontal display period.

In this way, when the dot data extraction gate An is determined, the shift controller 29 sends the data to each shift register 23 .
24 and a storage element 35/, a shift signal S is supplied,
The dot data shown in Table 2 is sequentially outputted from the OR gate 34a (takeout gate A!1).
When it is A8 to A15, it is supplied to the storage element 35 via 34b) and 34c, and this is output as a serial signal PT. In addition, dot data EO to E7 are 16X16
Used only when displaying a video pattern of pixels. Table 2 shows the display state when the signal MAG is "0", and when the signal MAG is "1", each dot data DO to D7 and EO to E7 is displayed twice in succession. Ru. As described above, this control is performed by the shift controller 29 alternately outputting the shift signal S/hold signal H.

In this way, according to this embodiment, when the EC bit is on, the initial value NX of the X counter 21 is changed by addition at the start of horizontal display, so there is no need to advance the counting start time of the X counter as in the conventional case. . Therefore, the time available for data sets during the horizontal non-display period is extended, and - the number of moving image patterns that can be displayed on a horizontal scan line is reduced from the conventional 1.
The number of patterns can be increased approximately five times (for example, from 5 patterns to 8 patterns).

〔Effect of the invention〕

As explained above, the present invention adds a predetermined value (for example, 32) to the X counter at the start of horizontal display to change its initial value when the control bit (EC bit) is on. Since the moving image pattern is shifted to the left side of the screen, it is not necessary to start counting the X counter within the horizontal non-display period as in the conventional case. As a result, the number of moving image patterns that can be set within the horizontal non-display period increases, thereby providing the advantage that it becomes possible to increase the number of moving images that can be displayed on the horizontal scanning line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a conventional display device, FIG. 2 is a memory map showing the contents of a VRAM 5 shown in FIG. 1, and FIG. 3 is a block diagram (Gf). 4 is a conceptual diagram showing an example of the storage contents of the video pattern table 5d shown in FIG. 2, FIG.
The figure is a conceptual diagram showing the display position (x, y) of the moving image pattern Pi, FIG. 5 is a conceptual diagram illustrating the screen shift when specifying the EC bit, and FIG. FIG. 7 is a block diagram showing the structure of the moving image processing circuit 20 according to the same embodiment. 21...X counter (counter), 23, 24...
...shift register, 30...addition circuit (addition means), 32...latch circuit (latch means),
33...Decoder, EC...EC bit (
specific bit). Applicant ASCII Co., Ltd.

Claims (1)

[Claims] - Equipped with a counter that specifies the display start position in the horizontal direction of the video pattern, and when a specific pit set during programming is on, the count of the counter is advanced by a predetermined pit amount from the start of horizontal scanning, and the pattern is In a display controller configured to display a moving image pattern in which a portion is hidden at the left end of the screen, if the specific bit is on, the predetermined number of pits is set to the counter at the start of horizontal scanning, instead of accelerating the counting start of the counter. a latch means for latching the value of the counter immediately after the addition as a display start bit of the moving image pattern, a decoder for decoding the output of the latch means and specifying the display start bit; a shift register that sequentially outputs dot data of the moving image pattern from the bit specified by the output of the display controller, and displays the moving image pattern sequentially from the display start bit to the left end of the screen. -La.