KR910006476Y1 - Rgb signal selecting circuit - Google Patents

Abstract

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Description

RGB signal selection circuit

1 is a circuit diagram of the present invention.

Figure 2 is an illustration of color selection and removal according to the present invention.

* Explanation of symbols for main parts of the drawings

10: 8 bit latch 20: 4 bit latch

30: Address Decode Logic BUF1-BUF4: 3 status buffer

MUX1-MUX4: Multiplexer

The present invention relates to the selection of color signals in a monitor screen display circuit, in particular red (Red: R), green (hereinafter referred to as G), and blue input to a cathode raytube (CRT). (Blue: referred to as B) and I (Intensity: referred to as I) The present invention relates to an interchange circuit of RGB signals that enables color replacement of the entire screen through interchange and removal of signals.

Figures and characters that appear on a CRT screen are composed of a number of pixels (PIXEL) .They display information on the screen, that is, shapes and colors, stored in the video memory for every pixel. shall.

At this time, the CRT controller reads the information stored in the video memory, separates the information into RGB and I signals, and hands them over to the CRT. The CRT configures a screen based on the signals.

Therefore, when the screen is configured as described above, the color of the monitor screen can be selected by combining RGB and I signals for the color desired to be displayed on the screen by the color video board and displaying 16 colors.

At this time, if you want to change the color of the screen to any other color in the prior art had to change the color data stored in the video memory.

For example, in order to convert the red parts of the screen to green, it was necessary to delete the existing red information stored in the video memory and exchange the green color information.

Therefore, not only the program hassles due to memory information exchange due to the color of the screen, but the contents of the video memory have to be replaced and recorded so that the time required is long.

Accordingly, an object of the present invention is to provide an RGB signal selection circuit that can easily replace the entire color displayed on the screen by exchanging or removing the RGB and I signals input to the CRT.

Hereinafter, with reference to the accompanying drawings of the present invention.

FIG. 1 is a circuit diagram of the present invention, and includes a first to fourth multiplexer (MUX1-MUX4) for inputting R, G, B, and I signals from a video board output terminal to selectively output one of the four signals according to a state of a predetermined control signal. 8-bit RGBI position array determination signal (D0-) from the data bus, using a signal selection means (100) composed of the < RTI ID = 0.0 > and input / output < / RTI > A first latch means (10) for latching D7) to control the respective selection stages S10, S11, S20, S21, S30, S31, S40, S41 of the first-fourth multiplexer MUX1-MUX4. And first to fourth tri-state buffers BUF1 to BUF4 buffering and outputting the first to fourth color signals output from the signal selecting means 100 under the control of the output control means 20 described below. An output control signal of 4 bits from the data bus according to the output means 300 and the state of the I / O WRITE signal operating as a clock signal. 4-bit latch 20 to latch arcs D0-D4 and address decode logic to control the enable terminals of the 8-bit latch 10 and 4-bit latch 20 by decoding arbitrary input / output addresses. It consists of 30.

2 is an example of the color selection and removal according to the present invention, 2a) is an example of the screen state before the color signal exchange, 2b) is a state of the screen after the R → B color signal exchange in (2a), 2c) is (2a) This is the state diagram when B signal is removed from.

Based on the above-described configuration will be described an embodiment of the present invention in detail.

When the RGB signal connected to the output terminal of the existing video board is input to the first-fourth multiplexer (MUX1-MUX4), each of the multiplexers is one of the input R, G, B, and I signals according to the input state of the selection signal. Select to print.

At this time, the selection signal takes 2 bits each from the 8-bit latch 10 output, and the 8-bit latch 10 is enabled under the control of the address decode 30.

That is, it latches and writes 8-bit RGBI position array determination signal (D0-D7) from the data bus according to the state of I / O writer signal generated from microcomputer and operating as clock signal. The color selection of the first to fourth multiplexers MUX1 to MUX4 is changed according to the bit latch 10 output state, so that the RGBI array can be arbitrarily changed.

In addition, the multiplexer outputs are input to the first to fourth tri-state buffers BUF1 to BUF4, and the respective buffers BUF10BUF4 are controlled by the 4-bit latch 20 to determine whether to monitor the buffering signal. do.

At this time, the 4-bit latch 20 latches data of the upper 4 bits from the data bus into the output control signals D0-D3 in the same manner as the 8-bit latch.

Therefore, when the above-described RGBI selection and removal will be described with reference to specific embodiments as shown in FIG. 2, first, the arrangement position change through interchange of RGB signals during color selection is as follows.

That is, assuming that the screen state before the change is the same as that of FIG. 2 (2a), and the state where the B signal and the R signal are exchanged is the same as (2b), the first multiplexer MUX1 returns the R signal before signal exchange. Since the second multiplexer MUX2 should select the G signal, the third multiplexer MUX3 should select the B signal, and the fourth multiplexer MUX4 should select the I signal, the first multiplexer MUX1. The select signals S10 and S11 are "0", the select signals S20 and S21 of the second multiplexer MUX2 are "1", and the select signals S30 and S3 of the third multiplexer MUX3. S31 is "10", and the selection signals S40 and S41 of the fourth multiplexer MUX4 should be "11".

However, in order to exchange the R and G signals, the first multiplexer MUX1 needs to select the G signal, so that the states of the selection signals S10 and S11 must also be changed to "1", and the second multiplexer MUX2. Since the R signal must be selected, the selection signal (S20, S21) state must also be changed to " 0 ".

However, since the third and fourth multiplexers MUX3MUX4 have no change in the color signal previously selected, the state of the selection signals S30, S31 and S40, S41 also remains unchanged.

Therefore, data of "1001011" should be recorded in the 8-bit latch 10.

This decodes any I / O address assigned for an 8-bit latch to enable the 8-bit latch 10 and allow data carried on the data bus to be written by an I / O write signal. do.

In the above operation, the programmer simply needs to control to send data of "1001011" to the address allocated to the 8-bit latch 10 in one output command.

In addition, when the color signal output to each of the multiplexer to turn on (ON) or off (OFF) to operate as follows.

For example, assuming that the screen state before the R signal is off as shown in (2a), the screen state diagram in which the R signal is shorted (off) is as shown in (2c).

Therefore, the control input of the tri-state buffers BUF1 to BUF4 buffering and outputting the R signal should be "1" when the R signal is on and "0" off.

Therefore, in order to change the contents of the 4-bit latch 20 that becomes the control input signal of the three-state buffer, the same as in the contents change of the 8-bit latch.

That is, when all signals are being output, all three-state buffers BUF1-BUF4 should be turned on. Therefore, the contents of the 4-bit latch should be set to "0". If you change to 1 ", the corresponding signal output can be turned off.

By implementing the selection and removal of the RGB signal as described above, there is an advantage that the function improvement can be avoided by simplifying the control program and shortening the use time.

Claims (1)

In the RGB signal selection and interchange circuit of the image processing system, the R, G, B, and I signals are input from the video board output terminal to the first to fourth selectors for selectively outputting one of the four signals according to the state of a predetermined control signal. By using the configured signal selection means 100 and the input / output write signal output from the microcomputer as a clock signal, the first and second selectors are controlled by latching the RGBI positioning signal D0-D7 from the data bus. Output means 300 comprising a first latch means 10 and the first to fourth buffer portion BUF1-BUF4 output from the signal selection means 100 under the control of the following output control means 20. And second latch means 20 for latching an output control signal D0-D3 from the data bus in accordance with the state of the input / output write signal operating as a clock signal, and decoding an arbitrary input / output address. Control the first latch means 10 and the second latch means 20; Circuit comprising: an address decode logic (30).