JPS60211699A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve read/write characteristics of an EPROM by impressing a grounding potential and a substrate backup bias voltage in accordance with selection and non-selection of a floating gate/avalache injection MOSFET(FAMOS) of an element forming area. CONSTITUTION:When FAMOSQ11-Q1n of an element forming area of a memory array M-ARY are selected through, for instance, a word line WL1, etc., an FETQ2 of a switch circuit S1 is turned on, and a substrate back bias voltage is supplied to the element forming area from a substrate back bias voltage generator circuit VBB-G. Conversely, when they are not selected, an FETQ1 is turned on, and a grounding voltage is supplied, whereby relative threshold voltages of the FAMOSQ11-Q1n change in accordance with the selection and non-selection. Consequently, a conductance characteristic of the FAMOS where writing is carried out at the time of writing becomes larger, and most parts of a write current blow, which causes a leak current to the non-selected FAMOS to be reduced. This can apply reading, and write/read characteristics of an EPROM can be improved.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and includes, for example, a MOSFET (insulated gate field effect transistor) and a FAMO3 (floating gate field effect transistor).
EPROM whose memory element (memory cell) is a semiconductor element such as avalanche injection MO3FET
(Electrically Programmable Read-Only Memory)

[Background technology]

EPROM devices using semiconductor elements such as FAMO3 (floating gate avalanche injection MO3FET) as storage elements (memory cells) are known (see Japanese Patent Laid-Open No. 152933/1983).

FAMO3) When writing to the transistor, the word line is unselected and the data line is selected.
The voltage VFG of the floating gate in the AMO3 transistor is expressed by the following equation (1) due to capacitive coupling with the drain when there is no charge on the floating gate.

VFG=VD -C3/CT...-Ill Here, VD is the drain voltage, C3 is the capacitance between the floating gate and the drain, and CT is the capacitance C1 between the semiconductor substrate and the floating gate and the floating This is the sum of the capacitances C2 and 03 between the gate and the control gate.

At this time, the voltage VFG is larger than the threshold voltage vth of the FAMO3I-transistor (if this happens, a channel will be formed. As a result, a so-called non-selective leakage current will flow. As a result, the selected FAMO3)
The write current supplied to the transistor decreases, resulting in a decrease in write efficiency. As a countermeasure for this, F.
It is conceivable to set the threshold voltage vth of the AMO3) transistor so that it is always higher than the above voltage VFG, but since the channel current of the selected transistor decreases, in other words, its conductance characteristics become small. As the drain current increases, the drain current decreases, resulting in a decrease in write efficiency.

It is also possible to reduce the impurity concentration of the drain region of the transistor 1"AMO3) to reduce the capacitance value of the capacitor C3, but in this case, the drain expansion
Since the resistance value becomes large, the read speed becomes slow as a result.

E F using FAMO3) transistors as above
Since ROM has contradictory operating characteristics in the selected state and non-selected state or in the write operation and read operation, it is difficult to set the different characteristics, and it is difficult to prevent variations in the element characteristics. be affected.

[Purpose of the invention]

An object of the present invention is to provide an EP ROM device with improved write/read characteristics.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the FAMOS3) transistor is configured by dividing it into electrically isolated element formation regions, and the FAMOS transistor formed in the element formation region controls the substrate bank bias voltage when it is in a non-selected state, and controls the circuit voltage when it is in a selected state. It supplies ground potential.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of an EPROM device according to the present invention. The concave path element shown in the figure is formed on a semiconductor substrate such as, but not limited to, single crystal silicon using a known MO3 semiconductor integrated circuit manufacturing technique. Although not particularly limited, this embodiment circuit will be described using an example in which an N-channel MO3FET is used.

In this embodiment of the EPROM device, a complementary address signal processed and formed is inputted to address decoders X-DCR and Y-DCR through an address buff 1 which receives an address signal supplied from an external terminal (not shown).

Address decoder X-DCR outputs word lines W1 to Wm of memory array M-ARY according to the complementary address signal.
form a selection signal.

Address decoder Y-DCR outputs data lines D1 to Dn of memory array M-ARY according to its complementary address signal.
form a selection signal.

The memory array M-ARY is composed of a plurality of FAMO3I-transistors (non-volatile memory elements: MO3FETQI 1 to Qm n ) shown as a representative, word lines W1 to Wm, and data lines D1 to Dn. ing.

In the memory array M-ARY, FAMO3) transistors Qll to Q1 n (Q2
1~Q2 n, Q31~Q3 n and Qm1~Q m
The control gates of the word lines Wl (W2, W3 and W m ) are respectively connected to the corresponding word lines Wl (W2, W3 and W m ). Also, the FAMOS transistor Q placed in the same column
l 1~Qml (Q21~Q2n.

The drains of Q31-Q3n and Qln-Qmn) are connected to the corresponding data lines DI (D2, D3 and Dn), respectively.
It is connected to the.

Then, each of the above FAMO3) transistors Qll to Qm
The n common source line CS is connected to the ground potential Vss of the circuit.

Each of the data lines DI-Dn is connected to a common data line CD via column selection switches MO3FETQ3 to Q6.
It is connected to the. The common data line CD is connected at one end to the output terminal of the data input circuit DIB, and at the other end to the input terminal of the data output circuit DOB. Note that the data input circuit DIB has an external terminal I1.
0, and a write circuit that transmits the write signal raised to a high level by the output signal of the input buffer circuit to the common data line CD. Further, the data output circuit DOB is constituted by a sense amplifier that amplifies the signal read out to the common data line CD, and an output buffer circuit that receives the output signal and sends out the read signal from the external terminal I10. Ru.

Note that when reading the stored information of the FAMO5l-transistor, the address decoder X-DCR.

Although not particularly limited, a bias voltage is applied to the FAMO3) transistor selected by the Y-D CR by a sense amplifier having a level limiter function. The selected FAMO5) transistor has a threshold voltage equal to or lower than the word line selection level according to the write data.

When the selected FAMO3) transistor is turned off regardless of the word line selection level, the common data line CD is set to a relatively high level by the sense amplifier. On the other hand, when the selected FAMO3) transistor is turned on by the word line selection level, the common data line CD is set to a relatively low level. If the high level and low level of such common data line CD are limited by the limiter function provided in the sense amplifier, even though there is capacitance such as stray capacitance on this common data line CD etc. that limits the signal change speed. First, reading speed can be increased.

In other words, when reading out stored information from multiple FAMOS transistors one after another, the common data line C
The time required for one level of D to change to the other level can be shortened.

Although not shown, a control circuit is provided in addition to the above circuit. This control circuit includes an external terminal CE (not shown),
Various internal control signals necessary for write/read operations are formed according to the chip enable signal, output enable signal, program signal, and write high voltage supplied to OE, PGM, and VpH.

In this embodiment, the following circuits are added in order to improve the write/read characteristics. Furthermore, although not particularly limited, the FAM in the memory array M-ARY may be
O3) Of the transistors, FAMO3) Randisk Q1
1 to Q1n are formed in separate well regions for each group of FAMOS transistors arranged in the same row (word line Wl). That is, the above word i*w
FAMO3 transistors Qll-Qln, whose control gates are connected to i, are formed in a well region WLI shown by a dashed line in the figure. Other rows (word line W2~
FAMO3) transistors Q21~Q2n, Q31~Q3n and Qml~Q respectively arranged in Wm)
mn are also respectively formed in the well regions WL2 to WLm similar to the above. Although not particularly limited, the above FAMO3
) When N-channel MO3FETs are used as transistors, the well regions WL1 to WLm are P-type well regions formed on an N-type semiconductor substrate.

Each of these well regions WL1 to WLm is connected to the circuit ground potential Vss through the next switch circuits 31 to Sm and, although not particularly limited, to a substrate bank bias formed by a substrate bank bias generation circuit VBBG, which will be described later. A voltage -veB is selectively supplied.

The switch circuit, as shown in one switch circuit S1 as a representative, changes the ground potential Vss of the circuit to the well region W by the ON state of MO3FETQI.
LI, and the substrate bath bias voltage VBB is applied to the well region WLI by the ON state of MO3FETQ2.
It is intended to supply A signal from the word line W1 is supplied to the gate of the MO3FETQI, and the MO3FETQ
The gate of No. 2 is supplied with the signal of the word line W1 inverted by the impark circuit IVI. As a result, if the word line W1 is in the selected state of high level, the MOS
When FETQ1 is turned on and the circuit ground potential Vss is supplied to the well region WLI, and the word line W1 is at a low level in a non-selected state, MO5FETQ2 is turned on and the substrate hack bias voltage -VB is supplied to the well region WLI.
When the word line W1 is selected, the inverted signal of the low level (circuit ground potential Vss) is supplied to the gate of MO3FETQ2, and the substrate back Bias voltage VSa
However, by setting its threshold voltage vth relatively large, it is turned off.

Although the substrate bank bias voltage -vBB is not particularly limited, the built-in substrate bank bias voltage generation circuit V
Formed by Be-G.

By providing the above switch circuits 31 to Sm for each word line, in write/read operations, the ground potential Vss of the circuit is supplied to the well region belonging to the word line in the selected state, and the ground potential Vss is supplied to the well region belonging to the word line in the non-selected state. A substrate bank bias voltage -VaS is supplied to the well region belonging to .

FIG. 2 shows a circuit diagram of a switch circuit according to another embodiment of the present invention.

In this embodiment, although not shown, the memory array M-AR
FAMO3 in Y) If the well region in which transistors are formed is also separated in the direction of a plurality of data lines, a switch circuit @S as shown in the figure is used. That is, the gates of the drive MO3FETs QO1 and QO2 are supplied with signals from the data lines Di and D2 formed in their well regions, respectively. This 9 MO3FETQ01. The commonly connected drain of QO2 has a depletion type MO
3FETQO3 is provided as a load, and NOR
A gate circuit is configured. The output signal of this NOR gate circuit is supplied to the gate of a driving MO3FETQO7 forming a NAND gate circuit through an inverter circuit formed of a driving MO3FETQO4 and a depletion type load MO3FETQO5. This drive M
O3FETQO7 has MO3FETQ driven in series.
O6 is provided, and the signal of word line W1 is supplied to its gate. A depletion type load MO3FETQO8 is connected to the drain of the MO3FETQO7.
is provided, and a control signal for MO3FET'Q2 that supplies the substrate back bias voltage -vBB to its well region WL is output from the drains of MO3FE and TQO7. Also, a MOS transistor that supplies the ground potential Vss of the circuit to the well region WL via the inverter circuit IVI
A control signal for FETQl is output. By doing this, the ground potential Vss of the circuit is supplied to the well region WL only when the word line and any data line are in the selected state. This allows selection of the FAMO3) transistor formed in that well region.
The non-selection is identified and the substrate bias voltage is switched and supplied in the same manner as above. In this way, the FAMO3I-transistors that make up the memory array M-ARY can be divided in various combinations, and their selection/non-selection can be identified by the combination of the word line and data line signals. It's a spider.

〔effect〕

(In the ll write operation, the selected FAMO3I-
The circuit ground potential is supplied to the element formation region to which the transistor belongs to make its threshold voltage relatively small, and the substrate bank bias voltage is supplied to the element formation region to which the unselected FAMOS transistor belongs. This makes the threshold voltage relatively large. This causes the FAMO3 to be written into the selected state.
) The conductance characteristics of the transistor are increased to make it easier for the channel current to flow, and the FAMO in the non-selected state is
The occurrence of leakage current flowing through the 3I transistor can be prevented or significantly reduced. Therefore, since most of the write current can be supplied to the FAMO3l- transistor to which the write is to be performed, it is possible to achieve the effect that write efficiency can be improved. In other words, by preventing or significantly reducing the leakage current generated in the FAMO3 transistor in the non-selected state, the write current that can be supplied to the FAMO3 transistor in the selected state can be set with high accuracy, realizing a high-speed and reliable write operation. Become what you can.

(2) In the read operation, high-speed read can be achieved by increasing the conductance characteristics of the transistor (FAMO3 in the selected state according to 11) and reducing the parasitic capacitance in the FAMOS transistor in the non-selected state. Effects can be obtained. In other words, the junction capacitance between the drain and the substrate (element formation region) of the unselected FAMO3) transistor connected to the selected data line can be reduced by supplying the substrate back bias voltage, so the read signal appears. This is because the capacitance value of parasitic capacitance in the data line can be reduced.

(3) If the FAMOS transistor is divided into word line units and each is formed in an electrically isolated element formation region, and selective noise pressure is supplied as in (1) above, Since the word line selection signal can be used as is for switching the bias voltage, it is possible to improve the write and read characteristics by adding a simple circuit.

(4) When the FAM9S transistor is divided into word line units and each is formed in an electrically isolated element formation region, one word line is selected among the m FAMO3) transistors. Since the substrate back bias voltage is supplied to all remaining FAMOS transistors for each FAMO3) transistor, during write operations, leakage current in all unselected FAMOS transistors can be prevented or significantly reduced. In the read operation, the capacitance value of the parasitic capacitance of the FAMO3I-transistors in the all unselected state can be minimized, so that the most efficient write operation and high-speed read operation can be achieved.

(5) Since the bias voltage to the element formation region is switched and supplied by circuit means, the effect of (4) can be achieved without adding any special manufacturing process and without adding 11 above. Effects can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the element formation region may be electrically isolated by being formed on an insulating substrate such as a sapphire substrate. Furthermore, instead of N channel MO'5FET, P channel MO
In addition to those using 3FET, peripheral circuits are N-channel M
It may be configured by a CMO3 circuit configured by combining an O3FET and a P-channel MO3FET. Furthermore, the substrate bank bias voltage may be supplied from an external terminal.

Further, the specific circuits of the peripheral circuits for communication such as the write circuit and the read circuit can take various embodiments.

[Application field]

The present invention can be widely used not only in EPROM devices that store information by selectively injecting charges into floating gates, but also in various semiconductor integrated circuit devices such as microcomputers incorporating such EPROMs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of an EPROM device according to the invention, and FIG. 2 is a circuit diagram of a switch circuit showing another embodiment of the invention. X-DCR, Y-DCR...7 dress decoder, M-A
RY...Memory array, DIB...Data input circuit, D
OB...data output circuit, 81~8m...switch circuit, VBBG...substrate back bias voltage generation circuit

Claims (1)

[Claims] 1. Non-volatile semiconductor memory elements having a control gate and a floating gate and storing information by taking charge into the floating gate are arranged in a matrix and connected to a cell or a plurality of word lines. a memory array having a plurality of element formation regions configured to electrically isolate a storage element group connected to one or more other word lines from one another; The EFROM is characterized in that it includes a voltage switching circuit that switches and transmits a substrate bank bias voltage when a memory element configured therein is in a non-selected state and a circuit ground potential when it is in a selected state. Semiconductor integrated circuit device. . 2. The semiconductor integrated circuit device according to claim 1, wherein the substrate bank bias voltage is generated by a built-in substrate bank bias voltage generation circuit. 3. The element formation region is formed so as to be electrically isolated in units of word lines, and the selection/non-selection identification signal is a selection signal of the word line. A semiconductor integrated circuit device according to claim 1 or 2. 4. A plurality of data lines are arranged in the same element formation area, and the selection/non-selection is determined by the selection signal of the word line and the selection signal of the data line configured in the element formation area. A semiconductor integrated circuit device according to claim 1, 2 or 3, characterized in that the semiconductor integrated circuit device is carried out by: 5. The element isolation region is a well region of a second conductivity type formed on a semiconductor substrate of a first conductivity type. The semiconductor integrated circuit device according to the second, third or fourth item. 6o The semiconductor integrated circuit device according to claim 1, wherein the element isolation regions are semiconductor regions respectively formed on an insulating substrate.