JPS62275394A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve a working margin and to increase the reading speed with a semiconductor storage device by providing a differential sense amplifier circuit which amplifies the read signal of a memory cell to a complementary common data line to which the memory cell is selectively connected. CONSTITUTION:The input terminal of a differential sense amplifier circuit SA0 and the output terminal of a data input buffer DIB are connected to the complementary common data lines CD0 and the inverse of CD0 respectively. Furthermore, these input and output terminals are connected to the drains of load MOSFETs Q15 and Q16 via limiter MOSFET Q151 and Q161 respectively. The fixed positive bias voltage Vb is applied to the gates of both MOSFETs Q151 and Q161. Then both FETs Q15 and Q17 function as resistance elements having the prescribed conductances when their gates are connected to the earth potential of the circuit SA0. Therefore, the drain voltages of the FETs Q15 and Q16, i.e., the input voltage of the sense amplifier circuit SA vary in response to the read current.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention relates to a semiconductor memory device, for example, a semiconductor memory device that uses FAMOS (Floating Gate Avalanche Injection/MOS) as a memory element. EPR
It relates to technology that is effective for use in OM (Erasable & Programmable Read Only Memory).

[Conventional technology]

For EPROMs using non-volatile semiconductor memory elements such as FAMOS transistors, for example
It is publicly known from Publication No. 152933 and the like.

The FAMOS transistor has a logic "1" in its normal state when no writing is performed, and has a threshold voltage lower than the selection level of the word line to which its gate is coupled. Further, the written state is set to logic "O", and the gate has a threshold voltage higher than the selection level of the word line to which it is connected. F like this
In a semiconductor memory device that uses an AMOS transistor as a memory element, the memory cell is usually one FAMO5l-
Consists of transistors.

[Problem that the invention seeks to solve]

Figure 3 shows the EFR developed earlier by the present inventors.
A readout circuit including an OM sense amplifier circuit is shown. In this EFROM, the memory cell is one F
AMO5) A memory cell Q1 constituted by a transistor Q1 and to be read is selected by a word line W1 and an MO3FET Q6 of a Y gate YG, and is coupled to a complementary common data line CD. The memory cell Q1 has an iAM
Complementary common data 'MACD and M from O5FETQ15
A read current is supplied via O3FET QI 51.

When the threshold voltage of memory cell Ql is made lower than the word line selection level by storing logic "1° information," the FAMOS transistor of memory cell Q1 is turned on, a read current flows, and the sense amplifier The input voltage Vs of the circuit SA is a relatively low voltage.On the other hand, when the threshold voltage of the memory cell Q1 is made higher than the word line selection level by storing logic "01 information," The FAMO3) transistor remains in the off state, almost no read current flows, and the input voltage Vs of the sense amplifier circuit SA becomes a relatively high voltage.

The inventors of the present invention have discovered that such an E F ROM has the following problems. That is,
As the storage capacity of semiconductor memory devices increases, circuit elements become increasingly finer, and the difference between the higher and lower threshold voltages of Randisk, the so-called Δvth, becomes smaller. At the same time, the value of the read current that can be passed through the FAMO3 transistor is becoming smaller. This reduces the read margin and prevents speeding up of the read operation.

An object of the present invention is to provide a semiconductor memory device with improved read margin and faster read operations.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
A memory cell is constituted by two non-volatile storage elements which are made to have a threshold voltage complementary to a selected level of a word line according to stored information, and each memory cell is A differential sense amplifier circuit is provided on a complementary common data line selectively coupled via a column system selection circuit to amplify a memory cell read signal transmitted via this complementary common data line. be.

[For production]

According to the above-mentioned means, the stored information is stored in a complementary manner by two non-volatile storage elements, and the read signal is amplified by a highly sensitive differential sense amplifier circuit, so the read current can be increased. , it is possible to realize a semiconductor memory device with improved operating margin and faster read operation.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of an EFROM to which the present invention is applied. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known CMO5 integrated circuit manufacturing techniques.

In the same figure, the MOS FET with an arrow added to the channel (back gate) part is a P-channel type.
It is distinguished from the N-channel MO3FET, which is not marked with an arrow. Also, similarly, M with a straight line added to the channel part
OS F E ”r is depression type MO5F
ET is shown.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MO
SFET is formed on the source 6J region and drain region formed on the surface of such a semiconductor substrate, and on the slope surface of the semiconductor substrate between the source region and the drain region, with a thin gate insulating film interposed therebetween. It consists of a gate 'Ff1i made of polysilicon. P channel MO3F
ET is formed in an N-type well region formed on the surface of the hemi-hip substrate. This allows the semiconductor substrate to
This constitutes a common substrate gate for a plurality of N-channel MO5FETs formed on the substrate. The N-type well region constitutes the substrate gate of the P-channel MOS FET formed thereon. The substrate gate or N-type well region of the P-channel MO5FET is coupled to the power supply terminal VCC of FIG.

Since the EFROM of this embodiment performs read or write operations in units of 8 bits, eight memory arrays and read/write circuits are provided. FIG. 1 representatively shows the memory array M-ARYO and its reading and writing circuits.

In this embodiment, the memory cells MC constituting the memory array M-ARYO are FAMO3) transistors Ql and Q
Each device is constructed of two nonvolatile semiconductor memory elements represented by No. 2. These storage elements are coupled to corresponding complementary data lines D1·DI −, -p n -σ1, respectively, and selectively connected to complementary common data lines CDO·CDO by a Y gate circuit YGO. A differential sense amplifier circuit SA is connected to the complementary common data lines CD0-CD0.
Data manual buffer DIBO used as O and write circuit
are combined. Complementary read signals from the two storage elements Q1 and Q2 of memory cell MC are amplified by the highly sensitive sense amplifier circuit SAO, improving the operating margin and increasing the read current. It is intended to speed up the operation.

In FIG. 1, an X address signal AXONAXi and Y address signals AYO to AYj supplied from external terminals are input to address buffers XADB and YADB, respectively. The X address buffers XADB and YADB use these external address signals to generate complementary internal address signals ago-axi and ayO to ayj (hereinafter; for example, an internal address signal a that is in phase with the external address signal AXO).
xO and an internal address signal 771 of opposite phase are combined to form a complementary internal address signal axQ), which is supplied to address decoders XDCR and YDCR. In the figure, an address buffer and an address decoder are shown as one circuit block XADB-DCR or YADB-DCR, respectively. Although not particularly limited, the address buffers XADB and YADB are activated by a timing signal ce supplied from the timing control circuit CTL.

The X address decoder XDCR is
Decodes the complementary address signal supplied from ADB,
A word line selection signal for selecting a word line of memory array M-ARYO-M-ARY7 is formed and supplied to each memory array. Further, the Y address decoder YDCR decodes the complementary internal address signal ayO=ayj supplied from the Y address buffer YADB, and selects a pair of complementary data lines of the memory arrays M-ARYO to M-ARY7. Y gate circuits YGO to YG7 that form selection signals and are provided corresponding to each memory array.
supply to.

Each memory array represented by memory array M-ARYO stores m words aW1 to Wm and n pairs of complementary data M.
DI・■～[]n-51 and m x n memory cells M arranged at the intersections of the word line and the complementary data line of this 4
It is composed of C.

Each memory cell MC has two F
AMO5) Transistor (non-volatile semiconductor memory element) Ql
and Q2. In each memory array,
Two FAMOs of memory cells MC arranged in the same row
5) The control gates of the transistors are commonly coupled to the corresponding word lines W l w W m, respectively, and the two FAMO3) of the memory cells MC arranged in the same column
The drain of Ranjisk is connected to the corresponding complementary data Ij11
)1-Di to Dn-Dn, respectively. The sources of the two FAMO 5) transistors of each memory cell MC are commonly connected and coupled 8 to a common source 1jlcs.

The common source line C3 includes, but is not particularly limited to, a debension type MO3FETQ3 and an N-channel MO5FE whose gates receive an i-layer inversion timing signal τ.
1'Q31 to ground.

During the write operation, the conductance of the MO3FETQ3 is made relatively small by the low level of the inverted timing signal 1τ, and the conductance of the MOSFETQ31 is made relatively small.
is in the off state. As a result, the potential of the common source line CS becomes a relatively high potential, and the potential of the common source line CS becomes relatively high.
The threshold voltage of the transistor is relatively high (therefore, even if a high write voltage is supplied to the data line during a write operation, the FAMO3 transistor connected to the non-selected word line) The leakage current that flows can be reduced. Note that during the read operation, the high level of the inverted timing signal 7τ makes the conductances of the MO3FETs Q3 and Q31 relatively large, so that the read operation is performed at high speed.

It is coupled to the corresponding switch MOS FET of the Y gate circuit YGO via the reset circuit PSO.

The preset circuit PSO includes equalizing MO3FETQ4 to Q5 provided corresponding to each complementary data line, and discharging MO3FETQ6. Q7-Q8. Consists of Q9. That is, an equalizing MO3FE is provided between the non-inverted data line and the inverted data line of each complementary data line.
TQ4 to Q5 are provided, and a discharge MO3FE'r is provided between each data line and the ground potential of the circuit.
Q6゜Q7~Q8. Q9 is provided. M for equalization
Address signals AXO to AXi, AYO are applied to the gates of O3FETQ4 to Q5 in the operating state of this EFROM.
~AYj and the 3& transition of the chip enable signal GE are detected, and a timing signal eq that is kept at a high level for a certain period of time is supplied. In addition, %10 SF for discharge
E T Q G, Q 7-Q8. The gate of Q9 is supplied with a timing signal dc which rises slightly faster than the timing signal eq in the operating state of the EFROM. As a result, the level of each complementary data line is EP
In the non-operating state of the ROM, MOSFETQ6. Q7
˜Q8° They are discharged to the ground potential of the circuit by Q9, and further short-circuited by MO5FETs Q4 and Q5 to be at the same level.

Each complementary data line DI-DI"Dn-Dn is further connected to a switch MOSFETQI of a corresponding Y gate circuit YGO.
O, Ql 1-QL 2. It is selectively connected to stone 1 via Ql 3 with a complementary common data line CDO. A data line selection signal Y1 formed by the address decoder YDCR is applied to the gates of these switches MO5FET.
xYn is supplied.

The complementary common data line CDO/GO1 is connected to the input terminal of the differential sense amplifier circuit SAO and the data input buffer DI.
The output terminal of B is coupled and further connected to the limiter MO3FET.
Load MOSFET QI through QI 51 and Q161
5 and the drain of Q16. limiter MO
A fixed positive bias voltage vb is applied to the gates of the 3FETs QI 51 and Q161. Also load MOSF
ETQ15 and Q16 have their gates coupled to the ground potential of the circuit, thereby acting as resistance elements having a predetermined conductance. That is, in the read operation mode of the EPROM, the read current of the two FAMoS transistors of the memory cell MC selected by the address signal and connected to the complementary common data lines CDO and CDO varies depending on the stored information, that is, the threshold voltage. Change. Therefore, the drain voltage of the load MO5FETQI5 and Q16, that is, the sense amplifier circuit SA
The input voltage of changes depending on these read currents. For example, if the storage information of FAMO3) transistor Q1 is logic "1" and the storage information of FAMO5 transistor Q2 is logic "0", then FAMO3) transistor Q1
The threshold voltage of is lower than the word line selection level,
The threshold voltage of F AMOS transistor Q2 is made higher than the word line selection level. Therefore, F
AMOS transistor Q1 is in the on state, Q2 is in the off state, and the non-inverting data line DI and the non-inverting common data line C
The value of the read current flowing through the DO becomes thicker.

Therefore, the drain voltage of the load MO3FET QI 5 is the same as that of the FAMOS) transistor Q1 and the load MO3FET Q
The voltage decreases to a predetermined voltage determined by the conductance ratio of 15. On the other hand, due to the off state of transistor Q2 (FAMOS), no read current flows through the inverted data line lower] and the inverted common data line 5-1, so the load M
The drain voltage of O3FETQI6 becomes a high voltage almost like the circuit power supply voltage Vcc. These voltage changes are
Since it is amplified by the differential sense amplifier circuit SAO, the read operation as an EPROM becomes faster and has higher sensitivity.

The sense amplifier circuit SA is activated in the read operation mode of this EPROM, and the sense amplifier circuit SA is activated in the read operation mode of this EPROM, and as described above, the sense amplifier circuit SA is in an operating state.
amplify the complementary readout signals of. The output signal of this sense amplifier circuit SA is supplied to the data output buffer DOB as read data of the selected memory cell MC.

The data output buffer DOB is a timing control circuit CT.
In synchronization with the timing signal os supplied from the sense amplifier circuit SA, the read data supplied from the sense amplifier circuit SA is sent to an external device via the output terminal DO.

In the write operation mode of this EFROM, the data driver cover sofa DIB is put into an operating state by the inverted timing signal Wτ supplied from the timing control circuit CTL, and uses the write data input from the external terminal DO as a complementary write signal, and uses the complementary common data as a complementary write signal. Line CDO・CDO
The data is written to the selected memory cell MC via the memory cell MC.

The timing control circuit CTL operates under a chip enable signal σ supplied from the outside, a program signal PGM, an output enable signal OE, and a high voltage for writing VpG.
I, the low voltage VCC for reading is selectively supplied to the various internal timing signals, the address decoder, and the data input bumper DIB.
/if Input layer high voltage vpp etc. are formed.

For example, if the chip enable signal CE is low level, the output enable signal surface is high level, and the program signal PGM is low level, the writing operation (program) mode is identified, the timing signal ce is set to high level, and the inverted timing signal is W1 and timing signal oe are set to low level. In addition, address decoder circuits XDCR, YDCR and data capuffer D
A high voltage vpp for writing is supplied to IB.

On the other hand, if the chip enable signal GE is low level, the output enable signal OE is low level, the program signal PGM is high level, and Vpp is a high voltage for writing, it is identified as verify mode, and the above timing signals ce, oe and inverted Set the timing signal to high level. In this verify mode, XDCR, YD
The operating voltage of CR and DIB is the above-mentioned high voltage vpp.
The power supply voltage Vcc is cut down to a relatively high power supply voltage Vcc and then supplied.

Furthermore, when the chip enable signal GE is at low level,
If the output enable signal surface is low level, the program signal PGM is high level, and VPP is a low voltage for reading (same level as Vcc), the read mode is entered, and the timing signals co and os and the inverted timing signal W1 are set to high level. be done.

FIG. 2 shows an example of a timing diagram in the read operation mode of the EFROM of this embodiment. An overview of the read operation of the EFROM of this embodiment will be explained with reference to this timing diagram.

In the read operation mode of the EPROM, the program signal Fτ (not shown) remains at a high level, and VP
The P voltage terminal is set to the normal read voltage Vcc.

As mentioned above, address signals AXO-AXi.

A timing signal e that detects the transition of AYO-AYj and the chip enable signal σπ and is kept at a high level for a certain period of time.
q and dc equalize MO3FETQ4 to Q5 and discharge MOS of preset circuit pso.
FETQ6. Q7-Q8. Q9 is turned on. Therefore, each complementary data line is discharged to the ground potential of the circuit, and further equalized to the same level.

Address signals AX and A for specifying address Aa
By supplying Y and changing the chip enable signal σ from high level to low level, EFR
OM is activated. The output enable signal OE changes from high level to low level at the timing when the selection of the memory cell is completed and the read signal is determined by the sense amplifier circuit SA.

Although not particularly limited, address signals AXO-AXi, A
A timing signal eq that detects the transition of YO to AYj and the chip enable signal CE and is kept at a high level for a certain period of time.
and dc change from high level to low level after a certain period of time has elapsed. As a result, the equalization operation and discharge operation by the preset circuit PSO of each complementary data line is stopped.

Due to the low level of the chip enable signal CE, the timing signal ce rises from low level to high level, and the word line selection signal and data line selection signal are sent from the X address decoder XDCR and Y address decoder YDCR to the corresponding word line and Y gate circuit of the memory array. YG
is supplied to the switch MO3FET. This results in X
Address signals AXO to AXi and Y address signal AYO
~The memory cell specified by AYj is selected, and the corresponding complementary data line and switch MO of Y gate circuit YG are selected.
Complementary common data lines CDO/CD via S FET
Connected to O. After the timing signals dc and eq become low level, the equalizing MO5FET and the discharging MO3FET of the preset circuit PSO are all turned off. Therefore, the load MOS F
The potential of the complementary data line is rapidly charged by the read current flowing through ET. Furthermore, depending on the selection level of the word line, the two FAMO transistors constituting the selected memory cell will be in either an on state or an off state, and a difference will occur in the value of the read current flowing through the complementary data line. Two load MO3FETQ1
Differences also occur in the drain voltages of Q5 and Q16, that is, the two input voltages of the sense amplifier circuit SAO, depending on the information stored in the memory cell. This voltage difference is determined by the sense amplifier circuit S
The signal is rapidly expanded by the amplification operation of the AO, and is transmitted to the data output buffer DOB as its high level/low level binary output signal.

Next, when the output enable signal OE falls from high level to low level with a slight delay, timing control circuit C
A timing signal oe is formed by TL and supplied to the data output buffer DOB. Data output cover sofa D
OB is activated by this timing signal oe, and sends the read data supplied from the sense amplifier circuit SAO to an external device via the output terminal DO.

As shown in the above embodiment, this invention can be applied to FAMO
5) When applied to an EPROM using transistors as memory cells, the following effects can be obtained. That is, (11) a memory cell is constituted by two non-volatile memory elements which are made to have a relatively high threshold voltage or a low threshold voltage complementary to the word line selection level according to the stored information, A differential sense amplifier circuit for amplifying a memory cell read signal transmitted via this complementary common data line to a complementary common data line to which this memory cell is selectively coupled via a column system selection circuit. and,
By providing a write circuit for writing externally supplied write data into each memory cell as a complementary signal, the memory information is stored in a complementary manner by two nonvolatile memory elements, and the read signal is a differential sense signal. Since it is amplified by the amplifier circuit, it is possible to increase the read current, and it is possible to achieve the effect of being able to perform a read operation with high sensitivity and high speed.

(2) According to the above item (11), it is possible to obtain the effect that a semiconductor memory device such as an EPROM can be improved with improved operating margin and faster read operation.

(3) According to item (1) above, it is possible to compensate for the deterioration of the read signal due to deterioration of the characteristics of the memory element, insufficient writing, or changes over time, and it is possible to provide a semiconductor memory device such as a highly reliable EPROM, and to extend its durability. The effect is that the period can be expanded.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, the MO3FET for equalization of the Briscent circuit PSO in Fig. 1 is P
It may be configured with a complementary switch MO5FET in which an inter-channel O3FET and an N-channel MO3FET are connected in parallel, or the discharge MOS FET may be configured with a P-channel MO3F whose source is connected to a voltage generation circuit.
By using ET, the complementary data line may be precharged to a desired high level. Further, between the sense amplifier circuit SAO and the Y gate circuit YGO, there is an inverter circuit that receives the potential of the complementary common data line, and an N-channel MO5F for applying negative feedback by the output signal of the inverter circuit.
By providing ETt-, changes in the read signal of the complementary common data line may be limited.

Furthermore, various embodiments can be adopted, such as the configuration of the read current supply circuit using the load MO3FET, the unit bit for reading or writing, and the specific configuration of other circuits.

In the above explanation, the invention made by the present inventor has been explained in terms of its application to the reading circuit of an EPROM using FAMO3 as a memory cell, which is the field of application in which the invention was made, but it is not limited thereto. For example, the present invention can be applied to semiconductor memory devices such as EEPROMs using memory elements such as mask ROM'pMNO5 (metal nitride oxide semiconductor). The invention can be applied to a semiconductor memory device using a memory element having a threshold voltage or a low threshold voltage, or a semiconductor integrated circuit device including the same.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a memory cell is constituted by two non-volatile memory elements which are made to have a threshold voltage that is complementary to a selection level of a word line, which is either high or low according to stored information. A differential sense amplifier circuit for amplifying the memory cell read signal transmitted via the complementary common data line and write data supplied from the outside are selectively coupled to the complementary common data line. By providing a write circuit to write complementary signals to the memory cell, the memory information is stored in a complementary manner by two nonvolatile memory elements, and the read signal is amplified by the differential sense amplifier circuit, so that when reading The charging current can be increased without deteriorating the noise margin, and semiconductor memory devices such as EPROMs with improved operating margins and faster read operations can be realized.

[Brief explanation of the drawing]

1 is a circuit diagram showing an embodiment of an EPROM memory array and its peripheral circuit to which the present invention is applied; FIG. 2 is an operation timing diagram showing an example of read operation of the EPROM of FIG. 1; FIG. 3 is a circuit diagram showing a read circuit including a sense amplifier in a conventional EPROM. M-ARYO...memory array, MC...memory cell, XADB-DCR...X address buffer decoder, YADB-DCR...Y address eight sofa decoder, PSO...Bricent circuit, YGO・・Y
Gate, SAO... sense amplifier circuit, DIBQ...
・Data input cover sofa, DOBO...data output buffer, CTL...timing control circuit. Ql, Q2...FAMO3) Ranjisk, Q3...
Depression type MOSFET5. Q4-Q14. Q
31. Q151. Q161 ・ ・ ・N-channel MOSFET, Ql 5. Ql 6...P Chi? 7
Ne71/MO3FET. Representative Patent Attorney Katsuma Ogawa ′ Figure 2

Claims (1)

Claims: 1. Each gate is coupled to a common word line, each drain is coupled to a complementary data line,
Memory cells each consisting of two non-volatile storage elements are arranged in a matrix and have a threshold voltage that is either high or low complementary to the selected level of the word line according to storage information. a memory array configured, a complementary common data line to which the complementary data line is selectively coupled via a column system selection circuit, and amplification of a read signal of the memory cell transmitted via the complementary common data line. 1. A semiconductor memory device comprising a differential sense amplifier circuit. 2. The non-volatile memory elements constituting the above memory array are:
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a FAMOS transistor.