JPS60209846A - Interruption processing system - Google Patents

Abstract

PURPOSE:To inhibit generation of an interruption request signal form being duplicated to another central processing unit by holding an interruption unit in the state where the interruption request signal is issued to one central processing unit. CONSTITUTION:A decoding part 9 sets an interruption request trigger signal to a position corresponding to the interruption unit number in an interruption pending latch part 10. When the interruption request trigger is set, a precedence determining circuit 14 sets the interruption request signal to a signal transmitting part 15-0 to transfer the interruption request signal to the central processing unit in the mask on side and transmits the interruption request signal to a central processing unit 1-0. At this time, an interruption requesting bit is set to a latch 16-0, and the indication of this requesting is reported to a selecting circuit 13. Hereafter, the selecting circuit 13 does not output the interruption request trigger corresponding to the pertinent interruption unit number to the precedence determining circuit 14.

Description

Detailed Description of the Invention (A) Technical Field of the Invention The present invention provides a three-interrupt processing method, in particular, an input/output system area is created on the main memory so that the central processing unit can directly access information regarding input/output interrupts. This invention relates to an interrupt processing system in which one interrupt bending/launch and an interrupt request generation section are installed in a wired logic circuit, and one interrupt processing is executed while issuing two interrupt request signals in a data processing system configured as described above. It is.

(B) Technical background and problems Conventionally, input/output interrupt processing has been performed as follows.

That is, between a plurality of channel devices (CHP) and a plurality of central processing units (CPU), the correspondence between the channel device with two interrupt sources and the central processing unit that accepts the interrupt is determined, and the corresponding interrupt is accepted. After this, the central processing unit notifies the channel device, and if there are interrupts for multiple channels or subchannels in the channel device, the channel device selects among them based on the priority order, and then interrupts the corresponding channel device. We are trying to incorporate C3W and other information related to channels. For this reason, the central processing unit is placed in a standby state until the channel device performs the acquisition. Also, considering the case of a system with multiple central processing units, when an interrupt of another channel occurs in one channel device, it is assumed that the previous interrupt is taken into one central processing unit. Although it is desirable to be able to interrupt other central processing units even when the central processing unit is currently in use, conventionally it has not been possible to interrupt other central processing units.

(C) Object and structure of the invention The present invention aims to solve the above points,
The present invention focuses on the fact that the above-mentioned input/output system area is provided on the main storage device, and aims to provide an interrupt processing method that solves the above-mentioned problems. And for that reason 2
The interrupt processing method of the present invention includes one or more central processing units, one or more channel devices, and a main storage device.

It is configured to suspend input/output interrupts corresponding to interrupt units corresponding to channels or interrupt level units, and an input/output system area is created in a part of the main storage device to suspend the input/output interrupts corresponding to the interrupt units. In a data processing system that retains information regarding interrupts and has an interrupt queue, an interrupt bending system that suspends an interrupt request to the central processing unit and an interrupt level corresponding to the interrupt unit number for each interrupt unit. At the same time, one of the interrupt requests pending in the interrupt bending latch is selected based on mask information including an interrupt mask from the central processing unit and the interrupt level, and an interrupt request signal is sent to the central processing unit. When the interrupt request generating section that issues the interrupt request signal is sent, the interrupt request generating section holds the interrupt unit corresponding to the interrupt request while issuing the interrupt request signal to one central processing unit. The central processing unit is configured to prohibit the generation of duplicate interrupt request signals to other central processing units regarding the interrupt request, and the central processing unit that receives the interrupt request signal Refers to the contents of the system area and starts execution of interrupt processing.
The present invention is characterized in that the interrupt request and the pending state are reset. This will be explained below with reference to the drawings.

(D) Embodiment of the Invention FIG. 1 shows an embodiment of a data processing system to which the present invention is applied, and FIG. 2 shows a main part configuration of an embodiment of the main memory control section shown in FIG.

In FIG. 1, 1-0.1-1 is a central processing unit, 2 is a channel device, 3-0.3-1°- is a subchannel, and 4 is a main memory control unit.

5 represents a main storage device, and 6 represents an input/output system area.

The main memory control unit 4 performs processing to control access to the main memory device.2 In the case of the present invention, an input/output system area 6 is provided on the main memory device 5, and the central processing unit 1 is not required. Accordingly, the area 6 can be referred to without being mediated by the channel device 2, so to speak. Since the channel device 2 writes information corresponding to the occurrence of an interrupt factor corresponding to a channel or subchannel in the area 6, when the central processing unit 1 performs interrupt processing, the central processing unit 1 1 is the above area 6
It becomes possible to import and process the contents of

In FIG. 2, 1-i and 4 correspond to those in FIG.

Reference numeral 7 corresponds to an interrupt bending/launch according to the present invention, and the remainder 8 in the main memory control section shown in 2 corresponds to an interrupt request generation section according to the present invention. More specifically, 9 is an interrupt bending decode section, 1O-0 and 10-1 are interrupt bending latch sections, 11 is a scan counter, 12 is a timing adjustment circuit, and 110 and 13-1 are selection circuits, respectively. 14-0 and 14-1, which function to output information from the bending latch section 10-p having the corresponding number p via the timing adjustment circuit 12 in response to the selection signal;
are respectively priority determination circuits.

15-0 and 15-1 are respectively interrupt request signal sending parts, 16-0 and 16-1 are respectively interrupt request instruction lunches, 17 is a human output mask information receiving part, 18 is a scan counter value receiving register, and 19 is a The mask information selection circuit selects mask information based on conditions regarding the PSW mask and channel mask corresponding to the scan counter value, and 20 represents an input/output mask information transmitter.

Assume now that the scan counter value "p" is set in the register 18 and the mask information corresponding to the value "p" is selected. When this mask information reaches the priority determination circuit 14, the scan counter 11 has a value rp+3.
It is outputting J.

For this purpose, the timing adjustment circuit 12 is (p+3)−
3 is calculated and the value ITpJ is given to the selection circuit 13 as 1 selection information. As a result, the bending launch department
From O, an interrupt request from a position corresponding to the value rpJ is just guided to the priority determining circuit 14.

Needless to say, when an interrupt request occurs corresponding to a channel or an interrupt level unit (in this specification, both are collectively referred to as an interrupt unit for simplicity), the channel device 2 shown in FIG. Necessary information is written in the above-mentioned input/output system area and, for example, an interrupt request trigger signal, the above-mentioned interrupt unit number, and interrupt level are supplied to the 2-interrupt bending/decoding section 9. At this time, the decoding section 9.

The supplied information is decoded and 1 is placed at the position corresponding to the interrupt unit number in the 2-interrupt bending/launch unit IO.
Serves interrupt request trigger signals, etc. In other words, it is noted that an interrupt factor has occurred with respect to the interrupt unit.

In this way, if an interrupt factor occurs corresponding to each separate interrupt unit, it is written in the interrupt bending/launch unit 10, so that the corresponding interrupt factor is The interrupt request trigger and the like for the interrupt unit corresponding to the counter value "p" are guided to the priority order determining circuit 14. At that time, mask information from the central processing unit is supplied to the priority order determining circuit 14 in a form corresponding to the scan counter value "-p".

In the case of the configuration shown in FIG. 1, the priority determination circuit 14 transmits an interrupt request signal to the central processing unit on the side where the mask is on when the interrupt request trigger 9 is set. A request signal is sent to 15-0. by this.

Two interrupt request signals are sent to the central processing unit 1-0. At this time, the interrupt requesting bit is sent to the interrupt requesting instruction latch 16-0, and the sending unit 15-0
The selection circuit 13 is notified of the requesting instruction together with the contents of . Thereafter, the selection circuit 13 selects the interrupt request trigger corresponding to the interrupt unit number from the priority determination circuit 14.
Do not output to . In the above, it is assumed that the interrupt request signal 9 is issued to the central processing unit on the side where the mask is on, but the two central processing units 1 shown in FIG.
When the respective masks from -0 and 1-1 are both on, an interrupt request signal is issued to the central processing unit on the smaller number side.

As mentioned above, when the central processing unit 1-0, for example, receives an interrupt request signal from the interrupt unit having the interrupt unit number rpJ, the central processing unit 1-0 executes the above input/output in correspondence with the interrupt unit. It takes in necessary information from the card system area 6 and performs interrupt processing.

The contents of the above interrupt bending latch 7 are as follows.

When a mode in which interrupts are made in units of channels is in use, the central processing unit 1 sends an interrupt when it receives an interrupt request signal from the interrupt request signal sending unit 15, and a mode in which interrupts are made in units of interrupt levels is used. When applied, the two interrupt queues (formed in the input/output system area 6) are reset when they become empty.

Taking into consideration the fact that in conventional systems, the channel device dequeues the interrupt queue in the former mode, and the central processing unit dequeues in the latter mode, the present invention uniformly performs these functions. It can be assumed that this is because they were made so that they could be handled. Above latch 7
5 interrupt requests after reset
6 is reset.

In the manner described above, the central processing unit executes a series of interrupt processing. In this case, 1, for example, interrupt unit #r
Under the state in which an interrupt request signal corresponding to Even if there is one, the corresponding interrupt request signal may be sent to the central processing unit 1-1. but.

Under a state in which an interrupt request signal corresponding to interrupt unit #r is issued to the central processing unit 1-0, an interrupt request signal for the same interrupt unit #r is issued to another central processing unit 1-1. Emitting is prohibited.

Note that if you use an instruction to check the presence or absence of 9 interrupts and to import interrupt information when an interrupt exists, forcing the input/output mask of psw to be on will check the presence or absence of 1 interrupt and the above-mentioned interrupts. Once the unit is known, subsequent operations follow the same procedure. Furthermore, when a command to change the input/output mask or the human output sub-mask is issued, it is sufficient to reset the above-mentioned interrupt request mid-finger lunch so that the interrupt by the new mask can be seen.

(E) Detailed Description of the Invention (1) According to the present invention, the aspect in which the central processing unit is placed in an undesired standby state under the conventional system is eliminated. When two interrupt factors occur.

This also solves the problem that it was not possible to interrupt separate central processing units for each factor.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a data processing system to which the present invention is applied, and FIG. 2 shows a main part configuration of an embodiment of the main memory control section shown in FIG. In the figure, ↓ is the central processing unit, and 2 is the channel device. 3 is a subchannel, 4 is a main memory control unit, 5 is a main memory, 6 is an input/output system area, and 7 is an interrupt bending
8 represents an interrupt request generating section. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Mori 1) Hiroshi (1 other person) fllffl 1-0 7-7

Claims (1)

[Scope of Claims] A device comprising one or more central processing units, one or more channel devices, and a main storage device, and holds input/output interrupts corresponding to interrupt units corresponding to channels or interrupt level units. In the data processing system, an input/output system area is provided in a part of the main storage device, and information regarding the input/output interrupt is held in correspondence with the interrupt unit, and an interrupt queue is provided. For each interrupt unit, an interrupt bending launch is provided to suspend the interrupt request to the central processing unit and the interrupt level corresponding to the interrupt unit number, and the mask information including the interrupt mask from the central processing unit and the above The interrupt request generating section selects one of the interrupt requests pending in the interrupt bending launch according to the interrupt level and issues an interrupt request signal to the central processing unit. While the above interrupt request signal is being issued to the processing device,
The interrupt unit is configured to hold the interrupt unit corresponding to the interrupt request, and to prohibit the generation of duplicate interrupt request signals to other central processing units regarding the interrupt request. An interrupt processing method characterized in that, upon receiving the signal, the central processing unit refers to the contents of the input/output system area, starts execution of interrupt processing, and resets the interrupt request and the pending state. .