JPS60207375A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60207375A JPS60207375A JP6457784A JP6457784A JPS60207375A JP S60207375 A JPS60207375 A JP S60207375A JP 6457784 A JP6457784 A JP 6457784A JP 6457784 A JP6457784 A JP 6457784A JP S60207375 A JPS60207375 A JP S60207375A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- film
- silicon film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 13
- 238000000605 extraction Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 2
- FBOUIAKEJMZPQG-AWNIVKPZSA-N (1E)-1-(2,4-dichlorophenyl)-4,4-dimethyl-2-(1,2,4-triazol-1-yl)pent-1-en-3-ol Chemical compound C1=NC=NN1/C(C(O)C(C)(C)C)=C/C1=CC=C(Cl)C=C1Cl FBOUIAKEJMZPQG-AWNIVKPZSA-N 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 238000005406 washing Methods 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 abstract description 31
- 229910021332 silicide Inorganic materials 0.000 abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 14
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 59
- 150000004767 nitrides Chemical class 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 239000010953 base metal Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000007127 saponification reaction Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は半導体装置のＩＦ１ｍ方法に係り、特にバイ
ポーラ型半導体集積回路装置ｔ（以下ＦＢＩＰ・ＩＣ，
ｌという。）におけるトランジスタの電極引出部の形成
方法の改ｎに関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an IF1m method for a semiconductor device, and particularly relates to a bipolar semiconductor integrated circuit device t (hereinafter referred to as FBIP/IC).
It's called l. This invention relates to a modification of the method for forming an electrode lead-out portion of a transistor in (1).
［従来技術〕
・一般に、ＢＩＰ・ＩＣにお番プるｌ−ランジスクは、
ｐｎｎ接合分離０択択酸化技術用いた酸化膜分離。[Prior art] - In general, the l-lan disc used in BIP/IC is
PNN junction isolation 0 Oxide film isolation using selective oxidation technology.
または３重拡散を用いる方法などによって電気的に独立
した島内に形成される。ここでは酸化膜分離法によって
ｎｐｎ トランジスタを形成する方法について述べる。Alternatively, they are formed in electrically independent islands by a method using triple diffusion. Here, a method for forming an npn transistor using an oxide film separation method will be described.
もちろん、これ以外の上記各種分離法を用いる場合、さ
らにはｐｎｐ トランジスタについても適用できるもの
である。Of course, when using the above-mentioned various separation methods other than this, it can also be applied to pnp transistors.
第１図（１）〜Ｉ）は従来の製造方法の使用工程段階に
おける状態を示す断面図である。以下この図について従
来の方法を簡単に説明する。低不純物濃度のｐ形（ｐ−
形）シリコン基板１にコレクタ埋込層となる高不純物濃
度のｎ形（ｎ＋形）層２を選択的に形成した後、それら
の上に１１−形エピタキシャルＨ３を成長させるＬ第１
図（ａ）］。次に、下敷酸化膜１０１の上に形成した窒
化鯖２０１をマスクとして選択酸化を施し゛（゛厚い分
離酸化膜１０２を形成するが、このときこの分＊＊化膜
１０２の下にはチャンネルカット用のｐ形層４が同時に
形成される。［第１図（ｂ ） ｊ、次に、上述の選択
酸化用のマスクとして用いた窒化１１Ｉ２０１を下敷酸
化膜１０１とともに除去して、改めてイオン注入保護用
の酸化膜１０３を形成し、フォトレジスト膜（この段階
での７オトレジスト膜は図示せず）をマスクとして、外
部ベース層となるｐ＋形層５を、さらに、上記フォトレ
ジスト膜を除去（，１１改めてフォトレジスト膜３０１
を形成し、これをマスクとして活性ベース層となるｐ形
層６をイオン注入法によって形成するＬ第１図（Ｃ）１
゜続いて、フォトレジスト１Ｉ３ｏ１を除去し、一般に
ホスシリケートガラス（ＰＳＧ）からなるパッシベーシ
ョン１１１４０１を被着させ、ベースイオン注入＠５．
６のアニールとＰＳＧ膜４０１の炊きしめとを兼ねた熱
処理を行なって、中間段階の外部ベース層５１および活
性ベース層６１とした襖、ＰＳＧ膜４０１に所要の開孔
７０ｄ３よび８０を形成して、イオン注入法によって１
ミツタ曙となるべきｎ＋形層７およびコレクタ電極取出
層となるべきｎ＋形Ｗ８を形成する［第１図〈ｄ）］。FIGS. 1(1) to 1) are cross-sectional views showing the state of the conventional manufacturing method at the stage of use. The conventional method will be briefly explained below with reference to this figure. p-type (p-
After selectively forming a highly impurity-concentrated n-type (n+-type) layer 2 on a silicon substrate 1 as a collector buried layer, an 11-type epitaxial layer H3 is grown thereon.
Figure (a)]. Next, selective oxidation is performed using the nitride layer 201 formed on the underlying oxide film 101 as a mask. A p-type layer 4 is formed at the same time.[FIG. 1(b)] Next, the 11I nitride 201 used as a mask for the selective oxidation described above is removed together with the underlying oxide film 101, and ion implantation protection is again performed. Using the photoresist film (7 photoresist film is not shown at this stage) as a mask, remove the p+ type layer 5, which will become the external base layer, and then remove the photoresist film (, 11 Photoresist film 301 again
Using this as a mask, a p-type layer 6, which will become an active base layer, is formed by ion implantation.
゜Subsequently, the photoresist 1I3o1 is removed, a passivation 111401, typically made of phosphosilicate glass (PSG) is deposited, and a base ion implantation @5.
A heat treatment that also serves as the annealing in step 6 and the heating of the PSG film 401 is performed to form the required openings 70d3 and 80 in the intermediate stage external base layer 51 and the active base layer 61, and in the PSG film 401. , 1 by ion implantation method
An n+ type layer 7 to be used as the Mituta Akebono layer and an n+ type layer W8 to be used as the collector electrode extraction layer are formed [FIG. 1 (d)].
その慢、各イオン注入層をアニールして、外部ベース層
５２および活性ベース層６２を完成させるとともにエミ
ッタ１１７１．１５よびコレクタ電極取出層８１を形成
した優に、ベース電極取出用の需孔５０を形成し、各開
孔部５０．７０お５−
よび８０に電極の突抜は防止用の金属シリサイド［白金
シリサイド（Ｐｔ −８＋ ）、パラジウムシリサイド
（Ｐｄ −８ｉ ）など］膜５０１を形成した上で、ア
ルミニウム（Ａ１）のような低抵抗金属によってベース
電極配置１ｍ９．エミッタ電極配線１０およびコレクタ
電極配線１１を形成する［第１図（ｅ）］。After that, each ion-implanted layer was annealed to complete the external base layer 52 and active base layer 62, and the emitter 1171.15 and collector electrode extraction layer 81 were formed. After forming a metal silicide [platinum silicide (Pt -8+), palladium silicide (Pd -8i), etc.] film 501 in each opening 50, 70, 5- and 80 to prevent electrode penetration, , base electrode arrangement 1 m9. by a low resistance metal such as aluminum (A1). Emitter electrode wiring 10 and collector electrode wiring 11 are formed [FIG. 1(e)].
第２図はこの従来方法で製造されたトランジスタの平面
パターン図である。ところで、トランジスタの周波数特
性はベース・コレクタ容量およびベース抵抗などに依存
し、周波数特性の向上にはこれらを小ざくする必要があ
る。上記構造ではベース抵抗を低下するためにｐ＋形外
部ベースＭ５２を設けたのであるが、これはベース・コ
レクタ容量の増大を招くという欠点がある。また、ベー
ス抵抗はエミツタ層７１とベース電極取出開孔５０との
距離り、にも依存し、従来のものではベース電極配線９
とエミッタ電極配線１０との間隔と各電極配線９．１０
の各開孔５０．７０からのはみ出し分どの合計距離とな
っており、フォトエッ６−
チングの精度を向上して電極配線間隔を小さくしても、
上記はみ出し分はどうしても残る。FIG. 2 is a plan pattern diagram of a transistor manufactured by this conventional method. By the way, the frequency characteristics of a transistor depend on the base-collector capacitance, base resistance, etc., and it is necessary to reduce these to improve the frequency characteristics. In the above structure, the p+ type external base M52 is provided to reduce the base resistance, but this has the drawback of increasing the base-collector capacitance. The base resistance also depends on the distance between the emitter layer 71 and the base electrode lead-out hole 50, and in the conventional case, the base electrode wiring 9
and the distance between the emitter electrode wiring 10 and each electrode wiring 9.10
What is the total distance of the protrusion from each opening 50.70?
The above protrusion will inevitably remain.
［発明の概要］
この発明は以上のような点に岐みてなされたもので、ベ
ース電極をポリシリコン膜と金属シリサイド膜との重畳
層を介して活性ベース領域から直接取出すようにするこ
とどエミッタ１１極の一部をポリシリコン膜で形成して
このポリシリコン膜をマスクとして上記ベースの金属シ
リサイド暎形成のためのコンタクト開けを行なうことに
よって、エミツタ層とベース電極開孔との距離の中に両
電極配線の各開孔からのはみ出し分を組入れる要がなく
、上記距離を短縮でき、しかも＾不純物ＩＦＪｉの外部
ベース層を用いずにベース・コレクタ容量の増大の生じ
ない半導体装置の興造方法を提供することを目的として
いる。[Summary of the Invention] The present invention has been made in view of the points mentioned above, and it is possible to directly extract the base electrode from the active base region through a superimposed layer of a polysilicon film and a metal silicide film. By forming a part of the 11 poles with a polysilicon film and using this polysilicon film as a mask to open a contact for forming the base metal silicide, the distance between the emitter layer and the base electrode opening is made. A method for manufacturing a semiconductor device that eliminates the need to incorporate protruding portions of both electrode wirings from each hole, shortens the above-mentioned distance, and does not require an external base layer of impurity IFJi and does not cause an increase in base-collector capacitance. is intended to provide.
［発明の実施例］
第３＠（ａ）〜（ａ）はこの発明の一実施例による製造
方法の主要工程段階における状態を示す断面図で、第１
図の従来例と同等部分は同一符号で示す。まず、第１図
（ｂ）に示す状態までは従来と同様に、ｐ−形シリコン
基板１にｎ＋形コレクタ埋込層２．ｎ−形エピタキシャ
ル層３．チャンネルカット用ρ形層４および分離用酸化
Ｉｌ！１０２を形成した侵、第１図（ｂ）における窒化
膜２０１および下敷酸化膜１０１を除去し、改めてイオ
ン注入保護用の酸化ｗＡ１０３を形成し、図示しないフ
ォトレジストマスクを介して活性ベース層となるｐ形層
６をイオン注入法によって形成し、ベース電極開孔とな
るべき領域近傍の上記酸化膜１０３を除去し、その除去
部分を含めて全上面にポリシリコン膜６０１を被着させ
る［第３図（ａ）］。次に、ポリシリコン１６０１の表
面にｐ形不純物を全面に導入してから、シンタリングを
行なうことによってｐ形層６を中間段階の活性ベース領
域６１とした後、ポリシリコンｆｉｌ ６０１を選択エ
ツチング除去し、改めて鹸化を行なって酸化膜１０３が
あ〕た位置に酸化１１１１０５．残されたポリシリコン
購６０１の上に酸化膜゛１０６を形成し、さらに全上面
にＰ Ｓ Ｇ ８４４０ ’Ｉ ・ど形成する［第３図
（ｂ）］。次に、フォトレジストマスク（図示せず）を
用いた選択エツチングによって、エミツタ層およびコレ
クタ電極取出層となるべき領域の酸化１１１０５および
ＰＳＧＩ１４０１を除去し、ポリシリコン膜６０２を被
着させて、このポリシリコン膜にｎ形不純物を高濃度に
イオン注入した後ドライブを行ない該ポリシリコン膜か
ら拡散させてエミッタ層となるべぎｎ＋形層７１および
コレクタ電極取出層となるべきｎ＋形層８１を形成する
［第３図（Ｃ）］。次に、上記拡散源となったポリシリ
コン膜部分６０２．８０３のみを残すように選択エツチ
ングした後、レジストｗＡ３０２をマスクとしてベース
・コンタクトの窓開けを行なう［第３図（ｄ）］。この
とき、レジスト賎３０２は上記エミツタ層形成のポリシ
リコン１！６０２の内部になるようにして、上記ポリシ
リコン膜を一部マスクとしてベース俸コンタクトとそれ
に続くポリシリコンｌｌ６０１上の酸化膜１０６．ＰＳ
Ｇ膜４０１をエツチング除去している。低温（８００℃
〜９００℃程痕）での酸化を行なってｎ十９一
層のポリシリコン膜８０２．６０３上に厚い酸化１１１
０８を、また０層のシリ」ン基板６２ど０＋層のポリシ
リコン膜上に薄い酸化膜１０７を形成する［第３図（ｅ
）］。これはよく知られたようにｎ＋不純物のリンや砒
素が高濃度に入ったシリコンおよびポリシリコンでは低
温はど増速層化が行なわれることを使用し′Ｃいる。次
に、酸化ＷＩ４１０７のみをウォッシュアウトしてＰ
ｔ、Ｐ ｄ、Ｔ Ｉ、Ｗ 。[Embodiment of the Invention] Part 3 (a) to (a) are cross-sectional views showing states at main process steps of a manufacturing method according to an embodiment of the present invention.
Portions equivalent to those of the conventional example in the figure are indicated by the same reference numerals. First, up to the state shown in FIG. 1(b), as in the conventional case, a p- type silicon substrate 1 and an n+ type collector buried layer 2. n-type epitaxial layer 3. ρ-type layer 4 for channel cutting and oxidized Il for isolation! 102, the nitride film 201 and underlying oxide film 101 shown in FIG. A p-type layer 6 is formed by ion implantation, the oxide film 103 near the region where the base electrode hole is to be formed is removed, and a polysilicon film 601 is deposited on the entire upper surface including the removed portion [Third Figure (a)]. Next, p-type impurities are introduced into the entire surface of the polysilicon 1601, and then sintering is performed to make the p-type layer 6 an intermediate active base region 61. After that, the polysilicon film 601 is selectively etched away. Then, saponification is performed again to form oxide 111105. at the position where oxide film 103 was. An oxide film 106 is formed on the remaining polysilicon layer 601, and a PSG 8440'I film is further formed on the entire upper surface [FIG. 3(b)]. Next, by selective etching using a photoresist mask (not shown), the oxide 11105 and PSGI 1401 in the areas to become the emitter layer and the collector electrode extraction layer are removed, and a polysilicon film 602 is deposited. After ion-implanting n-type impurities into a silicon film at a high concentration, driving is performed to diffuse them from the polysilicon film to form an n+-type layer 71 that will become an emitter layer and an n+-type layer 81 that will become a collector electrode extraction layer. [Figure 3 (C)]. Next, after selectively etching is performed so as to leave only the polysilicon film portions 602 and 803 which served as the diffusion source, a window for the base contact is opened using the resist wA 302 as a mask [FIG. 3(d)]. At this time, the resist layer 302 is placed inside the polysilicon layer 1!602 forming the emitter layer, and the polysilicon film is partially used as a mask to form the base contact and the subsequent oxide film 106.602 on the polysilicon layer 11601. P.S.
The G film 401 is removed by etching. Low temperature (800℃
A thick oxide 111 is formed on the single layer polysilicon film 802 and 603 by oxidation at ~900°C.
08, and a thin oxide film 107 is formed on the silicon substrate 62 of the 0+ layer and the polysilicon film of the 0+ layer [FIG. 3(e)
)]. This is based on the well-known fact that silicon and polysilicon containing high concentrations of n+ impurities such as phosphorus and arsenic undergo speed-enhancing layering at low temperatures. Next, wash out only the oxidized WI4107 and P
t, P d, T I, W .
ＭＯなどのシリコンおよびポリシリコン膜どの間に金属
シリ勺イドを形成する金属Ｍ（図示Ｕず）を全上面に蒸
着またはスパッタリングによって形成した後、シンタリ
ングを行なって金属シリサイド１１５０１．５０２をシ
リコン基体の露出面およびポリシリコン躾６０１表面の
上に形成してから金属シリサイド膜を残して金属層を王
水などでエツチング除去する［第３図（ｒ）］。次に、
パッシベーション用窒化ｗＡ２０２ （１！化膜でもよ
い）を被＠させた後にこの窒化膜２０２および酸化膜１
０８に選択エツチングを施してベースｉｔ極用コンタク
ト孔５０．エミッタ電極用コンタクト孔７１０−
Ｏおよびコレクタ電極用コンタクト孔８０を形成した後
、たとえばＡＩなどの低抵抗金属によってベース電極配
置９．エミッタ電極配置１１０およびコレクタ電極配線
１１を（れぞれ形成する［第３図（ｇ）］。After forming a metal M (not shown) on the entire upper surface by vapor deposition or sputtering to form a metal silicide between silicon and polysilicon films such as MO, sintering is performed to form metal silicide 11501.502 on the silicon substrate. and the surface of the polysilicon layer 601, and then the metal layer is removed by etching with aqua regia or the like, leaving the metal silicide film [FIG. 3(r)]. next,
This nitride film 202 and oxide film 1 are coated with nitride film 202 (1! oxide film may also be used) for passivation.
08 is selectively etched to form a base IT electrode contact hole 50. After forming the emitter electrode contact hole 710-O and the collector electrode contact hole 80, base electrode arrangement 9. is performed using a low resistance metal such as AI. Emitter electrode arrangement 110 and collector electrode wiring 11 are formed (FIG. 3(g)).
さらに別の一実施例としてベース電極の一部となるポリ
シリコン膜６０１の形成に際しｃ１第４図に示すように
、第３図（ａ）での酸化膜１０３のエツチングを過剰に
行なうことでシリコン島３の側壁にポリシリコン膜６０
１が接するようになり、第３図（（１＞中のポリシリコ
ンｐＩｉ４６０１のベース層６２との接面９０が小さく
Ｃよくベース面積の縮小が行なえる。酸化膜のエツチン
グはポリシリコン膜６０１からの拡散１ｉ１６３がベー
スｌ１ｉ１６２の深さと同程度となることが耐圧の関係
から最も良い。またポリシリコン膜６０１の形成をベー
ス１１６２の形成前に行なってベース層の深さの制御と
結晶欠陥防止の向上を行なうことができる。As another example, when forming the polysilicon film 601 that will become a part of the base electrode, as shown in FIG. 4, the oxide film 103 in FIG. A polysilicon film 60 is formed on the side wall of the island 3.
The contact surface 90 of the polysilicon pIi 4601 with the base layer 62 in FIG. It is best for the diffusion 1i 163 to be approximately the same depth as the base l1i 162 from the viewpoint of breakdown voltage.Also, the polysilicon film 601 is formed before the base 1162 is formed to control the depth of the base layer and prevent crystal defects. Improvements can be made.
第５図はこのようにしてＷＪＩ造された従来法の第２図
に対応するトランジス、夕の平面パターン図で、図に示
すように、エミッタ１１７１とベース電極９につながっ
ているポリシリコン膜６０１および金属シリサイド膜５
０１との距離Ｄ２は拡散のための窓開は部（７１に相当
）と拡散源となるポリシリコン膜６０２との重ね合わせ
部分で決まるので、従来の第２図に示した距離り、に比
して小ざくできる。ベース抵抗はその分だけ小さくなる
のみでな（、従来のｐ＋髪形外ベース１１１５２（数１
０Ω／口〜１００Ω／口）の代わりに低非抵抗の金属シ
リサイド躾５０１（数Ω／口〜数１０Ω／口）を用いた
ので小さくなる。さらに、ｐ＋形外部ベース層５２を用
いず、ベース層６２自体若干小さくなっているので、ベ
ース・コレクタ容量も小さくなり、トランジスタの周波
数特性は改良される。FIG. 5 is a plane pattern diagram of a transistor, which corresponds to FIG. 2 of the conventional method manufactured by WJI in this way, and as shown in the figure, the polysilicon film 601 connected to the emitter 1171 and the base electrode 9 and metal silicide film 5
The distance D2 from 01 to 01 is determined by the overlapping part of the window opening for diffusion (corresponding to 71) and the polysilicon film 602 serving as the diffusion source, so it is different from the conventional distance shown in FIG. You can make it smaller. The base resistance only decreases by that amount (, the conventional p + hairstyle outside base 11152 (Math. 1
The resistance becomes small because a low resistance metal silicide 501 (several ohms/hole to several tens of ohms/hole) is used instead of 0 ohms/hole to 100 ohms/hole. Furthermore, since the p+ type external base layer 52 is not used and the base layer 62 itself is slightly smaller, the base-collector capacitance is also reduced, and the frequency characteristics of the transistor are improved.
［発明の効果］
以上説明したように、この発明によれば、ベース電極を
ポリシリコン膜と金属シリサイド躾との２重層で引出ベ
ース層に隣接する分ｌ１ｌＩｌＢ！化躾上に形成しエミ
ッタ電極の一部をポリシリコン膜で形成してこのポリシ
リコン膜をマスクとして上記ベースの金属シリサイド膜
形成のためのベース・コンタクト開けを行なったので、
ベース電極取出領域とエミツタ層との距離を小さくしベ
ース抵抗を小さくできる。また、高不純物濃度の外部ベ
ース層を設けないで、ベース・コレクタ間容量を小さく
でき、周波数特性の良好なｉ〜ランジスタが得られるな
どの効果がある。[Effects of the Invention] As explained above, according to the present invention, the base electrode is formed of a double layer of a polysilicon film and a metal silicide film, and the portion adjacent to the lead-out base layer is formed into a double layer of a polysilicon film and a metal silicide layer. A part of the emitter electrode was formed on the substrate with a polysilicon film, and this polysilicon film was used as a mask to open the base contact for forming the base metal silicide film.
The base resistance can be reduced by reducing the distance between the base electrode extraction region and the emitter layer. Further, without providing an external base layer with a high impurity concentration, the base-collector capacitance can be reduced, and an i~ transistor with good frequency characteristics can be obtained.
第１図（ａ）〜（ｅ）は従来の製造方法の主要工程段階
における状態を示す断面図、第２図は従来方法で製造さ
れたトランジスタの平面パターン図、第３図（ａ）〜（
９）はこの発明の一実施例になる製造方法の主要工程段
階における状態を示す断面図、第４図は本発明の別の実
施例になる製造方法の主要工程での断面図、第５図はこ
の実施例の方法で製造されたトランジスタの平面バタ・
−ン図である。
図において、１はｐ−形シリコン基板、３はｎ−型エピ
タキシャル層（第１伝導形層）、６゜６１．６２はベー
ス層、７．７１はエミツタ層、１３−
８．８１はコレクタ電極取出層、９はベース電極、１０
はエミッタ電極、１１はコレクタ電極、１゜２は分離酸
化膜、１０１，１０５，１０６，１０７．１０８はシリ
コン酸化膜、２０１．２０２は窒化膜、３０２はレジス
ト躾、４０１はＰＳＧ膜（ｖｉ縁膜）、６００，６０１
，６０２はシリコン膜、５００．５０１は金属シリサイ
ド躾である。
代理人 大 岩 増 維
１４−
手続補正書（自発）
昭和５９年７ １９ 日
”““Ｐｓ＆＊” ’ Ｊ
ｌ、事件の表示 特願昭５９−６４５７７号２、発明の
名称
半導体装置の製造方法
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号名 称
（６０１）三菱電機株式会社
代表者片山仁八部
４、代理人
５、補正の対象
明細書の発明の詳細な説明の欄
６、補正の内容
明ＩＩＡ！第１２頁第９行の「低非抵抗」を「低抵抗」
に訂正する。
以上FIGS. 1(a) to (e) are cross-sectional views showing the main process steps of the conventional manufacturing method, FIG. 2 is a plane pattern diagram of a transistor manufactured by the conventional method, and FIGS. 3(a) to (e).
9) is a cross-sectional view showing the main process steps of a manufacturing method according to an embodiment of the present invention, FIG. 4 is a cross-sectional view showing the main steps of a manufacturing method according to another embodiment of the present invention, and FIG. is the flat pattern of the transistor manufactured by the method of this example.
- is a diagram. In the figure, 1 is a p-type silicon substrate, 3 is an n-type epitaxial layer (first conductivity type layer), 6°61.62 is a base layer, 7.71 is an emitter layer, and 13-8.81 is a collector electrode. Extraction layer, 9 base electrode, 10
is an emitter electrode, 11 is a collector electrode, 1゜2 is an isolation oxide film, 101, 105, 106, 107.108 are silicon oxide films, 201.202 is a nitride film, 302 is a resist layer, 401 is a PSG film membrane), 600,601
, 602 are silicon films, and 500 and 501 are metal silicide films. Agent Masuo Oiwa 14- Procedural amendment (spontaneous) July 19, 1980 "Ps &*" J l, Indication of case Patent application No. 1982-64577 2, Title of invention Method for manufacturing semiconductor devices 3. Relationship with the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name
(601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4, Agent 5, Detailed explanation of the invention in the specification subject to amendment 6, Contents of the amendment IIA! “Low non-resistance” in line 9 of page 12 is changed to “low resistance”
Correct. that's all
Claims (2)
タ領域を構成すべき第１伝導形層を形成する第１の工程
、この第１伝導形層の表面部の一部に第２伝導形のベー
ス碩を形成する第２の工程、上記ベース層上の一部から
これに接する上記分離領域の上にわたってシリコン膜を
形成する第３の工程、上記ベース層上を含む上記第１伝
導形層の表面上および上記シリコン膜の上にシリコン酸
化膜を形成する第４の工程、上記シリコン酸化膜に選択
エツチングを施してコレクタ電極取出層を形成すべき部
分およびエミツタ層を形成すべき部分の上の上記シリコ
ン酸化膜を除去する第５の工程、この工程復シリコン膜
を形成し第１伝導形の不純物を高濃度に導入した模、？
ニーリングを施して上記、］レクタ電極取出層を形成す
べき部分および上記エミツタ層を形成ずべき部分に第１
伝導形の不純物をシリコン膜から幕板ベース層内に拡散
させてエミツタ層およびコレクタ電極取出層を形成する
第６の工程、上記シリコン膜がエミツタ層およびコレク
タ電極取出層を覆い目す部分を除いて選択的に除去する
第７の工程、上記シリコン膜の一部を含めて選択的に上
記ベース層上およびシリコン膜上の酸化膜を除去する第
８の工程、第１伝導形の不純物が高ａｍに導入された少
なくともエミツタ層上のシリコン膜上に厚い酸化膜をお
よび第８の工程でｎにされたベース電極形成部上に薄い
酸化膜を比較的低温で酸化することによって形成する第
９の工程、第９の工程で形成されたべ−・スミ極形成部
上の薄い酸化膜のウォッシュアウトする第１０の工程、
上記ベースＴｉ極取出領域および上記ベース層上のシリ
コン膜の上に金属シリナイドＩＩＵを形成する第１１の
Ｔ稈、ならびに上記分離ｆＩ４域の上および上記分離領
域で囲まれ上記各工程を経た領域上に［ｌｉ！１ｍｌを
形成しそれぞれこの保護膜に設けた開孔を通１）で上記
シリコン膜上位置にベース１権、エミツタ層上位置にエ
ミッタ１（徊およびコレクタ１ｔｗＡ取出開上位置にコ
レラ９電極を形成する第１２の工程を備えたことを特徴
とする半導体装置の製造方法。(1) A first step of forming a first conductivity type layer which is surrounded by m regions and should constitute a collector region on the surface of the semiconductor substrate, and a second conductivity type layer is formed on a part of the surface of the first conductivity type layer. a second step of forming a base layer of the shape, a third step of forming a silicon film from a part of the base layer to the isolation region in contact therewith, and a third step of forming a silicon film over the base layer including the first conductivity type. A fourth step of forming a silicon oxide film on the surface of the layer and on the silicon film, selectively etching the silicon oxide film to form a collector electrode extraction layer and an emitter layer. In the fifth step of removing the above-mentioned silicon oxide film, a silicon film is formed after this step and impurities of the first conductivity type are introduced at a high concentration.
The first layer is applied to the area where the rectifier electrode extraction layer is to be formed and the area where the emitter layer is to be formed.
A sixth step of diffusing conductive impurities from the silicon film into the curtain base layer to form an emitter layer and a collector electrode extraction layer, except for the portion where the silicon film covers the emitter layer and the collector electrode extraction layer. an eighth step of selectively removing the oxide film on the base layer and the silicon film including a part of the silicon film; A ninth step in which a thick oxide film is formed on at least the silicon film on the emitter layer introduced in the am and a thin oxide film is formed on the base electrode formation portion which has been made n in the eighth step by oxidizing at a relatively low temperature. a tenth step of washing out the thin oxide film on the base/sumi electrode formation portion formed in the ninth step;
The eleventh T culm in which metal silinide IIU is formed on the base Ti electrode extraction region and the silicon film on the base layer, and above the isolation fI4 region and on the region surrounded by the isolation region and subjected to each of the above steps. To [li! 1 ml was formed, and through the openings provided in each of the protective films 1), a base 1 electrode was formed on the silicon film, and an emitter 1 electrode was formed on the emitter layer. A method for manufacturing a semiconductor device, comprising a twelfth step.
の工程では、多結晶シリコン膜を全、Ｌ面に形成し第２
伝導形の不純物を導入後ベターニングを施してベース層
上の一部からこれに接する分ｍ領域の上にわたって残す
ことを特徴とする特許請求の範囲第１項記載の半導体装
置の製造方法。(2) Using a polycrystalline silicon film as the silicon film, the third
In the process, a polycrystalline silicon film is formed entirely on the L plane, and the second
2. The method of manufacturing a semiconductor device according to claim 1, wherein the conduction type impurity is introduced and then subjected to betering to leave it from part of the base layer to over the m region in contact with the base layer.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6457784A JPS60207375A (en) | 1984-03-30 | 1984-03-30 | Manufacture of semiconductor device |
| US06/698,523 US4665424A (en) | 1984-03-30 | 1985-02-05 | Semiconductor device |
| GB08508243A GB2157079B (en) | 1984-03-30 | 1985-03-29 | Electrode arrangement for semiconductor devices |
| US06/940,607 US4709469A (en) | 1984-03-30 | 1986-12-11 | Method of making a bipolar transistor with polycrystalline contacts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6457784A JPS60207375A (en) | 1984-03-30 | 1984-03-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60207375A true JPS60207375A (en) | 1985-10-18 |
| JPH0318738B2 JPH0318738B2 (en) | 1991-03-13 |
Family
ID=13262222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6457784A Granted JPS60207375A (en) | 1984-03-30 | 1984-03-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60207375A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6269517A (en) * | 1985-09-21 | 1987-03-30 | ドイチエ・アイテイ−テイ−・インダストリ−ズ・ゲゼルシヤフト・ミト・ベシユレンクタ・ハフツンク | Mounting method for contact on contact region of semiconductor substrate |
| JPS62114268A (en) * | 1985-11-13 | 1987-05-26 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS63114261A (en) * | 1986-09-11 | 1988-05-19 | フェアチャイルド セミコンダクタ コーポレーション | Self-aligning base shunt for transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563821A (en) * | 1978-11-06 | 1980-05-14 | Nec Corp | Semiconductor device |
| JPS5928378A (en) * | 1982-08-09 | 1984-02-15 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS5928377A (en) * | 1982-08-09 | 1984-02-15 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS645472A (en) * | 1987-06-30 | 1989-01-10 | Snow Brand Milk Products Co Ltd | Production of nutritive food |
-
1984
- 1984-03-30 JP JP6457784A patent/JPS60207375A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5563821A (en) * | 1978-11-06 | 1980-05-14 | Nec Corp | Semiconductor device |
| JPS5928378A (en) * | 1982-08-09 | 1984-02-15 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS5928377A (en) * | 1982-08-09 | 1984-02-15 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS645472A (en) * | 1987-06-30 | 1989-01-10 | Snow Brand Milk Products Co Ltd | Production of nutritive food |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6269517A (en) * | 1985-09-21 | 1987-03-30 | ドイチエ・アイテイ−テイ−・インダストリ−ズ・ゲゼルシヤフト・ミト・ベシユレンクタ・ハフツンク | Mounting method for contact on contact region of semiconductor substrate |
| JPS62114268A (en) * | 1985-11-13 | 1987-05-26 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS63114261A (en) * | 1986-09-11 | 1988-05-19 | フェアチャイルド セミコンダクタ コーポレーション | Self-aligning base shunt for transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0318738B2 (en) | 1991-03-13 |
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