JPS60194637A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To allow a receiver for frequency hopping spectrum spread communication to acquire synchronism securely by providing an FSK demodulator which receives a reverse spread signal and generates a data signal and a synchronism decision circuit which detects the coincidence between the data signal and a predetermined data pattern. CONSTITUTION:A conventional circuit is equipped with the 2nd decision circuit 15 consisting of the FSK demodulator 13 and a counter 14. Synchronism is acquired by using the output of the 1st decision circuit 2, but a control circuit 11 sends a timing signal 105 to the synchronism decision circuit 15 and the rate of ''1'' in the data signal is counted to decide on synchronism after tracking according to whether the counted value attains to a specific value or not. At this time, the value supplied to the counter 14 corresponds to the threshold level supplied to the 1st decision circuit 2, but this value is set according to an error rate of data and finely settable. The result of the 1st decision circuit 2 is determined by a signal-to-noise ratio and hardly influenced by AGC because the FSK demodulator 13 obtains the data signal by comparing a signal level with a noise level relatively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a synchronization circuit used in a receiver using a frequency hopping spread spectrum communication system.

[Prior art]

FIG. 1 is a block diagram of a synchronization circuit of a receiver in a conventional frequency hopping spread spectrum communication system. This synchronization circuit includes a frequency synthesizer 8 and a PN code generator 9 for generating a locally spread signal, and a received signal (hereinafter referred to as a preamble signal) in which the frequency of a carrier wave hops according to a PN code and predetermined data. 10
1 and a locally spread signal 104, forming a correlation signal 103 between
A correlation detector 1 consisting of a balance changer 3, a band pass filter 4, and an envelope detector 5; A first synchronization determination circuit 2 comprising an integrator 6 and a threshold detector 7;
OIQ; a synchronization tracking circuit 12 that maintains a synchronized state;
The control circuit 11 receives the output of the first determination circuit 2 and controls the VCOIO and synchronization tracking circuit 12.

The operation of this synchronous circuit will be explained. FIG. 2 shows a characteristic diagram of the correlation signal output with respect to the phase difference between the preamble signal 101 and the locally spread signal 104, where point A is in the synchronized state. The operation of this synchronization circuit is divided into acquisition, which adjusts the phase of the locally spread signal to range B in FIG. 2, and tracking, which adjusts the phase to the synchronized state at point A. First, in acquisition, the control circuit 11 changes the phase of the locally spread signal 104 and the determination circuit 2
monitor the output of When the determination circuit 2 determines that the phase of the locally spread signal 104 is within the range B, the control circuit 1
1 operates the synchronous tracking circuit 12 to complete acquisition and perform tracking. After this, the control circuit 11 again determines whether a synchronized state has been obtained based on the output of the first determination circuit 2,
Depending on the result, either re-acquiring or continuing synchronous tracking is performed.

However, in this conventional synchronous circuit, when the received signal level is constant and an automatic gain adjustment circuit (hereinafter referred to as AGC) is not required, the first determination circuit 2 makes a correct determination, but the received signal level is If the AGO is operated after the acquisition is completed to correct the fluctuation, there is a problem that correct judgment cannot be made.

For example, if you accidentally switch to tracking due to Hinane etc., the first
The determination circuit 2 has the disadvantage that it recognizes the fiber sound as a signal due to the action of AGC and cannot capture it again.

[Purpose of the invention]

An object of the present invention is to provide a synchronization circuit that can eliminate such runner-up problems and reliably acquire synchronization of a receiver in frequency hopping spread spectrum communication.

[Structure of the invention]

The configuration of the present invention includes a correlation detector that receives a spread spectrum signal modulated by predetermined data and forms a correlation signal indicating a correlation value between the spread spectrum signal and the local spread signal; The first step receives the correlation signal and makes a synchronization threshold judgment at a predetermined timing.
a determination circuit, a spread signal generator that forms the local spread signal, and a CO that generates a clock for the spread signal generator.
a synchronization tracking circuit that receives the spread spectrum signal and introduces a synchronization relationship with the local spread signal; and a control circuit that receives the determination output of the first determination circuit and controls the VCO and the synchronization tracking circuit. The synchronization circuit includes an FSK post-modulator that receives the despread signal from the correlation detector and translates the data signal, and detects the proportion of coincidence between the data signal of the demodulator and predetermined data, 1. The synchronization circuit according to the present invention is characterized in that a second determination circuit is added that supplies a determination output for determining synchronization when a match is detected to the control circuit. It uses a conventional synchronization circuit, a demodulator at F8 that receives the despread signal and generates a data signal, and detects a match between this data signal and a predetermined data pattern. It is composed of a second synchronization determination circuit.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is a pull diagram of an embodiment of the present invention, in which the data pattern at the time of the preamble signal is all "
1" is an example. This embodiment differs from the conventional circuit of FIG.
8 is provided with a second determination circuit 15 comprising a demodulator 13 and a counter 14 that determines whether the number of "1"s included in the data signal has reached a predetermined value within a certain period of time. It is characterized by

The operation of a circuit having such a configuration will now be described.

Acquisition of synchronization is carried out by the first judgment circuit 2 as in the conventional circuit.
However, in determining synchronization after tracking, the control circuit 11 sends the timing signal 10 to the second synchronization determination circuit 15.
5 is sent out, the ratio of ``1'' in the data signal is counted, and a determination is made based on whether the count value has reached a predetermined candy. At this time, the value given to the counter 14 corresponds to the threshold level given to the first judgment circuit 2, but this value is set according to the data error rate and can be set in detail. be.

In addition, the result of the judgment circuit 1 is affected by the change in noise level in the output of the detector by the AGC, and the first
The result of the judgment circuit 2 is the signal level of the demodulator 13 at F8,
In order to obtain data signals through relative comparison at the miscellaneous level,
It is determined by the signal-to-noise ratio and is not easily affected by AGC. Therefore, compared to conventional circuits, the synchronization circuit of this embodiment can correctly determine whether or not the synchronization state is established after acquisition and tracking.

〔Effect of the invention〕

As explained and explained above, the present invention provides a synchronization circuit that can reliably obtain a synchronized state even under conditions where the received signal level fluctuates in a frequency hopping spread communication receiver. It will be done. Therefore, by using this synchronization circuit, it is possible to effectively carry out mobile spread spectrum communication in which the received signal level fluctuates widely.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a synchronization circuit for conventional frequency phone pink reception, Fig. 2 is a correlation value pattern diagram explaining the operation of Fig. 1, and Fig. 3 is a block diagram of an embodiment of the present invention. It is. In the figure, 1...correlation detector,
2...First synchronization determination circuit, 3...Balanced modulator, 4...Band pass waver, 5...
・Enveloping line detector, 6...Integrator, 7...
・Threshold detector, 8...Frequency 1 synthesizer, 9...PN code generator, 10...
...VCOll...control circuit, 12...
...Synchronization tracking circuit, 13...FSK demodulation gain, 1
4...Counter, 15...Second synchronization determination circuit.

Claims (1)

[Claims] a correlation extractor that receives a spread spectrum signal modulated by predetermined data and forms a phase signal indicating a correlation value between the spread spectrum signal and the local spread signal; a first determination circuit that performs a synchronization threshold determination at the timing of;
a spread signal generator that forms the locally spread signal; a VCO that generates a clock for the spread signal generator; a synchronization tracking circuit that receives the spread spectrum signal and maintains a synchronous relationship with the locally spread signal; In a synchronization circuit that receives the determination output of the first determination circuit and includes a control circuit that controls the VCO and the synchronization tracking circuit, an F8 that modulates the signal despread from the track correlation detector with the Aisha data signal.
a second determination circuit that detects the proportion of coincidence between the data signal of the oIIMI device and predetermined data, and supplies a judgment output for determining synchronization to the control circuit when a coincidence of a predetermined proportion or more is detected; A synchronous circuit characterized by adding 9゛.