JP2720915B2 - Synchronous circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization circuit of a frequency hopping type receiving apparatus. [Prior Art] FIG. 4 shows, for example, “The latest spread spectrum communication system,
This is a synchronization circuit of a conventional spread spectrum communication apparatus shown in FIG. 6.11 of "RCDixon", published by Nippon Technology Economic Center Co., Ltd., November 30, 1978. In FIG. 4, 1 is an envelope detector to which a correlator output signal a is input, 2 is an integration circuit, 3 is a level detector that outputs a lock display signal b, and 4 is an integration circuit 2 and a level detector 3 This is a threshold detector for detecting the quality of synchronization. FIG. 5 (a) shows the output of the integration circuit 2 during the synchronization acquisition detection, and the hills indicate when the transmission and reception hopping patterns match. FIG. 5 (b) shows the output of the level detector 3, and illustrates the case where the H level is at the time of good synchronization and the L level is at the time of poor synchronization. FIGS. 6 (a) and 7 (a) show the output of the integrating circuit 2 as in FIG. 5 (a), and FIGS. 6 (b) and 7 (b) also show FIG. 5 (b). 3) shows the output of the level detector 3 as in the case of FIG. FIG. 6 shows a case where the synchronization level is stably maintained, and a case where the reception level fluctuates, for example, when the transmission / reception apparatus shown in FIG. Next, the operation will be described. When the transmission and reception hopping patterns do not match, the search operation continues as a receiver, but the correlator output signal a detected by the envelope detector 1 at that time is integrated by the integration circuit 2, and FIG. When the integrated waveform becomes as shown in a) and exceeds the threshold level 5, synchronization acquisition is detected by the threshold detector 4, and the search operation is stopped. After that, the operation proceeds to the operation of maintaining synchronization. If the reception level fluctuates due to fading or the like while maintaining the synchronization, the threshold detector 4 detects the loss of synchronization as shown in FIG. 7 (b), shifts to the synchronization acquisition mode, and restarts the search operation. Do. [Problems to be Solved by the Invention] Since the conventional synchronous circuit is configured as described above,
The reception level fluctuates due to fading, etc., and the integration circuit 2
7 (a), the threshold detector 4 determines that synchronization has been lost, shifts to the synchronization reacquisition mode, resumes the search operation, and interrupts the call. was there. The present invention has been made in view of such a point,
An object of the present invention is to provide a synchronization circuit that can stably maintain synchronization even when the reception level fluctuates under fading. Means for Solving the Problems The present invention has been made to solve the above problems, and detects synchronization acquisition based on a reception level, and detects synchronization acquisition based on the detection of the synchronization acquisition. In the synchronization circuit of the receiver performing communication based on the above, the synchronization acquisition is detected when the reception level exceeds the threshold level, and the synchronization detection is detected when the reception level falls below the threshold level. A shift detector, a timer for synchronizing that operates in response to the drop in the reception level, and outputs a synchronizing signal for maintaining the synchronization captured by the detection of the synchronizing acquisition, and an output of the synchronizing timer is input. When the drop time of the reception level continues for longer than the output period of the synchronization holding signal, loss of synchronization is detected, and the reception level is reduced. When the drop time is shorter than the output period of the synchronization holding signal, the logic circuit for holding the synchronization captured by the detection of the synchronization capturing by the synchronization holding signal, and the threshold detector detects the synchronization capturing. And a timer control circuit for stopping the operation of the synchronization holding timer to prevent erroneous synchronization from being captured. [Operation] The timer for maintaining synchronization in the present invention operates in response to a drop in the reception level, and maintains synchronization for a certain period of time. Further, the timer control circuit according to the present invention stops the operation of the timer at the time of synchronization acquisition, and prevents erroneous synchronization due to the operation of the timer. [Embodiment] FIG. 1 shows an embodiment of a synchronization circuit according to the present invention.
In FIG. 1, reference numeral 6 denotes a synchronization maintaining timer for maintaining synchronization for a certain period of time even if the reception level fluctuates, 7 a timer control circuit for stopping the operation of the timer during synchronization acquisition, and 8 an output of the level detector 3. A logical sum circuit (OR circuit) for calculating a logical sum with the output of the timer 6. In FIG. 1, the same or corresponding parts as in FIG. 4 are denoted by the same reference numerals. Also, the second
3 shows the case where the reception level fluctuates, and FIG. 3 shows the output of the integration circuit 2 and the output of the level detector 3 in the synchronization acquisition process when the timer control circuit 7 is not provided. Next, the operation will be described. When the transmission and reception hopping patterns do not match, the search operation continues as a receiver, but the correlator output signal a detected by the envelope detector 1 at that time is integrated by the integration circuit 2, and FIG. When the integrated waveform shown in a) is exceeded and the threshold level 5 is exceeded, synchronization acquisition is detected by the threshold detector 4, and the search operation is stopped. After that, the operation proceeds to the operation of maintaining synchronization. The operation so far is exactly the same as the conventional one. FIG. 2 (a) shows a case where the reception level fluctuates due to fading or the like during synchronization holding, and the level drop time from the threshold level 5 is a maximum τ. If the drop time τ is shorter than the setting of the synchronization holding timer 6, the synchronization is stable as shown in FIG. 2 (b). On the other hand, the timer control circuit 7 operates to stop the operation of the timer 6 during synchronization acquisition. Without the timer control circuit 7, the timer 6 operates due to noise or the like that generates the output of the time τ1 shown in FIG. 3, causing erroneous synchronization or extra synchronization time. In the above embodiment, the case of the receiver of the frequency hopping system has been described. However, the receiver of the direct spread system or another spread spectrum communication system may be used, and the same effects as in the above embodiment can be obtained. [Effects of the Invention] As described above, the present invention maintains synchronization for a certain period of time even when the reception level fluctuates, and stops the operation of the timer during synchronization acquisition, thereby maintaining stable synchronization even in a fading situation. However, there is an effect that synchronization acquisition can be reliably performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system diagram showing an embodiment of a synchronous circuit according to the present invention, FIG. 2 and FIG. 3 are waveform diagrams for explaining the operation of the circuit of FIG. 4 is a system diagram showing a conventional synchronous circuit, and FIGS. 5 to 7 are waveform diagrams for explaining the operation of the circuit of FIG. DESCRIPTION OF SYMBOLS 1 ... Envelope detector, 2 ... Integration circuit, 3 ... Level detector, 4 ... Threshold detector, 5 ... Threshold, 6 ... Timer, 7 ... Timer control circuit, 8 …… OR circuit.

Claims (1)

(57) [Claims] In a synchronization circuit of a receiver that detects synchronization acquisition by a reception level and performs communication based on synchronization acquired by the detection of the synchronization acquisition, the synchronization acquisition is detected when the reception level exceeds a threshold level, A threshold detector that detects loss of synchronization when the reception level falls below the threshold level; and a synchronization hold that operates in response to the drop in the reception level and holds the synchronization captured by the detection of synchronization capture. A synchronization holding timer for outputting a signal, and when the output of the synchronization holding timer is input, and when the drop time of the reception level continues longer than the output period of the synchronization holding signal, the synchronization loss is detected and the reception level is detected. Is shorter than the output period of the synchronization holding signal, the synchronization holding signal causes A logic circuit for holding the synchronization captured by the detection of the capture, and when the threshold detector detects the capture of the synchronization, the operation of the timer for maintaining the synchronization is stopped to prevent the capture of the erroneous synchronization. And a timer control circuit.