JPS60182279A - Television receiver - Google Patents

Abstract

PURPOSE:To enhance an added value of a picture function by adding a switching circuit to an address setting circuit of field memory and a written data latch circuit and by displaying either subpicture video signal or a character signal in a subpicture area. CONSTITUTION:When a digital signal processing part outputs a switching signal to a switching control signal line A from a control circuit 34, switching circuits 31-33 become an input mode of data and address data from the circuit 34. When the address data from the circuit 34, data and a latch signal are transferred to an address supply line C, a data supply line B and a latch control line D, respectively, arbitrary data can be written in the prescribed address of field memory. A line for controlling latch circuits 20R, 20G and 20B through the circuit 32 and pulse generator circuit 26 from the control line D is expressed by one line as shown in the circuit diagram, but respective three primary color axses are independently latched and respective chrominance signals can be written in field memories 21R, 21G and 21B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a television receiver, and particularly to a television receiver capable of displaying two or more images simultaneously on one display screen. The present invention relates to a device equipped with a so-called picture-in-picture type image projection means.

[Technical background of the invention]

As an example of image projection using the picture-in-picture method described above, a main screen is projected on the display surface of a display device such as a color picture tube, and a sub-screen is projected on a part of the main screen. There is something I did. Conventionally, as a means of displaying a plurality of images, the video signals of the sub-screen are stored in a field memory using random access memory (hereinafter referred to as RAM), and the two time axes are compressed and read out. By inserting this read signal into a portion of the main screen, a sub-screen can be constructed within the main screen.

As an example of displaying multiple screens as described above, a television receiver is provided with two reception channels.

The signal from one cheese output is displayed as the main screen,
The signal from the output of the other tuner is displayed as a sub-screen (for monitoring the so-called reverse program).

Alternatively, it is conceivable to display an image based on a video signal from a VTR, video disc player, camera, etc. as a sub-screen.

FIG. 1 is a circuit diagram showing the configuration of a conventional picture-in-picture type color television receiver, and its configuration and operation will be briefly explained.

In Figure 1, the signal received by antenna (1) is
The signal is input to the video intermediate frequency amplification and video detection circuit (3) via the video intermediate frequency amplification and video detection circuit (3). The output of this circuit (3) is supplied to an audio detection and amplification circuit (4), and the audio output is given to a speaker (5). Furthermore, the output of circuit (3) is the luminance
The signal is supplied to a color signal separation filter (6), the luminance signal is supplied to a video amplification circuit (7), and the two-color signal is supplied to a color demodulation circuit (8). The output of the video amplification circuit (7) and the output of the color demodulation circuit (8) are supplied to the matrix circuit (9), and the outputs are R (red) and G.
(green) and B (blue) primary color signals are created. Further, the output of the circuit (3) is supplied to a sync separation circuit (10K), and the sync signal is sent to the horizontal oscillation circuit (1t) and the vertical oscillation circuit (1t) at the next stage.
2). Each of these oscillation circuits (11), (1
2) is connected to a deflection yoke (14) via a horizontal/vertical deflection circuit (13). The circuit described above is the configuration of a common color television receiver, and detailed explanation will be omitted.

three primary color signals R2Q from the matrix circuit (9);
B is supplied to the signal switching circuit (15), and this circuit (15
), the three primary color signals JG, B for the main screen are obtained by receiving the signal input from the antenna (1) by the above-mentioned circuit.
and three primary color signals R', G', and B' for the sub-screen, which will be described later.
Switch between and output. The output is then supplied to a picture tube drive circuit (16), and further the image is reproduced on a display device (17)K such as a color picture tube.

The video signal for the sub-screen is then supplied to the video input terminal 18). As the video signal supplied here, a tune signal of a different system from the aforementioned tuner (2) can be considered. The signal supplied to this input terminal (18) is transmitted through a luminance/color signal separation filter (60), a video amplification circuit (70), a color demodulation circuit (SO), a matrix circuit ( 90) by R
, G, B three primary color signals. These three primary color signals are converted into analog/digital converters (hereinafter referred to as small converters) (19B, 19Gp19B), latch circuits (2OR, 20G, 20B), field memories (21R, 21e, 21B), and latch circuits (22R+22G+22B). , and digital fist analog converter (see below, abbreviated as converter)
(23R, 23G, 23B).

is led to the signal switching circuit (15) through the signal.

In the following explanation, the A/b converter (19
R), (19G), and (19B) are collectively referred to simply as the symbol (19). Similarly, the latch circuits (20R), (20a), (20B) are
Expressed as 0).

The memories (21R), (21G), and (21B) are expressed by the symbol (21), and the latch circuits (22R) and (22(
)) , (22B) is expressed by the symbol (22), and D/A
Konota (23R), (23()).

(23B) may also be expressed by the symbol (23).

', /b Nian Haata (19) to Takuai Conver,
! During 2 (23) i, the 1 image signal is converted from an analog signal to a digital signal, written to the field memory (21) as digital data, further read out, and converted from the digital signal to an analog signal again.

When inserting a sub-screen within the main screen area, it is necessary to compress the time axis of the sub-screen image signal, and it is also necessary to match the scanning period of the sub-screen to the scanning period (synchronization signal) of the main screen. , write timing and read timing to the field memory (21) must be considered.
A timing circuit as described below is required.

First, let's look at the write timing circuit.

When converting the three primary color signals for the sub-screen into digital signals using the converter (19)K, the sampling frequency of the converter is determined from the viewpoint of the number of effective pixels. Generally, the sampling frequency is selected to be an integral multiple of the color subcarrier, so a reference signal 3.
58 MH2 is taken out and sampled using a signal multiplied by an integer in a multiplier circuit (82). '／
l) The converted signal is written to the memory (21) via the latch circuit (20), but since only one field is written, the large sword terminal (18) and the K synchronization separation circuit (100)
and the output of this synchronization separation circuit (Zoo) is supplied to the horizontal single-handed oscillation circuits (110) and (120), and the horizontal oscillation circuit (110) and vertical oscillation circuit ( 120) is used to cue the write address. The write address is updated, the write address counter (24) performs cueing and counting, and creates address data.
Field memory (
21) is supplied to the address data input terminal.

The latch circuit (2o) is provided to match the timing of updating the address data with the timing of the output data of the small converter (19), and is provided with a write pulse synchronized with the output of the write address counter (24). Generation circuit (26
) is controlled by the output.

The field memory (21) has a read/write control circuit (
27) is configured so that an arbitrary address is read out during a gap in the data writing process for one field. During main screen scanning, the field memory data is read out at a predetermined position, and the main You can insert a subscreen image into the screen.

The read timing circuit is also configured in the same manner as the write timing circuit, and the color subcarrier frequency is 3.58 from the APC circuit (8a) connected to the color demodulation circuit (8).
Extract the reference signal with the same frequency as MHz.

A multiplier circuit (86) multiplies the signal by an integer to obtain a fundamental frequency signal for read timing. Read address counter (2
8), the fundamental frequency is counted to create address data, and output pulses from the horizontal oscillation circuit (11) and vertical oscillation circuit (12) are used to cue the address data and position the sub-screen insertion. The output of the read address counter (28) is supplied to the address selector (25), and the output of the read address counter (28) is supplied to the field memory (25) at the time of reading.
21) is supplied to the address data input terminal.

On the other hand, the output signal of the read address counter (28) is used to form a read pulse in the read pulse generation circuit (29), and the read/write control circuit (27) is put into the read state, and the field memory (21) The read data is latched for one basic cycle period using a latch circuit (22).

The output of the latch circuit (22) is converted into an analog signal by the alpha converter (23), and the three primary color signals R' and G' are generated.

B' is supplied to the switching circuit (15). The insertion position of the sub-screen into the main screen is set in the read address counter (28) using the horizontal and vertical pulses for the main screen as described above, and a switching signal S is supplied to the signal switching circuit (15). .

FIG. 2 shows a timing diagram of the main and sub-screen video signals resulting from the above-described processing.

In Fig. 2, (,) is the main screen input signal to the signal switching circuit (15), (b) is the sub-screen output signal of the matrix circuit (9o), and (6) is the converter (23R). 23a
).

(23B) and is the output signal from the signal switching circuit (15
), (d) is the signal switching circuit (15)
shows the output signal of

FIG. 3 shows an example of how images are projected and output on a picture tube screen, where (I) is the main screen and (■) is the sub-screen.

[Problems with background technology]

Conventionally, picture-in-picture television receivers such as those described above have been equipped with two reception tuners in the television receiver and have been used, for example, to monitor alternate programs. There is little demand.

Also, VTR is used as the video signal source for the sub-screen.

It is possible to use video discs, cameras, etc.

After all, there is little hope that it will become sufficiently widespread.

Therefore, even if a picture-in-picture function is provided, its added value is low.

[Purpose of the invention]

In view of the above points, the present invention utilizes the picture-in-picture function for other purposes, and makes it an important function inherent in a television receiver, and furthermore uses the picture-in-picture function for each video signal source as described above. It can also be used as a picture-in-picture monitor, and the function that used to be displayed on the screen by superimposing channel numbers etc. on the video signal using a character generator is used for picture-in-picture. Field memory to video RAM
To provide a television receiver capable of displaying various television reception modes in a sub-screen.

[Summary of the invention]

The present invention includes a first signal processing means for projecting a first image based on a video signal from a first video signal source on a display surface of a display device such as a picture tube.

Means for displaying a second image in synchronization with the signal from the first video signal source, the second image being projected by the video signal from the second video signal source. a second signal processing means comprising a field memory for time-base compressing data;

character data generating means serving as a signal source for displaying characters such as channel numbers on the display surface of the display device;

a switching means for selectively switching and supplying data from the video signal from the second video signal source or data from the character data generating means as write data to the field memory;

Controls writing of data to and reading of data from the field memory, and displays either an image based on a video signal from the second video signal source or the character as a second image on the display device. This is a television receiver comprising means for selectively displaying images.

[Embodiments of the invention]

The television receiver of the present invention will be explained below with reference to FIG.

In FIG. 4, parts that perform the same functions as those in FIG. 1 are denoted by the same reference numerals, and redundant explanation will be omitted. The feature of the present invention lies in the addition of the circuit shown within the dotted line frame (30), including the A/D converter (19R, 19()).

Switching circuits (31R, 31G, 31B) are provided between the latch circuits (2OR, 20, 20B) and the latch circuits (2OR, 20, 20B). (In addition, these (31R), (31G
) and (31B) may be collectively referred to simply by the symbol (31) in the following description. ) Also a write address counter (24) and a write pulse generation circuit (26)
A switching circuit (32) is provided between the write address counter (24) and the address selector (25), and a switching circuit (33) is provided between the write address counter (24) and the address selector (25). Each of these switching circuits (31).

(32) and (33) are connected to a control circuit (34) such as a microphone q processor, and the switching control signal line (A) from this control circuit (34) is connected to all switching circuits (31), (
32), (33) are coupled and further connected to the latch control line (D
) is coupled to the switching circuit (32).

The part into which the switching circuits (31), (32), and (33) are inserted is a digital signal processing section, and the components of the switching circuit that are specifically used may be general-purpose logic ICs, but the frequencies of the signals handled are comparable. It is better to use TTL gates because of their high accuracy. Also, memory write data and address data have a relatively large number of bits.

It is preferable to use a TTL bus drive or a TTL multiplexer as the changeover switch.

In the above configuration, when a switching signal is output from the control circuit (34) to the switching control signal line (A), the switching circuit (
31), (32), and (33) are all control circuits (3
4) enters the data and address data input mode. Transfers the write address data from the control circuit (34) to the address supply line (C), and at the same time transfers the write address data to the data supply line (C).
When data and latch signals are transferred to B) and latch control line (D), respectively, the latch circuits (2OR), (20G), and (20B) are controlled through the field control (32) and write pulse generation circuit (26). The line is represented by a single line on the circuit diagram, but if each of the three primary color axes can be latched independently, or if data supply lines (B) are provided on each side of the three primary color axes, each color signal can be Field memory (21R), (21()),
(21B).

If such an operation is performed, the field memory (21)
operates as a video RAM in which any character can be written to any address, and any character can be displayed in the sub-screen area.

The control circuit (34) determines what character to display.
It depends on the software, for example, if the control circuit (34) is shared for receiving a remote control signal for a television receiver or for controlling a channel selection circuit, it can be used for displaying a channel number when selecting two channels.

FIG. 5 shows an example in which the above-mentioned remote control signal reception and channel selection circuit control are commonly used, in which a key manual means (35) for causing the control circuit (34) to perform operations such as channel switching, and remote control light receiving circuit (36)
are connected to each other. and key human power means (35)
Alternatively, the data is sent to the control circuit (34) to select a predetermined channel according to a command from the remote control light receiving circuit (36).
), and the tuning voltage is further supplied to the tuner (2) via the tuning voltage generation circuit (37).

According to FIG. 5, when a key operation (or remote control operation) is performed to select a predetermined channel, a predetermined tuning voltage is supplied to the tuner (2), and the selected channel is displayed on the main screen. image is displayed. Furthermore, the signal line (A) is connected from the control circuit (34) in response to the channel selection operation.
A switching signal is supplied to the data supply line (B), data representing a channel number is supplied to the data supply line (B), and the channel number is displayed on the sub-screen. In addition, the channel number will be displayed only for a predetermined period of time after the channel selection operation.

Alternatively, the control circuit (34) may be programmed so that the channel can be displayed for a predetermined period of time by key operation when it is desired to check which channel the image is currently being received.

In addition, character display on the sub-screen is not limited to the above-mentioned channel display, but also displays other reception conditions such as reception mode (for example, a mode indicating whether it is stereo broadcasting, bilingual broadcasting, etc.)
may be displayed, or the volume level or brightness level may be displayed when the volume or brightness is adjusted by key operation. Alternatively, it may be used as a character display to confirm the type of external input, such as whether the signal input to the input terminal (18) is from a VTR or a video disc player. Conceivable.

In this way, information representing the reception status can be displayed on the sub-screen.

In the above embodiment, the digital signal processing part for sub-screen time axis compression is performed using R, G, and B primary color signals, and A/
We have shown an example using three b converters and three D/A converters;
/b conversion and viewing4. It is also possible to perform the conversion and provide a JG, B matrix circuit after the D/A conversion. At this time, if the luminance signal and the color difference signal are time-division multiplexed based on the frequency bandwidth ratio of the luminance signal and the color difference signal, and VD conversion is performed, it is possible to reduce the number of A/1) converters to one. In practical terms, this method is advantageous in terms of cost. In this case, it can be expected that the address map of the field memory will be somewhat different from that of the previous embodiment, and that the data of the luminance signal and color difference signal must be individually transferred from the control circuit (34) to the field memory. Although it is complicated.

This also depends only on the software of the control circuit (34), and the basic configuration can be realized in the same manner as in the previous embodiment.

Also, in the above explanation, it was stated that two screens, the main screen and the sub screen, are displayed, but it is possible to prevent the viewer from inserting the sub screen and display only the main screen in the entire screen if necessary. A switching means may also be provided.

〔Effect of the invention〕

In the picture-in-picture type television receiver according to the present invention, the address setting circuit part and the write data latch circuit part of the field memory provided for time axis compression of the video signal of the sub-screen are switched. By adding a circuit.

A signal created by a sub-screen video signal and a micro bra processor, etc. in the sub-screen area. Any of the lid signals can be freely selected and displayed. In particular, by displaying information that is highly important for the functionality of the television receiver (for example, channel number, etc.) as a sub-screen image based on character signals, it is possible to make the television receiver multi-functional. Yes, the added value of the picture-in-picture function is high.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional example of a picture-in-picture color television receiver. FIG. 2 is a waveform diagram showing the video signal waveform of each part according to the configuration of FIG. 1, FIG. 3 is an explanatory diagram showing an example of display on a picture tube screen, and FIG. FIG. 5 is a schematic diagram showing the basic configuration of a color television receiver, and FIG. 5 is a circuit diagram showing an embodiment of the present invention. 19R, 19G, 19B...A/b converter. 21R, 21G, 21B...Field memory. 23R, 23G, 23B... Takumi t converter. 25...Address selector. 26...Write pulse generation circuit. 29...Read pulse generation circuit. 31R, 31G, 3113, 32, 33...
・Switching circuit. 34...Control circuit (microprocessor).

Claims (3)

[Claims] (1) A display device that projects an image on a display surface. 1st. and a second video signal source. a first signal processing means for projecting a first image based on a video signal from the first video signal source on the display surface; means for displaying a second image in synchronization with a signal from the first video signal source, the video signal from the second video signal source; and second signal processing means comprising a field memory for time-base compressing data. Character data generating means serving as a signal source for projecting a character on the display surface of the display device. a switching means for selectively switching and supplying data from the video signal from the second video signal source or data from the character data generating means as write data to the field memory; Controls writing of data to and reading of data from the field memory, and displays either an image based on a video signal from the second video signal source or the character as a second image on the display device. A television receiver comprising means for selectively displaying images. (2) The television receiver according to claim 1, wherein the character data generating means is a circuit that generates data for displaying information representing a reception state. (3) The television according to claim 1, wherein the character data generating means is a circuit that generates data for displaying a channel number in response to a channel switching operation. receiver.